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-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini33
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini79
2 files changed, 59 insertions, 53 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
index 250783f94..459f492af 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -108,7 +109,7 @@ dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
@@ -122,7 +123,6 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
[system.cpu.dcache]
type=BaseCache
@@ -130,10 +130,11 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -144,7 +145,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -553,10 +553,11 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -567,7 +568,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -602,10 +602,11 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
-is_top_level=false
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -616,7 +617,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -635,8 +635,11 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
@@ -651,6 +654,7 @@ eventq_index=0
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing
+drivers=
egid=100
env=
errout=cerr
@@ -659,6 +663,7 @@ eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
@@ -688,11 +693,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
@@ -723,7 +731,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
@@ -732,6 +740,7 @@ clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index aa4b312c2..4e01cb733 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -159,7 +159,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -170,7 +170,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -206,9 +205,9 @@ opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=IntAlu
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
@@ -220,16 +219,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=IntMult
opLat=3
+pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
opClass=IntDiv
opLat=20
+pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
@@ -241,23 +240,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=FloatAdd
opLat=2
+pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=FloatCmp
opLat=2
+pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=FloatCvt
opLat=2
+pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
@@ -269,23 +268,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=FloatMult
opLat=4
+pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
-issueLat=12
opClass=FloatDiv
opLat=12
+pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
-issueLat=24
opClass=FloatSqrt
opLat=24
+pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=MemRead
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
@@ -311,142 +310,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdAdd
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdAddAcc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdAlu
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdCmp
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdCvt
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdMisc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdMult
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdMultAcc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdShift
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdShiftAcc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdSqrt
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatAdd
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatAlu
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatCmp
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatCvt
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatDiv
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatMisc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatMult
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatMultAcc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatSqrt
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
@@ -458,9 +457,9 @@ opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=MemWrite
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
@@ -472,16 +471,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=MemRead
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=MemWrite
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
@@ -493,9 +492,9 @@ opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
-issueLat=3
opClass=IprAccess
opLat=3
+pipelined=false
[system.cpu.icache]
type=BaseCache
@@ -507,7 +506,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -518,7 +517,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -557,7 +555,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
-is_top_level=false
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -568,7 +566,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -612,7 +609,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
kvmInSE=false