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-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini877
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr7
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout29
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt795
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini825
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr7
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout29
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out276
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin17
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl111
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl22
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav18
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv219
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf29
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt1074
15 files changed, 0 insertions, 4015 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
deleted file mode 100644
index 35828777f..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
+++ /dev/null
@@ -1,877 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=MinorCPU
-children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=system.cpu.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
-executeMemoryIssueLimit=1
-executeMemoryWidth=0
-executeSetTraceTimeOnCommit=true
-executeSetTraceTimeOnIssue=false
-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.executeFuncUnits]
-type=MinorFUPool
-children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
-eventq_index=0
-funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
-
-[system.cpu.executeFuncUnits.funcUnits0]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits0.timings
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits0.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits1]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits1.timings
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits1.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits2]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits2.timings
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntMult
-
-[system.cpu.executeFuncUnits.funcUnits2.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mul
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
-srcRegsRelativeLats=0
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits3]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=9
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
-opLat=9
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntDiv
-
-[system.cpu.executeFuncUnits.funcUnits4]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
-opLat=6
-timings=system.cpu.executeFuncUnits.funcUnits4.timings
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses]
-type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAddAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShift
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShiftAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.timings]
-type=MinorFUTiming
-children=opClasses
-description=FloatSimd
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits5]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
-opLat=1
-timings=system.cpu.executeFuncUnits.funcUnits5.timings
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=MemRead
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=MemWrite
-
-[system.cpu.executeFuncUnits.funcUnits5.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mem
-eventq_index=0
-extraAssumedLat=2
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
-srcRegsRelativeLats=1
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits6]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
-opLat=1
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=IprAccess
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=InstPrefetch
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr
deleted file mode 100755
index e0bca4e4e..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr
+++ /dev/null
@@ -1,7 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout
deleted file mode 100755
index 4b089cf00..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout
+++ /dev/null
@@ -1,29 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:43
-gem5 executing on e108600-lin, pid 28042
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/minor-timing
-
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 53437621500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
deleted file mode 100644
index 40657583a..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
+++ /dev/null
@@ -1,795 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.053438 # Number of seconds simulated
-sim_ticks 53437621500 # Number of ticks simulated
-final_tick 53437621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 468238 # Simulator instruction rate (inst/s)
-host_op_rate 468238 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 272260061 # Simulator tick rate (ticks/s)
-host_mem_usage 257916 # Number of bytes of host memory used
-host_seconds 196.27 # Real time elapsed on the host
-sim_insts 91903089 # Number of instructions simulated
-sim_ops 91903089 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory
-system.physmem.bytes_read::total 340608 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 202880 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 202880 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 3796576 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2577360 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6373936 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 3796576 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 3796576 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 3796576 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2577360 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6373936 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5322 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 340608 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 340608 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 468 # Per bank write bursts
-system.physmem.perBankRdBursts::1 295 # Per bank write bursts
-system.physmem.perBankRdBursts::2 308 # Per bank write bursts
-system.physmem.perBankRdBursts::3 524 # Per bank write bursts
-system.physmem.perBankRdBursts::4 224 # Per bank write bursts
-system.physmem.perBankRdBursts::5 238 # Per bank write bursts
-system.physmem.perBankRdBursts::6 222 # Per bank write bursts
-system.physmem.perBankRdBursts::7 289 # Per bank write bursts
-system.physmem.perBankRdBursts::8 254 # Per bank write bursts
-system.physmem.perBankRdBursts::9 282 # Per bank write bursts
-system.physmem.perBankRdBursts::10 254 # Per bank write bursts
-system.physmem.perBankRdBursts::11 261 # Per bank write bursts
-system.physmem.perBankRdBursts::12 410 # Per bank write bursts
-system.physmem.perBankRdBursts::13 344 # Per bank write bursts
-system.physmem.perBankRdBursts::14 501 # Per bank write bursts
-system.physmem.perBankRdBursts::15 448 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 53437285500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 5322 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 4860 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 449 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 981 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 347.009174 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 213.710292 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 326.985210 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 311 31.70% 31.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 198 20.18% 51.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 103 10.50% 62.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 115 11.72% 74.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 57 5.81% 79.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 30 3.06% 82.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 30 3.06% 86.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 26 2.65% 88.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 111 11.31% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 981 # Bytes accessed per row activation
-system.physmem.totQLat 132267250 # Total ticks spent queuing
-system.physmem.totMemAccLat 232054750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 24852.92 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 43602.92 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 6.37 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 6.37 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.05 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 4338 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.51 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 10040827.79 # Average gap between requests
-system.physmem.pageHitRate 81.51 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3348660 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1772265 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 18335520 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 173328480.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 64638000 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 9138240 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 468346770 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 218747040 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 12435217200 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 13392872175 # Total energy per rank (pJ)
-system.physmem_0.averagePower 250.626273 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 53271099000 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 16953500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 73680000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 51675337000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 569631000 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 74922500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 1027097500 # Time in different power states
-system.physmem_1.actEnergy 3677100 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1950630 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 19663560 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 191767680.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 68393160 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 9924480 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 510653310 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 251520000 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 12393371550 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 13451137230 # Total energy per rank (pJ)
-system.physmem_1.averagePower 251.716611 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 53261175500 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 18732000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 81534000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 51486455000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 654968250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 76126500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 1119805750 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 11450652 # Number of BP lookups
-system.cpu.branchPred.condPredicted 8210942 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 765019 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 6085116 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 5320742 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 87.438629 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1176677 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 2073 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 20415218 # DTB read hits
-system.cpu.dtb.read_misses 43383 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 20458601 # DTB read accesses
-system.cpu.dtb.write_hits 6579912 # DTB write hits
-system.cpu.dtb.write_misses 276 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 6580188 # DTB write accesses
-system.cpu.dtb.data_hits 26995130 # DTB hits
-system.cpu.dtb.data_misses 43659 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 27038789 # DTB accesses
-system.cpu.itb.fetch_hits 22968644 # ITB hits
-system.cpu.itb.fetch_misses 90 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 22968734 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 53437621500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 106875243 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 91903089 # Number of instructions committed
-system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 2191333 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.162912 # CPI: cycles per instruction
-system.cpu.ipc 0.859910 # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction
-system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction
-system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction
-system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction
-system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction
-system.cpu.op_class_0::MemRead 19433628 21.15% 92.31% # Class of committed instruction
-system.cpu.op_class_0::MemWrite 6424338 6.99% 99.30% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite 76788 0.08% 100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::total 91903089 # Class of committed instruction
-system.cpu.tickCycles 103792204 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 3083039 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 157 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1447.203649 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 26572187 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11910.437920 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1447.203649 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.353321 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.353321 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 53153435 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 53153435 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 20074003 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 20074003 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 6498184 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6498184 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 26572187 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 26572187 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 26572187 # number of overall hits
-system.cpu.dcache.overall_hits::total 26572187 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2919 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2919 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3415 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3415 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3415 # number of overall misses
-system.cpu.dcache.overall_misses::total 3415 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 58822000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 58822000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 274731500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 274731500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 333553500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 333553500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 333553500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 333553500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 20074499 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 20074499 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 26575602 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 26575602 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 26575602 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 26575602 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000449 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000449 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 118592.741935 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 118592.741935 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94118.362453 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 94118.362453 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 97673.060029 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 97673.060029 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
-system.cpu.dcache.writebacks::total 107 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1176 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1176 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1184 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1184 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1184 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1184 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1743 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2231 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 57888500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 57888500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 165966000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 165966000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 223854500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 223854500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 223854500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 223854500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 118623.975410 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 118623.975410 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95218.588640 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95218.588640 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 28831.975238 # average overall miss latency
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27832.038406 # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1743 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1743 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 15830 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 488 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45525 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4619 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 50144 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1900480 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149632 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2050112 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 18061 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 18061 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 18061 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 30013500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 23745000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3346500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 5322 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 3605 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1717 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1717 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 3605 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10644 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 10644 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 340608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 5322 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 5322 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 5322 # Request fanout histogram
-system.membus.reqLayer0.occupancy 6424500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 28175000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
deleted file mode 100644
index f4beb67d4..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ /dev/null
@@ -1,825 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-default_p_state=UNDEFINED
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=20
-pipelined=false
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
-
-[system.cpu.fuPool.FUList4.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
deleted file mode 100755
index e0bca4e4e..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
+++ /dev/null
@@ -1,7 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
deleted file mode 100755
index e5a3bf839..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ /dev/null
@@ -1,29 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:45
-gem5 executing on e108600-lin, pid 28064
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/o3-timing
-
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 21954917500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out
deleted file mode 100644
index 98777e0af..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out
+++ /dev/null
@@ -1,276 +0,0 @@
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
deleted file mode 100644
index 62b922e4e..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
+++ /dev/null
@@ -1,17 +0,0 @@
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
deleted file mode 100644
index bdc569e39..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
+++ /dev/null
@@ -1,11 +0,0 @@
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
deleted file mode 100644
index 6e2601e82..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
+++ /dev/null
@@ -1,2 +0,0 @@
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
deleted file mode 100644
index 04c8e9935..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
+++ /dev/null
@@ -1,18 +0,0 @@
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
deleted file mode 100644
index 9dd68ecdb..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
+++ /dev/null
@@ -1,19 +0,0 @@
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
deleted file mode 100644
index a4c2eac35..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
+++ /dev/null
@@ -1,29 +0,0 @@
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
deleted file mode 100644
index bb93c695e..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ /dev/null
@@ -1,1074 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.021955 # Number of seconds simulated
-sim_ticks 21954917500 # Number of ticks simulated
-final_tick 21954917500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 353144 # Simulator instruction rate (inst/s)
-host_op_rate 353144 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 92103562 # Simulator tick rate (ticks/s)
-host_mem_usage 259964 # Number of bytes of host memory used
-host_seconds 238.37 # Real time elapsed on the host
-sim_insts 84179709 # Number of instructions simulated
-sim_ops 84179709 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory
-system.physmem.bytes_read::total 334464 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 8923012 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 6311115 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15234127 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 8923012 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 8923012 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 8923012 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 6311115 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 15234127 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5226 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 5226 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 334464 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 334464 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 469 # Per bank write bursts
-system.physmem.perBankRdBursts::1 292 # Per bank write bursts
-system.physmem.perBankRdBursts::2 302 # Per bank write bursts
-system.physmem.perBankRdBursts::3 523 # Per bank write bursts
-system.physmem.perBankRdBursts::4 220 # Per bank write bursts
-system.physmem.perBankRdBursts::5 223 # Per bank write bursts
-system.physmem.perBankRdBursts::6 218 # Per bank write bursts
-system.physmem.perBankRdBursts::7 288 # Per bank write bursts
-system.physmem.perBankRdBursts::8 239 # Per bank write bursts
-system.physmem.perBankRdBursts::9 278 # Per bank write bursts
-system.physmem.perBankRdBursts::10 249 # Per bank write bursts
-system.physmem.perBankRdBursts::11 251 # Per bank write bursts
-system.physmem.perBankRdBursts::12 395 # Per bank write bursts
-system.physmem.perBankRdBursts::13 338 # Per bank write bursts
-system.physmem.perBankRdBursts::14 492 # Per bank write bursts
-system.physmem.perBankRdBursts::15 449 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 21954815500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 5226 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 3223 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1200 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 260 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 861 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 385.932636 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 229.340491 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 360.649518 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 261 30.31% 30.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 173 20.09% 50.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 93 10.80% 61.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 57 6.62% 67.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 37 4.30% 72.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 30 3.48% 75.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 47 5.46% 81.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 33 3.83% 84.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 130 15.10% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 861 # Bytes accessed per row activation
-system.physmem.totQLat 128746000 # Total ticks spent queuing
-system.physmem.totMemAccLat 226733500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 26130000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 24635.67 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 43385.67 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 15.23 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 15.23 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.12 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 4356 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.35 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 4201074.53 # Average gap between requests
-system.physmem.pageHitRate 83.35 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3034500 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1593900 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 18099900 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 118625520.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 48811380 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 6176640 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 312556080 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 154176960 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 5001436845 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 5664547785 # Total energy per rank (pJ)
-system.physmem_0.averagePower 258.008156 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 21831003750 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 11536500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 50426000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 20744771750 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 401491250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 61308000 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 685384000 # Time in different power states
-system.physmem_1.actEnergy 3177300 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1673595 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 19213740 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 106332720.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 46621440 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 5256960 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 301076850 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 131936160 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 5018107080 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 5633395845 # Total energy per rank (pJ)
-system.physmem_1.averagePower 256.589251 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 21838957750 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 9258500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 45178000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 20835144000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 343577000 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 61468500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 660291500 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 16102182 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11688137 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 930988 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8963257 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7508303 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 83.767575 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1594537 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 466 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 29363 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 3639 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 24064359 # DTB read hits
-system.cpu.dtb.read_misses 206311 # DTB read misses
-system.cpu.dtb.read_acv 4 # DTB read access violations
-system.cpu.dtb.read_accesses 24270670 # DTB read accesses
-system.cpu.dtb.write_hits 7168837 # DTB write hits
-system.cpu.dtb.write_misses 1192 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 7170029 # DTB write accesses
-system.cpu.dtb.data_hits 31233196 # DTB hits
-system.cpu.dtb.data_misses 207503 # DTB misses
-system.cpu.dtb.data_acv 4 # DTB access violations
-system.cpu.dtb.data_accesses 31440699 # DTB accesses
-system.cpu.itb.fetch_hits 15932695 # ITB hits
-system.cpu.itb.fetch_misses 79 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 15932774 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 21954917500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 43909836 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 16643979 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 137979397 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16102182 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9128564 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 26000321 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1939876 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2307 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 15932695 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 367713 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 43616730 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.163451 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.433365 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 19436456 44.56% 44.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2618537 6.00% 50.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1330059 3.05% 53.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1934096 4.43% 58.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 3001834 6.88% 64.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1292274 2.96% 67.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1355703 3.11% 71.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 886638 2.03% 73.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 11761133 26.96% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 43616730 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.366710 # Number of branch fetches per cycle
-system.cpu.fetch.rate 3.142335 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 12867029 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8250930 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19434015 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 2106147 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 958609 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2654207 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 11848 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 132149793 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 49699 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 958609 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13986200 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4658485 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 10631 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 20305693 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 3697112 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 128776944 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 70815 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2027533 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 1361651 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 79521 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 94599397 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 167333600 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 159779432 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 7554167 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 26172036 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 950 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 8272242 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26904484 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 8704450 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3461355 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1614052 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 111855473 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1918 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 99762246 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 119439 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 27677681 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 21095832 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1529 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 43616730 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.287247 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.099564 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 11270720 25.84% 25.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 7659760 17.56% 43.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7470187 17.13% 60.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5700495 13.07% 73.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4466514 10.24% 83.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2981046 6.83% 90.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2041941 4.68% 95.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1170841 2.68% 98.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 855226 1.96% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 43616730 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 484010 20.07% 20.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 20.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 20.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 34926 1.45% 21.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 12192 0.51% 22.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 1012503 41.99% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 682717 28.32% 92.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 160804 6.67% 99.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 21053 0.87% 99.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 2406 0.10% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 60662676 60.81% 60.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2847523 2.85% 64.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2443321 2.45% 66.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 314198 0.31% 67.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 24115562 24.17% 91.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 7190219 7.21% 99.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 739060 0.74% 99.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 78236 0.08% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 99762246 # Type of FU issued
-system.cpu.iq.rate 2.271979 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2411149 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.024169 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 229977416 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 129921960 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 89757276 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 15694394 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 9653681 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 7189481 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 93785924 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 8387464 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1923320 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6908286 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11342 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 40947 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2203347 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 42864 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1503 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 958609 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 3613912 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 479107 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 122779790 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 241415 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26904484 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 8704450 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1918 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 38391 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 434865 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 40947 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 502384 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1034333 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 98436741 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 24271214 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1325505 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 10922399 # number of nop insts executed
-system.cpu.iew.exec_refs 31441282 # number of memory reference insts executed
-system.cpu.iew.exec_branches 12471732 # Number of branches executed
-system.cpu.iew.exec_stores 7170068 # Number of stores executed
-system.cpu.iew.exec_rate 2.241792 # Inst execution rate
-system.cpu.iew.wb_sent 97645487 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 96946757 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 66976137 # num instructions producing a value
-system.cpu.iew.wb_consumers 94960144 # num instructions consuming a value
-system.cpu.iew.wb_rate 2.207860 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.705308 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 30878503 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 919659 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 39122931 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.349084 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.919383 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 14724541 37.64% 37.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 8532800 21.81% 59.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3880104 9.92% 69.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 1909784 4.88% 74.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1376640 3.52% 77.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1034511 2.64% 80.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 692868 1.77% 82.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 729092 1.86% 84.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6242591 15.96% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 39122931 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 91903055 # Number of instructions committed
-system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 26497301 # Number of memory references committed
-system.cpu.commit.loads 19996198 # Number of loads committed
-system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 10240685 # Number of branches committed
-system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1029620 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 51001453 55.49% 63.90% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 19433618 21.15% 92.31% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 6424318 6.99% 99.30% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 76785 0.08% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction
-system.cpu.commit.bw_lim_events 6242591 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 155660858 # The number of ROB reads
-system.cpu.rob.rob_writes 250112359 # The number of ROB writes
-system.cpu.timesIdled 4774 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 293106 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 84179709 # Number of Instructions Simulated
-system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.521620 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.521620 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.917104 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.917104 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 133010551 # number of integer regfile reads
-system.cpu.int_regfile_writes 72904644 # number of integer regfile writes
-system.cpu.fp_regfile_reads 6263409 # number of floating regfile reads
-system.cpu.fp_regfile_writes 6178123 # number of floating regfile writes
-system.cpu.misc_regfile_reads 719113 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 158 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1457.034872 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 28588531 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 12734.312249 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1457.034872 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.355721 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.355721 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 57198427 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 57198427 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 22095438 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 22095438 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 6492623 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6492623 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 28588061 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 28588061 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 28588061 # number of overall hits
-system.cpu.dcache.overall_hits::total 28588061 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1079 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1079 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 8480 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 8480 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 9559 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9559 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9559 # number of overall misses
-system.cpu.dcache.overall_misses::total 9559 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 87318000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 87318000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 649645257 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 649645257 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 106000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 106000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 736963257 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 736963257 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 736963257 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 736963257 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 22096517 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 22096517 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 28597620 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 28597620 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 28597620 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 28597620 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80924.930491 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 80924.930491 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76609.110495 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76609.110495 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 106000 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 106000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 77096.271263 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 77096.271263 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 43101 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 174 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 350 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 123.145714 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 108 # number of writebacks
-system.cpu.dcache.writebacks::total 108 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 564 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 564 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6751 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6751 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7315 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7315 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7315 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7315 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1729 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1729 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47711000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 47711000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177283495 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 177283495 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224994495 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 224994495 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224994495 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 224994495 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002123 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002123 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92642.718447 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92642.718447 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102535.277617 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102535.277617 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 105000 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 105000 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100264.926471 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 100264.926471 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100264.926471 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 100264.926471 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 9511 # number of replacements
-system.cpu.icache.tags.tagsinuse 1600.395362 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 15918262 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 11449 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 1390.362652 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1600.395362 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.781443 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.781443 # Average percentage of cache occupancy
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33078.427948 # average overall mshr miss latency
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-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 11965 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 9511 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1729 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1729 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 11450 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 516 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32410 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4648 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 37058 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341440 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 1492032 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 13695 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 13695 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 13695 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 21301000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 17173500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 5226 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 3523 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1703 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1703 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 3523 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 5226 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 5226 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 5226 # Request fanout histogram
-system.membus.reqLayer0.occupancy 6271000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 27424000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
-
----------- End Simulation Statistics ----------