diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 818 |
1 files changed, 410 insertions, 408 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 31e90a11a..91b6b6b0a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.130383 # Number of seconds simulated -sim_ticks 130382890500 # Number of ticks simulated -final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132486 # Number of seconds simulated +sim_ticks 132485848500 # Number of ticks simulated +final_tick 132485848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 369340 # Simulator instruction rate (inst/s) -host_op_rate 389344 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 279457902 # Simulator tick rate (ticks/s) -host_mem_usage 317800 # Number of bytes of host memory used -host_seconds 466.56 # Real time elapsed on the host +host_inst_rate 159309 # Simulator instruction rate (inst/s) +host_op_rate 167937 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 122483807 # Simulator tick rate (ticks/s) +host_mem_usage 270152 # Number of bytes of host memory used +host_seconds 1081.66 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory -system.physmem.bytes_read::total 247424 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 247552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138240 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1059280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 838392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1897672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1059280 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1059280 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1059280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 838392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1897672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3866 # Number of read requests accepted +system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1043432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 825084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1868517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 825084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1868517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3868 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 247424 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 247552 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 247424 # Total read bytes from the system interface side +system.physmem.bytesReadSys 247552 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -52,12 +52,12 @@ system.physmem.perBankRdBursts::6 273 # Pe system.physmem.perBankRdBursts::7 222 # Per bank write bursts system.physmem.perBankRdBursts::8 248 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts -system.physmem.perBankRdBursts::10 295 # Per bank write bursts +system.physmem.perBankRdBursts::10 296 # Per bank write bursts system.physmem.perBankRdBursts::11 200 # Per bank write bursts system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts -system.physmem.perBankRdBursts::15 204 # Per bank write bursts +system.physmem.perBankRdBursts::15 205 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 130382796000 # Total gap between requests +system.physmem.totGap 132485754500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3866 # Read request sizes (log2) +system.physmem.readPktSize::6 3868 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 268.939891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.781102 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 276.529935 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 273 29.84% 29.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 347 37.92% 67.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 83 9.07% 76.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 59 6.45% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 3.83% 87.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 24 2.62% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 16 1.75% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20 2.19% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 58 6.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 915 # Bytes accessed per row activation -system.physmem.totQLat 27071500 # Total ticks spent queuing -system.physmem.totMemAccLat 99559000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7002.46 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 929 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 264.680301 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.140302 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 275.634226 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 285 30.68% 30.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 355 38.21% 68.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 86 9.26% 78.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 48 5.17% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 3.77% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 24 2.58% 89.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21 2.26% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 19 2.05% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 56 6.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 929 # Bytes accessed per row activation +system.physmem.totQLat 30291250 # Total ticks spent queuing +system.physmem.totMemAccLat 102816250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7831.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25752.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26581.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage @@ -217,56 +217,56 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2948 # Number of row buffer hits during reads +system.physmem.readRowHits 2934 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33725503.36 # Average gap between requests -system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3144960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1716000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 34251746.25 # Average gap between requests +system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3182760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1736625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3562127505 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75103936500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 87202954965 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.831686 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 124939990750 # Time in different power states -system.physmem_0.memoryStateTime::REF 4353700000 # Time in different power states +system.physmem_0.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3626588520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 76308756000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88609573905 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.835850 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126944435250 # Time in different power states +system.physmem_0.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1087339250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1115186250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3764880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2054250 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3544157970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.803682 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states -system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states +system.physmem_1.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3635416395 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 76301020500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88609288305 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.833625 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126931702750 # Time in different power states +system.physmem_1.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1127787750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 49622074 # Number of BP lookups -system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups -system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 49693791 # Number of BP lookups +system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 130382890500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 260765781 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 264971697 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.513284 # CPI: cycles per instruction -system.cpu.ipc 0.660815 # IPC: instructions per cycle +system.cpu.cpi 1.537692 # CPI: cycles per instruction +system.cpu.ipc 0.650325 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction @@ -432,18 +432,18 @@ system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction -system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 256731546 # Number of cycles that the object actually ticked +system.cpu.idleCycles 8240151 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.678714 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40755400 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22504.362231 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.678714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336591 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336591 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -451,43 +451,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362636 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362636 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40709197 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40709197 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40709659 # number of overall hits -system.cpu.dcache.overall_hits::total 40709659 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40710124 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40710124 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40710586 # number of overall hits +system.cpu.dcache.overall_hits::total 40710586 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1651 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1651 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses -system.cpu.dcache.overall_misses::total 2441 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59629000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59629000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126003000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126003000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 185632000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 185632000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 185632000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 185632000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28347350 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28347350 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2403 # number of overall misses +system.cpu.dcache.overall_misses::total 2403 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55315500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55315500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127182500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127182500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 182498000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 182498000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 182498000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 182498000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) @@ -496,28 +496,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40711637 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40711637 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40712100 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40712100 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000134 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76078.688525 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73655.792277 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73655.792277 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77033.615990 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77033.615990 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.518734 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75977.518734 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75945.900957 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75945.900957 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -526,14 +526,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 552 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 552 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 592 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 592 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 592 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 592 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses @@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52555500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52555500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85213000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85213000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52182500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52182500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86133500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86133500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137768500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 137768500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137838500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 137838500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138316000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 138316000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138386000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 138386000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -564,334 +564,336 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73393.108298 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73393.108298 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78374.431301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78374.431301 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2881 # number of replacements -system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76417.679558 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76417.679558 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76414.135837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76414.135837 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2864 # number of replacements +system.cpu.icache.tags.tagsinuse 1424.966015 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 70941364 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15213.674459 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.966015 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses -system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits -system.cpu.icache.overall_hits::total 70779397 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4678 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4678 # number of overall misses -system.cpu.icache.overall_misses::total 4678 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 198432500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 198432500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 198432500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 198432500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 198432500 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42418.234288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43087.371355 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43087.371355 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43087.371355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43087.371355 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2000.553914 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5137 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.844524 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 489.811820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.714154 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 489.810148 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046012 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061021 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2783 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::total 0.061052 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 4664 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6489 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4678 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6475 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4664 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6489 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6475 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461950 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461950 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886236 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886236 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461950 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.950856 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.598397 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461950 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.950856 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.598397 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75724.568633 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463551 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463551 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463551 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.951408 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.600000 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77359.761687 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77359.761687 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75229.648474 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75229.648474 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79525.316456 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79525.316456 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76526.640927 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76526.640927 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 15 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2159 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2159 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2161 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2161 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2161 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3869 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72569000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72569000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 138134000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 138134000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43490000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43490000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138134000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116059000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 254193000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138134000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116059000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 254193000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73489500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73489500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140980000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140980000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43051500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43051500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140980000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116541000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 257521000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140980000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116541000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 257521000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461522 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463336 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.595932 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.595932 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67359.761687 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67359.761687 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65238.315595 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65238.315595 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69775.526742 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69775.526742 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4664 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12191 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 15900 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15855 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 600640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 598656 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6489 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.071197 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.257174 # Request fanout histogram +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 6475 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.072896 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.259985 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6027 92.88% 92.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 462 7.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6003 92.71% 92.71% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 472 7.29% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6475 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7570500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6994999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 2775 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 2777 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 247424 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 2777 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7736 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247552 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3866 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 3868 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3866 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3868 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3866 # Request fanout histogram -system.membus.reqLayer0.occupancy 4516500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3868 # Request fanout histogram +system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20548250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20557500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |