diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 642 |
1 files changed, 321 insertions, 321 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index f50e78f71..fc0b314ed 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131756 # Number of seconds simulated -sim_ticks 131756455500 # Number of ticks simulated -final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131767 # Number of seconds simulated +sim_ticks 131767151500 # Number of ticks simulated +final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 150043 # Simulator instruction rate (inst/s) -host_op_rate 158169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 114724713 # Simulator tick rate (ticks/s) -host_mem_usage 245376 # Number of bytes of host memory used -host_seconds 1148.46 # Real time elapsed on the host -sim_insts 172317809 # Number of instructions simulated -sim_ops 181650742 # Number of ops (including micro ops) simulated +host_inst_rate 176753 # Simulator instruction rate (inst/s) +host_op_rate 186327 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 135158895 # Simulator tick rate (ticks/s) +host_mem_usage 309748 # Number of bytes of host memory used +host_seconds 974.91 # Real time elapsed on the host +sim_insts 172317810 # Number of instructions simulated +sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 138304 # Nu system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1049609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 829585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1879194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 829585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1879194 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3869 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue @@ -52,11 +52,11 @@ system.physmem.perBankRdBursts::7 222 # Pe system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 201 # Per bank write bursts +system.physmem.perBankRdBursts::11 200 # Per bank write bursts system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts -system.physmem.perBankRdBursts::15 204 # Per bank write bursts +system.physmem.perBankRdBursts::15 205 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131756361000 # Total gap between requests +system.physmem.totGap 131767057000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation -system.physmem.totQLat 26795500 # Total ticks spent queuing -system.physmem.totMemAccLat 99339250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 272.793826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.627814 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 276.033343 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 260 28.67% 28.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 352 38.81% 67.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 83 9.15% 76.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 54 5.95% 82.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 42 4.63% 87.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 20 2.21% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 22 2.43% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 19 2.09% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 55 6.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 907 # Bytes accessed per row activation +system.physmem.totQLat 28218000 # Total ticks spent queuing +system.physmem.totMemAccLat 100761750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6925.69 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7293.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25675.69 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26043.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -216,49 +216,49 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2968 # Number of row buffer hits during reads +system.physmem.readRowHits 2961 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34054370.90 # Average gap between requests -system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 34057135.44 # Average gap between requests +system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3114720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1699500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16200600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3539591415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75945924750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88111773435 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.773046 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126343729250 # Time in different power states -system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states +system.physmem_0.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3598001595 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75904039500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88129416795 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.827838 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126271035750 # Time in different power states +system.physmem_0.memoryStateTime::REF 4399980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1010946750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1095966750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3742200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2041875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13954200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.806861 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states -system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states +system.physmem_1.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3577878315 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75921691500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88125668970 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.799395 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126300767500 # Time in different power states +system.physmem_1.memoryStateTime::REF 4399980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1066235000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49934475 # Number of BP lookups -system.cpu.branchPred.condPredicted 39666705 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24374227 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits +system.cpu.branchPred.lookups 49934214 # Number of BP lookups +system.cpu.branchPred.condPredicted 39669228 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5745476 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24397430 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23302007 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.592537 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.510089 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1908013 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263512911 # number of cpu cycles simulated +system.cpu.numCycles 263534303 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 172317809 # Number of instructions committed -system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 172317810 # Number of instructions committed +system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed +system.cpu.discardedOps 11762366 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.529226 # CPI: cycles per instruction -system.cpu.ipc 0.653925 # IPC: instructions per cycle -system.cpu.tickCycles 257129929 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6382982 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.529350 # CPI: cycles per instruction +system.cpu.ipc 0.653872 # IPC: instructions per cycle +system.cpu.tickCycles 257146871 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6387432 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.698550 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40765676 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.696434 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40764379 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22522.472928 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22521.756354 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698550 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.696434 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id @@ -404,72 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81538034 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81538034 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28357756 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28357756 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 81535444 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81535444 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28356460 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28356460 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 465 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 465 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 464 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40720397 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40720397 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40720862 # number of overall hits -system.cpu.dcache.overall_hits::total 40720862 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 789 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 789 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 40719101 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40719101 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40719565 # number of overall hits +system.cpu.dcache.overall_hits::total 40719565 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2435 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2435 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses -system.cpu.dcache.overall_misses::total 2436 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57528734 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57528734 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127304750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127304750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184833484 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184833484 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184833484 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184833484 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28358545 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28358545 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2438 # number of overall misses +system.cpu.dcache.overall_misses::total 2438 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59434234 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59434234 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127677000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127677000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 187111234 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 187111234 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 187111234 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 187111234 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28357251 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28357251 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 466 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 466 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 465 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 465 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40722832 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40722832 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40723298 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40723298 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40721538 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40721538 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40722003 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40722003 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002146 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002146 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002151 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002151 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72913.477820 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72913.477820 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77341.889429 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77341.889429 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75906.974949 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75906.974949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75875.814450 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75875.814450 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75138.096081 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75138.096081 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77568.043742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77568.043742 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76779.332786 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76779.332786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76747.840033 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76747.840033 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,14 +480,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 628 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 628 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 628 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses @@ -498,91 +498,91 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809 system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51124264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51124264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85250250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85250250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52911264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52911264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85210500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85210500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136374514 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 136374514 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136444014 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 136444014 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138121764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 138121764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138191264 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 138191264 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002146 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002146 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002151 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002151 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71904.731364 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71904.731364 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77641.393443 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77641.393443 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74418.092827 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74418.092827 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77605.191257 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77605.191257 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75386.685462 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75386.685462 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75383.433149 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75383.433149 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76352.550580 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76352.550580 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76348.764641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76348.764641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2891 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.909257 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71597353 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15272.472910 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2892 # number of replacements +system.cpu.icache.tags.tagsinuse 1425.992142 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71598587 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4690 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15266.223241 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909257 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1425.992142 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.696285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.696285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143208772 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143208772 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71597353 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71597353 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71597353 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71597353 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71597353 # number of overall hits -system.cpu.icache.overall_hits::total 71597353 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses -system.cpu.icache.overall_misses::total 4689 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200357248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200357248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200357248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200357248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200357248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200357248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71602042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71602042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71602042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71602042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71602042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71602042 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42729.206227 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42729.206227 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42729.206227 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42729.206227 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 143211246 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143211246 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71598587 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71598587 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71598587 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71598587 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71598587 # number of overall hits +system.cpu.icache.overall_hits::total 71598587 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4691 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4691 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4691 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4691 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4691 # number of overall misses +system.cpu.icache.overall_misses::total 4691 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200040248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200040248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200040248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200040248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200040248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200040248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71603278 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71603278 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71603278 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71603278 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71603278 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71603278 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.412492 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42643.412492 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42643.412492 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42643.412492 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,66 +591,66 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4689 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4689 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4689 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192396752 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 192396752 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192396752 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 192396752 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192396752 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 192396752 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41031.510343 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41031.510343 # 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Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2003.582702 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2608 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.935773 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676370 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029186 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1509.739376 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814139 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046074 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061144 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2007 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 56005 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 56005 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2525 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 56021 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 56021 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2527 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2605 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61981.036078 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62841.546763 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64621.788991 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64621.788991 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595293 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61824.468085 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68751.618123 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63364.388489 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64585.321101 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64585.321101 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 5403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5402 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9381 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13017 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6517 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7498748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3019736 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 2779 # Transaction distribution system.membus.trans_dist::ReadResp 2779 # Transaction distribution @@ -820,9 +820,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3869 # Request fanout histogram -system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4517000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20559750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20556500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |