diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 777 |
1 files changed, 408 insertions, 369 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index fae4160aa..21492b1f0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.130773 # Number of seconds simulated -sim_ticks 130772642500 # Number of ticks simulated -final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.130383 # Number of seconds simulated +sim_ticks 130382890500 # Number of ticks simulated +final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239563 # Simulator instruction rate (inst/s) -host_op_rate 252538 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 181805529 # Simulator tick rate (ticks/s) -host_mem_usage 322304 # Number of bytes of host memory used -host_seconds 719.30 # Real time elapsed on the host +host_inst_rate 248644 # Simulator instruction rate (inst/s) +host_op_rate 262111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188134778 # Simulator tick rate (ticks/s) +host_mem_usage 275596 # Number of bytes of host memory used +host_seconds 693.03 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 138112 # Nu system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1059280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 838392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1897672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1059280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1059280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1059280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 838392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1897672 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3866 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 130772548000 # Total gap between requests +system.physmem.totGap 130382796000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 271.628729 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.806384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 277.022098 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 259 28.62% 28.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 352 38.90% 67.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.50% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 59 6.52% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 34 3.76% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 21 2.32% 89.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation -system.physmem.totQLat 27654500 # Total ticks spent queuing -system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 268.939891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.781102 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 276.529935 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 273 29.84% 29.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 347 37.92% 67.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 83 9.07% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 59 6.45% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 3.83% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 24 2.62% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 16 1.75% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20 2.19% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 58 6.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 915 # Bytes accessed per row activation +system.physmem.totQLat 27071500 # Total ticks spent queuing +system.physmem.totMemAccLat 99559000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7002.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25752.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage @@ -216,49 +216,53 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2957 # Number of row buffer hits during reads +system.physmem.readRowHits 2948 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33826318.68 # Average gap between requests -system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 33725503.36 # Average gap between requests +system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3144960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1716000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.826558 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states -system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states +system.physmem_0.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3562127505 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75103936500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 87202954965 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.831686 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 124939990750 # Time in different power states +system.physmem_0.memoryStateTime::REF 4353700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1087339250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3764880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2054250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.811714 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states -system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states +system.physmem_1.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3544157970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.803682 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states +system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49732170 # Number of BP lookups -system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5592247 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24154061 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23128262 # Number of BTB hits +system.cpu.branchPred.lookups 49622074 # Number of BP lookups +system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.753099 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1888632 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,69 +381,104 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 261545285 # number of cpu cycles simulated +system.cpu.numCycles 260765781 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11660914 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.517808 # CPI: cycles per instruction -system.cpu.ipc 0.658845 # IPC: instructions per cycle -system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.513284 # CPI: cycles per instruction +system.cpu.ipc 0.660815 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction +system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction +system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction +system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 181650743 # Class of committed instruction +system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81519460 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81519460 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28348467 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28348467 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362639 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362639 # number of WriteReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40711106 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40711106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40711568 # number of overall hits -system.cpu.dcache.overall_hits::total 40711568 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 794 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 794 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1648 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1648 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40709197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40709197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40709659 # number of overall hits +system.cpu.dcache.overall_hits::total 40709659 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2442 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses -system.cpu.dcache.overall_misses::total 2443 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses +system.cpu.dcache.overall_misses::total 2441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59629000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59629000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126003000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126003000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 185632000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 185632000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 185632000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 185632000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28347350 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28347350 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) @@ -448,10 +487,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40713548 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40713548 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40714011 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40714011 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40711637 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40711637 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712100 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712100 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses @@ -462,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76078.688525 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,34 +519,34 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 550 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 633 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 633 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 633 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 633 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52555500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52555500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85213000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85213000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137768500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137768500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137838500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 137838500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -518,71 +557,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2888 # number of replacements -system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2881 # number of replacements +system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 142037650 # Number of tag accesses -system.cpu.icache.tags.data_accesses 142037650 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71011798 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71011798 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71011798 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71011798 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71011798 # number of overall hits -system.cpu.icache.overall_hits::total 71011798 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4685 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4685 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4685 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses -system.cpu.icache.overall_misses::total 4685 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71016483 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71016483 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71016483 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses +system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits +system.cpu.icache.overall_hits::total 70779397 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4678 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4678 # number of overall misses +system.cpu.icache.overall_misses::total 4678 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 198432500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 198432500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 198432500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 198432500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 198432500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 198432500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 70784075 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 70784075 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 70784075 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 70784075 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42671.611526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42671.611526 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42418.234288 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42418.234288 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42418.234288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,135 +630,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 2888 # number of writebacks -system.cpu.icache.writebacks::total 2888 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4685 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4685 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4685 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4685 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4685 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4685 # 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number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4685 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 4685 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2559 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2559 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4678 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4678 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4685 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6495 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4685 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6495 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461259 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461259 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461259 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.597844 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461259 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.597844 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174 # average overall miss latency +system.cpu.l2cache.demand_accesses::cpu.inst 4678 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6489 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4678 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6489 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461950 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461950 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886236 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886236 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461950 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.950856 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.598397 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461950 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.950856 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.598397 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75724.568633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -738,97 +777,97 @@ system.cpu.l2cache.demand_mshr_hits::total 16 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2159 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2159 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 618 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 618 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72427500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72427500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139601500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139601500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42758500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42758500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139601500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.460832 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.867978 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72569000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72569000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 138134000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 138134000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43490000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43490000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138134000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116059000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 254193000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138134000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116059000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 254193000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461522 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595932 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595932 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 15919 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 484608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 601472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15900 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 600640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6495 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.071132 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.257064 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6489 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.071197 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.257174 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6033 92.89% 92.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 462 7.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6027 92.88% 92.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 462 7.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6495 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7616500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7026998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2721986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 2776 # Transaction distribution -system.membus.trans_dist::ReadExReq 1090 # Transaction distribution -system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2776 # Transaction distribution +system.membus.trans_dist::ReadResp 2775 # Transaction distribution +system.membus.trans_dist::ReadExReq 1091 # Transaction distribution +system.membus.trans_dist::ReadExResp 1091 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes) @@ -844,9 +883,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3866 # Request fanout histogram -system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4516500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20548250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |