diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 346 |
1 files changed, 181 insertions, 165 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index f13570e98..f50e78f71 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131756 # Nu sim_ticks 131756455500 # Number of ticks simulated final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 249754 # Simulator instruction rate (inst/s) -host_op_rate 263281 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 190965456 # Simulator tick rate (ticks/s) -host_mem_usage 316672 # Number of bytes of host memory used -host_seconds 689.95 # Real time elapsed on the host +host_inst_rate 150043 # Simulator instruction rate (inst/s) +host_op_rate 158169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 114724713 # Simulator tick rate (ticks/s) +host_mem_usage 245376 # Number of bytes of host memory used +host_seconds 1148.46 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # By system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation -system.physmem.totQLat 26801000 # Total ticks spent queuing -system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 26795500 # Total ticks spent queuing +system.physmem.totMemAccLat 99339250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6925.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25675.69 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -227,14 +227,14 @@ system.physmem_0.preEnergy 1674750 # En system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.773044 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states +system.physmem_0.actBackEnergy 3539591415 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75945924750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88111773435 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.773046 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126343729250 # Time in different power states system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1010946750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) @@ -250,13 +250,13 @@ system.physmem_1.memoryStateTime::REF 4399460000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49934480 # Number of BP lookups -system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted +system.cpu.branchPred.lookups 49934475 # Number of BP lookups +system.cpu.branchPred.condPredicted 39666705 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24374227 # Number of BTB lookups system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 95.592537 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -386,15 +386,15 @@ system.cpu.discardedOps 11759003 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.529226 # CPI: cycles per instruction system.cpu.ipc 0.653925 # IPC: instructions per cycle -system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 257129929 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6382982 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.698550 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40765676 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22522.472928 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698550 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id @@ -404,64 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 81538034 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81538034 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28357756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28357756 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 465 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 465 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits -system.cpu.dcache.overall_hits::total 40720863 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 40720397 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40720397 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40720862 # number of overall hits +system.cpu.dcache.overall_hits::total 40720862 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 789 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 789 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2435 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2435 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses system.cpu.dcache.overall_misses::total 2436 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57528734 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57528734 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127304750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127304750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184833484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184833484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184833484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184833484 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28358545 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28358545 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 466 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 466 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40722832 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40722832 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40723298 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40723298 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002146 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002146 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72913.477820 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72913.477820 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77341.889429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77341.889429 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75906.974949 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75906.974949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75875.814450 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75875.814450 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,46 +488,54 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 626 system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51124264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51124264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85250250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85250250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136374514 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136374514 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136444014 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136444014 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002146 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002146 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71904.731364 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71904.731364 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77641.393443 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77641.393443 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75386.685462 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75386.685462 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75383.433149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75383.433149 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2891 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1424.909257 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71597353 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 15272.472910 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909257 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id @@ -529,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 490 system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits -system.cpu.icache.overall_hits::total 71597357 # number of overall hits +system.cpu.icache.tags.tag_accesses 143208772 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143208772 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71597353 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71597353 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71597353 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71597353 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71597353 # number of overall hits +system.cpu.icache.overall_hits::total 71597353 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses system.cpu.icache.overall_misses::total 4689 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200357248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200357248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200357248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200357248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200357248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200357248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71602042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71602042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71602042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71602042 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71602042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71602042 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42729.206227 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42729.206227 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42729.206227 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42729.206227 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -581,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4689 system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192401752 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 192401752 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192401752 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 192401752 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192401752 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 192401752 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192396752 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 192396752 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192396752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 192396752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192396752 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 192396752 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41032.576669 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41032.576669 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41031.510343 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41031.510343 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41031.510343 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41031.510343 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41031.510343 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41031.510343 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.520500 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2001.520504 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676368 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814962 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676370 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814964 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy @@ -646,17 +662,17 @@ system.cpu.l2cache.demand_misses::total 3886 # nu system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses system.cpu.l2cache.overall_misses::total 3886 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161201250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161196250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49637250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 210838500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84065750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84065750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 161201250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 133703000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 294904250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 161201250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 133703000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 294904250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 210833500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84066750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 84066750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 161196250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 133704000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294900250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 161196250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 133704000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294900250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4689 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5401 # number of ReadReq accesses(hits+misses) @@ -681,17 +697,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.597938 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74492.259704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74489.949168 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75407.188841 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77124.541284 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77124.541284 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75888.896037 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75888.896037 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75405.400572 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77125.458716 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77125.458716 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74489.949168 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.599303 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75887.866701 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74489.949168 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.599303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75887.866701 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,17 +736,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3870 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134008500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134003000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174699500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70437750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70437750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134003000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111134250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 245137250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134003000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111134250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 245137250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses @@ -742,17 +758,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61981.036078 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62841.546763 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64621.788991 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64621.788991 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution @@ -806,7 +822,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 3869 # Request fanout histogram system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20559750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |