diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 480 |
1 files changed, 242 insertions, 238 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 91b6b6b0a..9382954d5 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132486 # Number of seconds simulated -sim_ticks 132485848500 # Number of ticks simulated -final_tick 132485848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132488 # Number of seconds simulated +sim_ticks 132487590500 # Number of ticks simulated +final_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159309 # Simulator instruction rate (inst/s) -host_op_rate 167937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 122483807 # Simulator tick rate (ticks/s) -host_mem_usage 270152 # Number of bytes of host memory used -host_seconds 1081.66 # Real time elapsed on the host +host_inst_rate 200266 # Simulator instruction rate (inst/s) +host_op_rate 211113 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153975874 # Simulator tick rate (ticks/s) +host_mem_usage 275560 # Number of bytes of host memory used +host_seconds 860.44 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247552 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 825084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1868517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 825084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1868517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3868 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 132485754500 # Total gap between requests +system.physmem.totGap 132487495500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 264.680301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.140302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 275.634226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 285 30.68% 30.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 355 38.21% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.26% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 48 5.17% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 3.77% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 24 2.58% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21 2.26% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.05% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 56 6.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 929 # Bytes accessed per row activation -system.physmem.totQLat 30291250 # Total ticks spent queuing -system.physmem.totMemAccLat 102816250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation +system.physmem.totQLat 28381250 # Total ticks spent queuing +system.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7831.24 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26581.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s @@ -217,56 +217,56 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2934 # Number of row buffer hits during reads +system.physmem.readRowHits 2936 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34251746.25 # Average gap between requests -system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3182760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1736625 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 34252196.35 # Average gap between requests +system.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3626588520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 76308756000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88609573905 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.835850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126944435250 # Time in different power states +system.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.825360 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states system.physmem_0.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1115186250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3635416395 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 76301020500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88609288305 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.833625 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126931702750 # Time in different power states +system.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.826698 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states system.physmem_1.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1127787750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 49693791 # Number of BP lookups -system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 49693795 # Number of BP lookups +system.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 264971697 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 264975181 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.537692 # CPI: cycles per instruction -system.cpu.ipc 0.650325 # IPC: instructions per cycle +system.cpu.cpi 1.537712 # CPI: cycles per instruction +system.cpu.ipc 0.650317 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction @@ -432,18 +432,18 @@ system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction -system.cpu.tickCycles 256731546 # Number of cycles that the object actually ticked -system.cpu.idleCycles 8240151 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked +system.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1378.678714 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40755400 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22504.362231 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1378.678714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336591 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336591 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -451,11 +451,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362636 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362636 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits @@ -464,10 +464,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40710124 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40710124 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40710586 # number of overall hits -system.cpu.dcache.overall_hits::total 40710586 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits +system.cpu.dcache.overall_hits::total 40710587 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1651 # number of WriteReq misses @@ -478,16 +478,16 @@ system.cpu.dcache.demand_misses::cpu.data 2402 # n system.cpu.dcache.demand_misses::total 2402 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2403 # number of overall misses system.cpu.dcache.overall_misses::total 2403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55315500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55315500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127182500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127182500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 182498000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 182498000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 182498000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 182498000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +496,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses @@ -510,14 +510,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73655.792277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73655.792277 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77033.615990 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77033.615990 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.518734 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75977.518734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75945.900957 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75945.900957 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52182500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52182500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 138316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138386000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 138386000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -564,26 +564,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73393.108298 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73393.108298 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78374.431301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78374.431301 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76417.679558 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76417.679558 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76414.135837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76414.135837 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2864 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.966015 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use system.cpu.icache.tags.total_refs 70941364 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15213.674459 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.966015 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695784 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id @@ -593,7 +593,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 141896719 # Number of tag accesses system.cpu.icache.tags.data_accesses 141896719 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 70941364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 70941364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 70941364 # number of demand (read+write) hits @@ -606,12 +606,12 @@ system.cpu.icache.demand_misses::cpu.inst 4664 # n system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses system.cpu.icache.overall_misses::total 4664 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200959500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200959500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200959500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200959500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200959500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200959500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 70946028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 70946028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 70946028 # number of demand (read+write) accesses @@ -624,12 +624,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43087.371355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43087.371355 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43087.371355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43087.371355 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,48 +644,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4664 system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196296500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 196296500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196296500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 196296500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196296500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 196296500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42087.585763 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42087.585763 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2000.553914 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5137 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.844524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029612 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.714154 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 489.810148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046012 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 76244 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 76244 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.040521 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits @@ -714,18 +712,18 @@ system.cpu.l2cache.demand_misses::total 3885 # nu system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 162646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 162646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50260000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 50260000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 162646500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 134659500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 297306000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 162646500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 134659500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 297306000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85311000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 85311000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 299285500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses) @@ -754,18 +752,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.600000 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77359.761687 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77359.761687 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75229.648474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75229.648474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79525.316456 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79525.316456 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76526.640927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76526.640927 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77036.164736 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77036.164736 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,18 +792,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3869 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73489500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73489500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140980000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140980000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43051500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43051500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140980000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116541000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 257521000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140980000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116541000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 257521000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses @@ -818,25 +816,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67359.761687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67359.761687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65238.315595 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65238.315595 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69775.526742 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69775.526742 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution @@ -870,7 +868,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 6994999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2777 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution @@ -891,9 +895,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3868 # Request fanout histogram -system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20557500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |