diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 1381 |
1 files changed, 697 insertions, 684 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a8c1caea2..b441da851 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085032 # Number of seconds simulated -sim_ticks 85032044000 # Number of ticks simulated -final_tick 85032044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085019 # Number of seconds simulated +sim_ticks 85018904000 # Number of ticks simulated +final_tick 85018904000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135904 # Simulator instruction rate (inst/s) -host_op_rate 143266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67069129 # Simulator tick rate (ticks/s) -host_mem_usage 314096 # Number of bytes of host memory used -host_seconds 1267.83 # Real time elapsed on the host +host_inst_rate 135768 # Simulator instruction rate (inst/s) +host_op_rate 143122 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66991355 # Simulator tick rate (ticks/s) +host_mem_usage 315704 # Number of bytes of host memory used +host_seconds 1269.10 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory -system.physmem.bytes_read::total 245888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3842 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1494025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 558472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 839213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2891710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1494025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1494025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1494025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 558472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 839213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2891710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3842 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 126976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71296 # Number of bytes read from this memory +system.physmem.bytes_read::total 246144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 126976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 126976 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1984 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1114 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3846 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1493503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 563075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 838590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2895168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1493503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1493503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1493503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 563075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 838590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2895168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3846 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3842 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3846 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 245888 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 246144 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 245888 # Total read bytes from the system interface side +system.physmem.bytesReadSys 246144 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,16 +48,16 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 309 # Per bank write bursts system.physmem.perBankRdBursts::1 220 # Per bank write bursts system.physmem.perBankRdBursts::2 142 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::3 309 # Per bank write bursts system.physmem.perBankRdBursts::4 300 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts -system.physmem.perBankRdBursts::7 233 # Per bank write bursts +system.physmem.perBankRdBursts::7 237 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts system.physmem.perBankRdBursts::9 219 # Per bank write bursts -system.physmem.perBankRdBursts::10 292 # Per bank write bursts +system.physmem.perBankRdBursts::10 291 # Per bank write bursts system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 191 # Per bank write bursts +system.physmem.perBankRdBursts::12 193 # Per bank write bursts system.physmem.perBankRdBursts::13 211 # Per bank write bursts system.physmem.perBankRdBursts::14 211 # Per bank write bursts system.physmem.perBankRdBursts::15 194 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85031900500 # Total gap between requests +system.physmem.totGap 85018760500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3842 # Read request sizes (log2) +system.physmem.readPktSize::6 3846 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,16 +94,16 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 763 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 320.083879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.433795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.783352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 232 30.41% 30.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 191 25.03% 55.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 11.53% 66.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 86 11.27% 78.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 27 3.54% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 4.85% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11 1.44% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 2.23% 90.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 74 9.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 763 # Bytes accessed per row activation -system.physmem.totQLat 43141443 # Total ticks spent queuing -system.physmem.totMemAccLat 115178943 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19210000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11228.90 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 316.211068 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.877402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.919917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 237 30.50% 30.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 193 24.84% 55.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 10.81% 66.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 88 11.33% 77.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.50% 81.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 40 5.15% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 20 2.57% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13 1.67% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 67 8.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 777 # Bytes accessed per row activation +system.physmem.totQLat 39111678 # Total ticks spent queuing +system.physmem.totMemAccLat 111224178 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10169.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29978.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28919.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.30 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.71 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3071 # Number of row buffer hits during reads +system.physmem.readRowHits 3067 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.93 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22132196.90 # Average gap between requests -system.physmem.pageHitRate 79.93 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2729160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1489125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22105761.96 # Average gap between requests +system.physmem.pageHitRate 79.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2744280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1497375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16231800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2330695800 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48971187750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56875754235 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.921152 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81466351731 # Time in different power states -system.physmem_0.memoryStateTime::REF 2839200000 # Time in different power states +system.physmem_0.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2336092560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48961790250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56871322905 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.930183 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81450773508 # Time in different power states +system.physmem_0.memoryStateTime::REF 2838940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 720558269 # Time in different power states +system.physmem_0.memoryStateTime::ACT 728623992 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3016440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1645875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13548600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1707750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13712400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2293230555 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 49004052000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56868968670 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.841346 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81522647918 # Time in different power states -system.physmem_1.memoryStateTime::REF 2839200000 # Time in different power states +system.physmem_1.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2289194100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 49002929250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56863639980 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.839816 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81519548908 # Time in different power states +system.physmem_1.memoryStateTime::REF 2838940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 665486082 # Time in different power states +system.physmem_1.memoryStateTime::ACT 659848592 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85925704 # Number of BP lookups -system.cpu.branchPred.condPredicted 68401753 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6018362 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40106814 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39018678 # Number of BTB hits +system.cpu.branchPred.lookups 85912123 # Number of BP lookups +system.cpu.branchPred.condPredicted 68393040 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6015536 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40101118 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39014565 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.286905 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3705148 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81894 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.290467 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3703089 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81902 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,130 +381,130 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170064089 # number of cpu cycles simulated +system.cpu.numCycles 170037809 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5613343 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349288276 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85925704 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42723826 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158284040 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12050671 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5613511 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349250633 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85912123 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42717654 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158261511 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12044973 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1577 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2225 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78959765 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17996 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169926703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150511 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.047128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2368 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78950648 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18008 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169901476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047122 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17361476 10.22% 10.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30212798 17.78% 28.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31840839 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90511590 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17358895 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30204196 17.78% 27.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31835534 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90502851 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169926703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505255 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.053863 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17566577 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17110905 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122676579 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6722207 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5850435 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11136607 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190140 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306627324 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27647944 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5850435 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37756146 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8468505 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 579113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108935441 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8337063 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278668040 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13416082 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3052051 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 841470 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187697 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 36000 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26450 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483113762 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196983953 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297587542 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006013 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169901476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505253 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.053959 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17563828 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17110473 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122657456 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6722156 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5847563 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11134699 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190129 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306600036 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27639970 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5847563 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37745979 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8468798 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579877 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108923634 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8335625 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278650711 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13412582 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3051453 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842711 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2185712 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 35165 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26489 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483080894 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196921588 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297573906 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006747 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190136833 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23525 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23424 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13336678 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34143660 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476609 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2548114 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1810648 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264825192 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45854 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214913936 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5193552 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 83235092 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219939501 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 638 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169926703 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264745 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190103965 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23523 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23430 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13336347 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34142095 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476543 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2549376 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1793123 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264810332 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45855 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214902718 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5190620 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 83220233 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219925398 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 639 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169901476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264867 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.017460 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52848454 31.10% 31.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36099011 21.24% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65787739 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13574201 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1569834 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47276 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 188 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52832101 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36093158 21.24% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65784259 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13574357 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570220 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47195 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 186 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169926703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169901476 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35606881 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152777 0.28% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35605011 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152712 0.28% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35731 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 243 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 1036 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34373 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35741 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1037 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34404 0.06% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14081261 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3945561 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14078469 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3945889 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167354642 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918991 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167344164 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918970 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -525,91 +525,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 33018 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165174 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165202 0.08% 78.39% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460494 0.21% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206680 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460547 0.21% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32007537 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373732 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32006921 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13373534 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214913936 # Type of FU issued -system.cpu.iq.rate 1.263723 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53859137 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250608 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654855291 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 346101904 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204603491 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3951973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2011176 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806361 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266640239 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2132834 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1601131 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214902718 # Type of FU issued +system.cpu.iq.rate 1.263853 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53854775 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250601 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654798543 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 346070765 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204597394 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3953764 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2012584 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806443 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266623027 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2134466 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1601141 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6247516 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7571 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7104 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1831975 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6245951 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7537 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7067 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1831909 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25920 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 745 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25713 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 804 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5850435 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5682032 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37041 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264886958 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5847563 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5681873 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37049 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264872174 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34143660 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476609 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3875 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29998 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7104 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3234550 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3248118 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6482668 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207528127 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30721496 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7385809 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34142095 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476543 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23447 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3919 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29963 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7067 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3232804 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246682 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6479486 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207521850 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30720954 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7380868 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15912 # number of nop insts executed -system.cpu.iew.exec_refs 43861162 # number of memory reference insts executed -system.cpu.iew.exec_branches 44936179 # Number of branches executed -system.cpu.iew.exec_stores 13139666 # Number of stores executed -system.cpu.iew.exec_rate 1.220294 # Inst execution rate -system.cpu.iew.wb_sent 206744895 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206409852 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129477271 # num instructions producing a value -system.cpu.iew.wb_consumers 221697359 # num instructions consuming a value +system.cpu.iew.exec_nop 15987 # number of nop insts executed +system.cpu.iew.exec_refs 43860782 # number of memory reference insts executed +system.cpu.iew.exec_branches 44934590 # Number of branches executed +system.cpu.iew.exec_stores 13139828 # Number of stores executed +system.cpu.iew.exec_rate 1.220445 # Inst execution rate +system.cpu.iew.wb_sent 206738830 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206403837 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129472700 # num instructions producing a value +system.cpu.iew.wb_consumers 221699640 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.213718 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584027 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213870 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584000 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69541697 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69532932 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5843462 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158482976 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646662 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5840613 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158460459 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646701 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73704941 46.51% 46.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41274815 26.04% 72.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22552900 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9628649 6.08% 92.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3549516 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2148015 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1280291 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 986897 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3356952 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73681032 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41276330 26.05% 72.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22553900 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9626912 6.08% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3550160 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2147757 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1281176 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 986541 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3356651 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158482976 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158460459 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,374 +655,380 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3356952 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406312862 # The number of ROB reads -system.cpu.rob.rob_writes 513841850 # The number of ROB writes -system.cpu.timesIdled 3415 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 137386 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3356651 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 406281881 # The number of ROB reads +system.cpu.rob.rob_writes 513821502 # The number of ROB writes +system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 136333 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.987006 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.987006 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013165 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013165 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218961575 # number of integer regfile reads -system.cpu.int_regfile_writes 114515726 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904225 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441500 # number of floating regfile writes -system.cpu.cc_regfile_reads 709589041 # number of cc regfile reads -system.cpu.cc_regfile_writes 229545726 # number of cc regfile writes -system.cpu.misc_regfile_reads 59313943 # number of misc regfile reads +system.cpu.cpi 0.986853 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986853 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013322 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013322 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218956398 # number of integer regfile reads +system.cpu.int_regfile_writes 114512064 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904391 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441624 # number of floating regfile writes +system.cpu.cc_regfile_reads 709567727 # number of cc regfile reads +system.cpu.cc_regfile_writes 229536120 # number of cc regfile writes +system.cpu.misc_regfile_reads 59314176 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72899 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.418278 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41116599 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73411 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.087712 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 506067250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.418278 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998864 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998864 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72863 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.419653 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41115439 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73375 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.346698 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 504093500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.419653 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998867 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998867 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82531693 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82531693 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28730266 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28730266 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341417 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341417 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82529747 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82529747 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28729201 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28729201 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341321 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341321 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22149 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22149 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41071683 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41071683 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41072044 # number of overall hits -system.cpu.dcache.overall_hits::total 41072044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89294 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89294 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22870 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22870 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112164 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112164 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112282 # number of overall misses -system.cpu.dcache.overall_misses::total 112282 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 853196487 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 853196487 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 241173427 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 241173427 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2319500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2319500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1094369914 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1094369914 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1094369914 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1094369914 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28819560 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28819560 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 41070522 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41070522 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41070883 # number of overall hits +system.cpu.dcache.overall_hits::total 41070883 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89405 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89405 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22966 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22966 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112371 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112371 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112488 # number of overall misses +system.cpu.dcache.overall_misses::total 112488 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 853901000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 853901000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 240852499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 240852499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2309500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1094753499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1094753499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1094753499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1094753499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28818606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28818606 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 478 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 478 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41183847 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41183847 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41184326 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41184326 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003098 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003098 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001850 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001850 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011603 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011603 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002723 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002723 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002726 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002726 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9554.913958 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9554.913958 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10545.405641 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10545.405641 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8921.153846 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8921.153846 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9756.873097 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9756.873097 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9746.619351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9746.619351 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 167 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9765 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41182893 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41182893 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41183371 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41183371 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003102 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003102 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244770 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.244770 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002729 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002729 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9550.931156 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9550.931156 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10487.350823 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10487.350823 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8916.988417 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8916.988417 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9742.313399 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9742.313399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9732.180313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9732.180313 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10552 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 848 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 11.515330 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.198844 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64878 # number of writebacks -system.cpu.dcache.writebacks::total 64878 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24567 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24567 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14301 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14301 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38868 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38868 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38868 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38868 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64727 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64727 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8569 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8569 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73296 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73411 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73411 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 526755010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 526755010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81248758 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 81248758 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 920500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 920500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 608003768 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 608003768 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 608924268 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 608924268 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses +system.cpu.dcache.writebacks::writebacks 64850 # number of writebacks +system.cpu.dcache.writebacks::total 64850 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24706 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24706 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14404 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14404 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39110 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39110 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39110 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39110 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64699 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64699 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8562 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8562 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73261 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73261 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73375 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73375 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558347000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 558347000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85131499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85131499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 970000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 970000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 643478499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 643478499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 644448499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 644448499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.238494 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.238494 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8138.103264 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8138.103264 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9481.708251 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9481.708251 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8004.347826 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8004.347826 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8295.183475 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8295.183475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8294.727875 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8294.727875 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8629.917000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8629.917000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9942.945457 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9942.945457 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8508.771930 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8508.771930 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8783.370402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8783.370402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8782.943768 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8782.943768 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54462 # number of replacements -system.cpu.icache.tags.tagsinuse 510.603252 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78902001 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54974 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1435.260323 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84278847250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.603252 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997272 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997272 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 54433 # number of replacements +system.cpu.icache.tags.tagsinuse 510.604366 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78892637 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54945 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1435.847429 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84263927500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.604366 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997274 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997274 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157974458 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157974458 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78902001 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78902001 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78902001 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78902001 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78902001 # number of overall hits -system.cpu.icache.overall_hits::total 78902001 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57741 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57741 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57741 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57741 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57741 # number of overall misses -system.cpu.icache.overall_misses::total 57741 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 606045932 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 606045932 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 606045932 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 606045932 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 606045932 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 606045932 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78959742 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78959742 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78959742 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78959742 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78959742 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78959742 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000731 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000731 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000731 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000731 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000731 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000731 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10495.937583 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10495.937583 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10495.937583 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10495.937583 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10495.937583 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10495.937583 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 55224 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 157956201 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157956201 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78892637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78892637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78892637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78892637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78892637 # number of overall hits +system.cpu.icache.overall_hits::total 78892637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57991 # number of overall misses +system.cpu.icache.overall_misses::total 57991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 602655456 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 602655456 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 602655456 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 602655456 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 602655456 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 602655456 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78950628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78950628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78950628 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78950628 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78950628 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78950628 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10392.223897 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10392.223897 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10392.223897 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10392.223897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10392.223897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10392.223897 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 58612 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2764 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2849 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.979740 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.572833 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72744.722955 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69549.326538 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1031,126 +1037,133 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 14 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020793 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1818 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1818 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1984 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1984 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 513 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 513 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1984 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 748 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2732 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1984 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 748 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1818 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4550 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70301588 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70301588 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16173000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16173000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 123686500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 123686500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33594500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33594500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 123686500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49767500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 173454000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 123686500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49767500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70301588 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 243755588 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036108 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010107 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021241 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036108 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010107 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027218 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027218 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036109 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007924 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007924 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010194 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021291 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010194 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035300 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60019.776826 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65166.831683 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61063.657430 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39193.573407 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67258.438819 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67258.438819 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60019.776826 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65834.905660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61602.037770 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60019.776826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65834.905660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52677.219109 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035458 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38669.740374 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68821.276596 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68821.276596 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62341.985887 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62341.985887 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65486.354776 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65486.354776 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62341.985887 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66534.090909 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63489.751098 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62341.985887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66534.090909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53572.656703 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 119749 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 119749 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2153 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 321648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3518336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12368832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2153 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 195416 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011018 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104385 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 119686 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64850 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2160 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54945 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64741 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155973 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217450 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 373423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8846400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12362880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2160 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 257776 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.008379 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.091155 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 193263 98.90% 98.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2153 1.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 255616 99.16% 99.16% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2160 0.84% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 195416 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 161509500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 257776 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 192658000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82870477 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82430973 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110219231 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110066991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3605 # Transaction distribution -system.membus.trans_dist::ReadResp 3605 # Transaction distribution -system.membus.trans_dist::ReadExReq 237 # Transaction distribution -system.membus.trans_dist::ReadExResp 237 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 245888 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3611 # Transaction distribution +system.membus.trans_dist::ReadExReq 235 # Transaction distribution +system.membus.trans_dist::ReadExResp 235 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3611 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7692 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7692 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 246144 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3842 # Request fanout histogram +system.membus.snoop_fanout::samples 3846 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3842 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3846 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3842 # Request fanout histogram -system.membus.reqLayer0.occupancy 4969720 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3846 # Request fanout histogram +system.membus.reqLayer0.occupancy 5081597 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20244552 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20277583 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |