diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 1325 |
1 files changed, 672 insertions, 653 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 59645b4d8..eafc895c2 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074209 # Number of seconds simulated -sim_ticks 74208571000 # Number of ticks simulated -final_tick 74208571000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074057 # Number of seconds simulated +sim_ticks 74056845500 # Number of ticks simulated +final_tick 74056845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109569 # Simulator instruction rate (inst/s) -host_op_rate 119969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47190079 # Simulator tick rate (ticks/s) -host_mem_usage 316768 # Number of bytes of host memory used -host_seconds 1572.55 # Real time elapsed on the host +host_inst_rate 115398 # Simulator instruction rate (inst/s) +host_op_rate 126351 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49598898 # Simulator tick rate (ticks/s) +host_mem_usage 265028 # Number of bytes of host memory used +host_seconds 1493.11 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory -system.physmem.bytes_read::total 243264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131456 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2054 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3801 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1771440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1506672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3278112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1771440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1771440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1771440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1506672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3278112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3802 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 131840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory +system.physmem.bytes_read::total 244032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131840 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2060 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3813 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1780254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1514944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3295198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1780254 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1780254 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1780254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1514944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3295198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3814 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3802 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3814 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 243328 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 244096 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 243328 # Total read bytes from the system interface side +system.physmem.bytesReadSys 244096 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 306 # Per bank write bursts -system.physmem.perBankRdBursts::1 216 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 307 # Per bank write bursts +system.physmem.perBankRdBursts::1 215 # Per bank write bursts system.physmem.perBankRdBursts::2 134 # Per bank write bursts -system.physmem.perBankRdBursts::3 308 # Per bank write bursts -system.physmem.perBankRdBursts::4 298 # Per bank write bursts +system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::4 299 # Per bank write bursts system.physmem.perBankRdBursts::5 300 # Per bank write bursts system.physmem.perBankRdBursts::6 265 # Per bank write bursts -system.physmem.perBankRdBursts::7 217 # Per bank write bursts +system.physmem.perBankRdBursts::7 223 # Per bank write bursts system.physmem.perBankRdBursts::8 246 # Per bank write bursts -system.physmem.perBankRdBursts::9 215 # Per bank write bursts +system.physmem.perBankRdBursts::9 213 # Per bank write bursts system.physmem.perBankRdBursts::10 289 # Per bank write bursts -system.physmem.perBankRdBursts::11 192 # Per bank write bursts +system.physmem.perBankRdBursts::11 196 # Per bank write bursts system.physmem.perBankRdBursts::12 190 # Per bank write bursts -system.physmem.perBankRdBursts::13 208 # Per bank write bursts -system.physmem.perBankRdBursts::14 218 # Per bank write bursts -system.physmem.perBankRdBursts::15 200 # Per bank write bursts +system.physmem.perBankRdBursts::13 207 # Per bank write bursts +system.physmem.perBankRdBursts::14 219 # Per bank write bursts +system.physmem.perBankRdBursts::15 201 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 74208552500 # Total gap between requests +system.physmem.totGap 74056827000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3802 # Read request sizes (log2) +system.physmem.readPktSize::6 3814 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,72 +186,74 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 315.649673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.993895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 311.806865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 244 31.90% 31.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 208 27.19% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 73 9.54% 68.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 46 6.01% 74.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 29 3.79% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 70 9.15% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 12 1.57% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 15 1.96% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 68 8.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 765 # Bytes accessed per row activation -system.physmem.totQLat 30320750 # Total ticks spent queuing -system.physmem.totMemAccLat 101608250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19010000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7974.95 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 775 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.641290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.687696 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 311.293227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 258 33.29% 33.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189 24.39% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87 11.23% 68.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51 6.58% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 41 5.29% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 31 4.00% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 5.55% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10 1.29% 91.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 65 8.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 775 # Bytes accessed per row activation +system.physmem.totQLat 30109750 # Total ticks spent queuing +system.physmem.totMemAccLat 101622250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19070000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7894.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26724.95 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26644.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.28 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3030 # Number of row buffer hits during reads +system.physmem.readRowHits 3033 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.69 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19518293.66 # Average gap between requests -system.physmem.pageHitRate 79.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 70857777500 # Time in different power states -system.physmem.memoryStateTime::REF 2477800000 # Time in different power states +system.physmem.avgGap 19417101.99 # Average gap between requests +system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 70721348250 # Time in different power states +system.physmem.memoryStateTime::REF 2472860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 867720500 # Time in different power states +system.physmem.memoryStateTime::ACT 861203250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 3278112 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2731 # Transaction distribution -system.membus.trans_dist::ReadResp 2730 # Transaction distribution -system.membus.trans_dist::ReadExReq 1071 # Transaction distribution -system.membus.trans_dist::ReadExResp 1071 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7603 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7603 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243264 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 243264 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 243264 # Total data (bytes) +system.membus.throughput 3295198 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2737 # Transaction distribution +system.membus.trans_dist::ReadResp 2736 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 1077 # Transaction distribution +system.membus.trans_dist::ReadExResp 1077 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7631 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 244032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 244032 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 244032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4541000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35718000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35636248 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 94830067 # Number of BP lookups -system.cpu.branchPred.condPredicted 74823235 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6280063 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44671635 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43055955 # Number of BTB hits +system.cpu.branchPred.lookups 95688557 # Number of BP lookups +system.cpu.branchPred.condPredicted 75485372 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6295432 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 45268261 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43530249 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.383208 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4354004 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88575 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.160639 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4420185 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 89338 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,240 +339,241 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148417143 # number of cpu cycles simulated +system.cpu.numCycles 148113692 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39654365 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380231735 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94830067 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47409959 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80369944 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27285630 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7202415 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5794 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 40192835 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 385592009 # Number of instructions fetch has processed +system.cpu.fetch.Branches 95688557 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47950434 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81543775 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28012255 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4465673 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5818 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36851066 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1832690 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148222429 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37392446 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1863811 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 147907378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.849949 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.160123 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68020985 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5256509 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10534999 7.11% 56.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10284828 6.94% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8666572 5.85% 69.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6537070 4.41% 73.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6246175 4.21% 77.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8016813 5.41% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24658478 16.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66535735 44.98% 44.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5361707 3.63% 48.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10726789 7.25% 55.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10405351 7.04% 62.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8725871 5.90% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6634741 4.49% 73.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6328592 4.28% 77.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8060301 5.45% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25128291 16.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148222429 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638943 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.561913 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45507597 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5871716 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74805608 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1201041 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20836467 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14340186 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164591 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392845308 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 733522 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20836467 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50894479 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 722812 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 602318 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70557272 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4609081 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371354915 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 338748 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3656059 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631764461 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1588652531 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506975247 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3198470 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 147907378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.646048 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.603352 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45234948 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3964725 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76674416 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 488435 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21544854 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14463585 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165860 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 398867240 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 776962 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21544854 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 49978288 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80802 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 634035 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72417632 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3251767 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 377266574 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 64 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 883323 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2242172 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19804 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 7460 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 639899653 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1616068029 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1531504010 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3330597 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333720322 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25119 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25116 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13019783 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43012506 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16421309 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5620383 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3639856 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329245944 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47173 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249482695 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 793526 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139565421 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362544222 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1957 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148222429 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683164 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761970 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 341855514 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25341 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25337 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6011835 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 44415560 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16956234 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6645157 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4213095 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334591306 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47320 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 251099486 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1072213 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 144899766 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 380484892 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2104 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 147907378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.697681 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.790678 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56049781 37.81% 37.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22646407 15.28% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24808421 16.74% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20317592 13.71% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12547069 8.47% 92.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6521251 4.40% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4032352 2.72% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1118421 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181135 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56583019 38.26% 38.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 21897324 14.80% 53.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24121591 16.31% 69.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20330444 13.75% 83.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12466477 8.43% 91.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6673732 4.51% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4321605 2.92% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1302038 0.88% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 211148 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148222429 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 147907378 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 964061 38.35% 38.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5595 0.22% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 96 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1168003 46.46% 85.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 376162 14.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1040958 39.39% 39.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5589 0.21% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 97 0.00% 39.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 39.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 39.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 356 0.01% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 45 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1222208 46.25% 85.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 373303 14.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194908316 78.12% 78.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 978999 0.39% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33072 0.01% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164299 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255151 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76428 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465968 0.19% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206368 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71868 0.03% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38371220 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13950685 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 195834645 77.99% 77.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 981127 0.39% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33203 0.01% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 259909 0.10% 78.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76654 0.03% 78.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 470113 0.19% 78.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206582 0.08% 78.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71910 0.03% 78.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38922233 15.50% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14078361 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249482695 # Type of FU issued -system.cpu.iq.rate 1.680956 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2513965 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010077 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646755779 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466684925 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237894917 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3739531 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2191886 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1842592 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250120414 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1876246 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2009109 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 251099486 # Type of FU issued +system.cpu.iq.rate 1.695316 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2642556 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010524 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 650051417 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477257433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 239511768 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3769702 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2301296 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1862518 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 251853224 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1888818 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2264941 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13163022 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11141 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18733 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3776675 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14566076 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14946 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20827 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4311600 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 115 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20836467 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18579 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 909 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329310121 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 781513 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43012506 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16421309 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24765 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 190 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 272 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18733 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3888765 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3761308 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7650073 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242977304 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36862847 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6505391 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21544854 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1947 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2849 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334655682 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 756589 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 44415560 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16956234 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24912 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 319 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2632 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20827 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3907560 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3770350 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7677910 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 244706645 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37396904 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6392841 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17004 # number of nop insts executed -system.cpu.iew.exec_refs 50511963 # number of memory reference insts executed -system.cpu.iew.exec_branches 53432662 # Number of branches executed -system.cpu.iew.exec_stores 13649116 # Number of stores executed -system.cpu.iew.exec_rate 1.637124 # Inst execution rate -system.cpu.iew.wb_sent 240796428 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239737509 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148472463 # num instructions producing a value -system.cpu.iew.wb_consumers 267293668 # num instructions consuming a value +system.cpu.iew.exec_nop 17056 # number of nop insts executed +system.cpu.iew.exec_refs 51162912 # number of memory reference insts executed +system.cpu.iew.exec_branches 53733408 # Number of branches executed +system.cpu.iew.exec_stores 13766008 # Number of stores executed +system.cpu.iew.exec_rate 1.652154 # Inst execution rate +system.cpu.iew.wb_sent 242463171 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 241374286 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150213875 # num instructions producing a value +system.cpu.iew.wb_consumers 271770811 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615295 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555466 # average fanout of values written-back +system.cpu.iew.wb_rate 1.629655 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.552723 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140639228 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 145985060 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6126680 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127385962 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481096 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186061 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6141058 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126362524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.493092 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.207919 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57702305 45.30% 45.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31675528 24.87% 70.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13782422 10.82% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7634808 5.99% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4379316 3.44% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1319569 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1705598 1.34% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1313930 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7872486 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57333838 45.37% 45.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31277146 24.75% 70.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13531640 10.71% 80.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7550408 5.98% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4276360 3.38% 90.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1325331 1.05% 91.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1692872 1.34% 92.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1209518 0.96% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 8165411 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127385962 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126362524 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -616,229 +619,237 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.70% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction -system.cpu.commit.bw_lim_events 7872486 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 8165411 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448818394 # The number of ROB reads -system.cpu.rob.rob_writes 679565858 # The number of ROB writes -system.cpu.timesIdled 2789 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 194714 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 452847863 # The number of ROB reads +system.cpu.rob.rob_writes 690972129 # The number of ROB writes +system.cpu.timesIdled 2844 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 206314 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.861373 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861373 # CPI: Total CPI of All Threads -system.cpu.ipc 1.160937 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.160937 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079497274 # number of integer regfile reads -system.cpu.int_regfile_writes 384888160 # number of integer regfile writes -system.cpu.fp_regfile_reads 2912753 # number of floating regfile reads -system.cpu.fp_regfile_writes 2499155 # number of floating regfile writes -system.cpu.misc_regfile_reads 64874393 # number of misc regfile reads +system.cpu.cpi 0.859612 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.859612 # CPI: Total CPI of All Threads +system.cpu.ipc 1.163316 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.163316 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1087499674 # number of integer regfile reads +system.cpu.int_regfile_writes 386673292 # number of integer regfile writes +system.cpu.fp_regfile_reads 2922602 # number of floating regfile reads +system.cpu.fp_regfile_writes 2532629 # number of floating regfile writes +system.cpu.misc_regfile_reads 65625361 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5170292 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 19 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1081 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8239 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3733 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.throughput 5184342 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1084 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1084 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8245 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11985 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 383808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 383808 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6548996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6552747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3099487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3102991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2388 # number of replacements -system.cpu.icache.tags.tagsinuse 1346.753946 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36845676 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4119 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8945.296431 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2387 # number of replacements +system.cpu.icache.tags.tagsinuse 1349.069671 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37387126 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4121 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9072.343121 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1346.753946 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.657595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.657595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1349.069671 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.658725 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.658725 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1734 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 73706251 # Number of tag accesses -system.cpu.icache.tags.data_accesses 73706251 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 36845676 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36845676 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36845676 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36845676 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36845676 # number of overall hits -system.cpu.icache.overall_hits::total 36845676 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5390 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5390 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5390 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5390 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5390 # number of overall misses -system.cpu.icache.overall_misses::total 5390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 228751995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 228751995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 228751995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 228751995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 228751995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 228751995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36851066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36851066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36851066 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36851066 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36851066 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36851066 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42440.073284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42440.073284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42440.073284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42440.073284 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1596 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 547 # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4120 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4120 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4120 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 167326504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 167326504 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 167326504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 167326504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 167326504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 167326504 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # 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number of cycles access was blocked @@ -847,194 +858,202 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 17 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101013500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218835750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871134 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.557802 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990749 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.990749 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940765 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.636105 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.498786 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56698.053528 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58325.128792 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57445.686481 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.558800 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993542 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993542 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942473 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1410.171492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.344280 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.344280 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1804 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.438721 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 93623269 # 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number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34671591 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356534 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356534 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22477 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22477 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46756186 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46756186 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46756186 # number of overall hits -system.cpu.dcache.overall_hits::total 46756186 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1907 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1907 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7731 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7731 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 47028125 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47028125 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 47028125 # number of overall hits +system.cpu.dcache.overall_hits::total 47028125 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1914 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1914 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7753 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7753 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9638 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9638 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9638 # number of overall misses -system.cpu.dcache.overall_misses::total 9638 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 121525225 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 121525225 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 489452496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 489452496 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9667 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9667 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9667 # number of overall misses +system.cpu.dcache.overall_misses::total 9667 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 120679977 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 120679977 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 501616998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 501616998 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 610977721 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 610977721 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 610977721 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 610977721 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34401537 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34401537 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 622296975 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 622296975 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 622296975 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 622296975 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34673505 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34673505 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22479 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22479 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46765824 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46765824 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46765824 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46765824 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 47037792 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47037792 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47037792 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47037792 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63725.865233 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63725.865233 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63310.373302 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63310.373302 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63051.189655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63051.189655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64699.728879 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64699.728879 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63392.583627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63392.583627 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 318 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.545455 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64373.329368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64373.329368 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 99 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.428571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 99 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 19 # number of writebacks -system.cpu.dcache.writebacks::total 19 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1130 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1130 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6651 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6651 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6668 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6668 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7781 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7781 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7781 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7781 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7805 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7805 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7805 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7805 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1080 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1080 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52119013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52119013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75404498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75404498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 127523511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 127523511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 127523511 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 127523511 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1862 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1862 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1862 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1862 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51275761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51275761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75222996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75222996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126498757 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126498757 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126498757 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126498757 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67077.236808 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67077.236808 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69818.979630 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69818.979630 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65991.970399 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65991.970399 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69329.950230 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69329.950230 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |