summaryrefslogtreecommitdiff
path: root/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout')
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/simple-timing/simout7
1 files changed, 3 insertions, 4 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
index 50f61b81e..aba76e9d8 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,13 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:24:06
-gem5 started Jan 23 2014 00:01:50
+gem5 compiled Jan 23 2014 12:08:08
+gem5 started Jan 23 2014 18:39:21
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
-Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu.isa: ISA system set to: 0 0x5d0ed00
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988