diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt | 116 |
1 files changed, 58 insertions, 58 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 1e695b431..4c3bb52b8 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.232077 # Number of seconds simulated -sim_ticks 232077154000 # Number of ticks simulated -final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 232077144000 # Number of ticks simulated +final_tick 232077144000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 665536 # Simulator instruction rate (inst/s) -host_op_rate 728833 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 898821179 # Simulator tick rate (ticks/s) -host_mem_usage 233632 # Number of bytes of host memory used -host_seconds 258.20 # Real time elapsed on the host -sim_insts 171842491 # Number of instructions simulated -sim_ops 188185929 # Number of ops (including micro ops) simulated +host_inst_rate 1482014 # Simulator instruction rate (inst/s) +host_op_rate 1622964 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2001492603 # Simulator tick rate (ticks/s) +host_mem_usage 236052 # Number of bytes of host memory used +host_seconds 115.95 # Real time elapsed on the host +sim_insts 171842483 # Number of instructions simulated +sim_ops 188185920 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory system.physmem.bytes_read::total 220992 # Number of bytes read from this memory @@ -70,43 +70,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 464154308 # number of cpu cycles simulated +system.cpu.numCycles 464154288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 171842491 # Number of instructions committed -system.cpu.committedOps 188185929 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses +system.cpu.committedInsts 171842483 # Number of instructions committed +system.cpu.committedOps 188185920 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3504894 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32493891 # number of instructions that are conditional controls -system.cpu.num_int_insts 150106226 # number of integer instructions +system.cpu.num_func_calls 3545028 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32493890 # number of instructions that are conditional controls +system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 898652287 # number of times the integer registers were read -system.cpu.num_int_register_writes 294073530 # number of times the integer registers were written +system.cpu.num_int_register_reads 898652246 # number of times the integer registers were read +system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_mem_refs 42494120 # number of memory refs -system.cpu.num_load_insts 29849485 # Number of load instructions +system.cpu.num_mem_refs 42494119 # number of memory refs +system.cpu.num_load_insts 29849484 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 464154308 # Number of busy cycles +system.cpu.num_busy_cycles 464154288 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1506 # number of replacements -system.cpu.icache.tagsinuse 1147.981155 # Cycle average of tags in use -system.cpu.icache.total_refs 189857010 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1147.981203 # Cycle average of tags in use +system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 62227.797443 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1147.981155 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1147.981203 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.560538 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.560538 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 189857010 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 189857010 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 189857010 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 189857010 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 189857010 # number of overall hits -system.cpu.icache.overall_hits::total 189857010 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 189857001 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 189857001 # number of overall hits +system.cpu.icache.overall_hits::total 189857001 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses @@ -119,12 +119,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 115332000 system.cpu.icache.demand_miss_latency::total 115332000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 115332000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 115332000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 189860061 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 189860061 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 189860061 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 189860061 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 189860061 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 189860061 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 189860052 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 189860052 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 189860052 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses @@ -171,26 +171,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 40 # number of replacements -system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use -system.cpu.dcache.total_refs 42007359 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1363.604373 # Cycle average of tags in use +system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 23480.916154 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.604315 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 1363.604373 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.332911 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.332911 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 29599358 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 29599358 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41962545 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41962545 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41962545 # number of overall hits -system.cpu.dcache.overall_hits::total 41962545 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits +system.cpu.dcache.overall_hits::total 41962544 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses @@ -207,18 +207,18 @@ system.cpu.dcache.demand_miss_latency::cpu.data 97454000 system.cpu.dcache.demand_miss_latency::total 97454000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 97454000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 97454000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 29600047 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 29600047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41964334 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41964334 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41964334 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41964334 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1675.648101 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.582102 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 3.038048 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1169.027734 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 503.582248 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1169.027783 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 503.582269 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy |