diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux')
4 files changed, 1155 insertions, 1161 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index c2d632546..f13570e98 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131746 # Number of seconds simulated -sim_ticks 131745950000 # Number of ticks simulated -final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131756 # Number of seconds simulated +sim_ticks 131756455500 # Number of ticks simulated +final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165378 # Simulator instruction rate (inst/s) -host_op_rate 174335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126440065 # Simulator tick rate (ticks/s) -host_mem_usage 304748 # Number of bytes of host memory used -host_seconds 1041.96 # Real time elapsed on the host +host_inst_rate 249754 # Simulator instruction rate (inst/s) +host_op_rate 263281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 190965456 # Simulator tick rate (ticks/s) +host_mem_usage 316672 # Number of bytes of host memory used +host_seconds 689.95 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 138176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory -system.physmem.bytes_read::total 247488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2159 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 247616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1048806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 829718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 829718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3867 # Number of read requests accepted +system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3869 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side +system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -45,18 +45,18 @@ system.physmem.perBankRdBursts::0 305 # Pe system.physmem.perBankRdBursts::1 217 # Per bank write bursts system.physmem.perBankRdBursts::2 135 # Per bank write bursts system.physmem.perBankRdBursts::3 313 # Per bank write bursts -system.physmem.perBankRdBursts::4 308 # Per bank write bursts +system.physmem.perBankRdBursts::4 307 # Per bank write bursts system.physmem.perBankRdBursts::5 305 # Per bank write bursts system.physmem.perBankRdBursts::6 273 # Per bank write bursts system.physmem.perBankRdBursts::7 222 # Per bank write bursts system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 199 # Per bank write bursts +system.physmem.perBankRdBursts::11 201 # Per bank write bursts system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts -system.physmem.perBankRdBursts::15 203 # Per bank write bursts +system.physmem.perBankRdBursts::15 204 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131745861500 # Total gap between requests +system.physmem.totGap 131756361000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3867 # Read request sizes (log2) +system.physmem.readPktSize::6 3869 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation -system.physmem.totQLat 28130750 # Total ticks spent queuing -system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation +system.physmem.totQLat 26801000 # Total ticks spent queuing +system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2950 # Number of row buffer hits during reads +system.physmem.readRowHits 2968 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34069268.55 # Average gap between requests -system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 34054370.90 # Average gap between requests +system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.807422 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states -system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.773044 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states +system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.815773 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states -system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.806861 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states +system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49935043 # Number of BP lookups -system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits +system.cpu.branchPred.lookups 49934480 # Number of BP lookups +system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,75 +377,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263491900 # number of cpu cycles simulated +system.cpu.numCycles 263512911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317809 # Number of instructions committed system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.529104 # CPI: cycles per instruction -system.cpu.ipc 0.653978 # IPC: instructions per cycle -system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.529226 # CPI: cycles per instruction +system.cpu.ipc 0.653925 # IPC: instructions per cycle +system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.772724 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336370 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28355530 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362643 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40718173 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40718173 # number of overall hits -system.cpu.dcache.overall_hits::total 40718173 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1644 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits +system.cpu.dcache.overall_hits::total 40720863 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses system.cpu.dcache.overall_misses::total 2436 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 54011984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 115610250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 169622234 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28356322 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40720609 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40720609 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses @@ -454,14 +454,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,10 +472,10 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 546 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits @@ -488,14 +488,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76508500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123801764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 123801764 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -504,69 +504,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69679.872495 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2909 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2891 # number of replacements +system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143242775 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143242775 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71614329 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71614329 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71614329 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71614329 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71614329 # number of overall hits -system.cpu.icache.overall_hits::total 71614329 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4706 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4706 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4706 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses -system.cpu.icache.overall_misses::total 4706 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71619035 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71619035 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71619035 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits +system.cpu.icache.overall_hits::total 71597357 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses +system.cpu.icache.overall_misses::total 4689 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -575,123 +575,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4706 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4706 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4706 # 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mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118562000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 98729500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118562000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 98729500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134008500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 2777 # Transaction distribution -system.membus.trans_dist::ReadResp 2777 # Transaction distribution +system.membus.trans_dist::ReadReq 2779 # Transaction distribution +system.membus.trans_dist::ReadResp 2779 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3867 # Request fanout histogram +system.membus.snoop_fanout::samples 3869 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3867 # Request fanout histogram -system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3869 # Request fanout histogram +system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 30df36f38..bc1d643b6 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085008 # Number of seconds simulated -sim_ticks 85008313500 # Number of ticks simulated -final_tick 85008313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085027 # Number of seconds simulated +sim_ticks 85027009000 # Number of ticks simulated +final_tick 85027009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130085 # Simulator instruction rate (inst/s) -host_op_rate 137131 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64179279 # Simulator tick rate (ticks/s) -host_mem_usage 313784 # Number of bytes of host memory used -host_seconds 1324.54 # Real time elapsed on the host +host_inst_rate 134467 # Simulator instruction rate (inst/s) +host_op_rate 141751 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66356016 # Simulator tick rate (ticks/s) +host_mem_usage 312828 # Number of bytes of host memory used +host_seconds 1281.38 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 181635953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 127168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory -system.physmem.bytes_read::total 246528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 127168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 127168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3852 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1495948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 564651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 839447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2900046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1495948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1495948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1495948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 564651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 839447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2900046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3852 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory +system.physmem.bytes_read::total 245760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3840 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1494113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 560763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2890376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1494113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1494113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1494113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 560763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2890376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3840 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3852 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3840 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 246528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 245760 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 246528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 245760 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 309 # Per bank write bursts -system.physmem.perBankRdBursts::1 223 # Per bank write bursts +system.physmem.perBankRdBursts::1 220 # Per bank write bursts system.physmem.perBankRdBursts::2 142 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::3 304 # Per bank write bursts system.physmem.perBankRdBursts::4 300 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts system.physmem.perBankRdBursts::7 237 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts -system.physmem.perBankRdBursts::9 218 # Per bank write bursts -system.physmem.perBankRdBursts::10 293 # Per bank write bursts +system.physmem.perBankRdBursts::9 219 # Per bank write bursts +system.physmem.perBankRdBursts::10 292 # Per bank write bursts system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 193 # Per bank write bursts -system.physmem.perBankRdBursts::13 212 # Per bank write bursts +system.physmem.perBankRdBursts::12 191 # Per bank write bursts +system.physmem.perBankRdBursts::13 211 # Per bank write bursts system.physmem.perBankRdBursts::14 211 # Per bank write bursts system.physmem.perBankRdBursts::15 194 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85008170000 # Total gap between requests +system.physmem.totGap 85026865500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3852 # Read request sizes (log2) +system.physmem.readPktSize::6 3840 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,17 +94,17 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.936842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 203.366462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.047629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 237 31.18% 31.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 182 23.95% 55.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 69 9.08% 64.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 96 12.63% 76.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 4.61% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 45 5.92% 87.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 2.37% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 14 1.84% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 64 8.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 760 # Bytes accessed per row activation -system.physmem.totQLat 36289181 # Total ticks spent queuing -system.physmem.totMemAccLat 108514181 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19260000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9420.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.332464 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.822648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.559029 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 236 30.77% 30.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 188 24.51% 55.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 81 10.56% 65.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 90 11.73% 77.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 32 4.17% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 41 5.35% 87.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 12 1.56% 88.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 2.09% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71 9.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 767 # Bytes accessed per row activation +system.physmem.totQLat 42919435 # Total ticks spent queuing +system.physmem.totMemAccLat 114919435 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11176.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28170.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29926.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 3.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3085 # Number of row buffer hits during reads +system.physmem.readRowHits 3071 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.97 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22068579.96 # Average gap between requests -system.physmem.pageHitRate 80.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2721600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1485000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22142412.89 # Average gap between requests +system.physmem.pageHitRate 79.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2691360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1468500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2339255205 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48949672500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56861323425 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.935094 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81434793722 # Time in different power states -system.physmem_0.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_0.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2327866605 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48973677750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56875372215 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.916551 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81470624236 # Time in different power states +system.physmem_0.memoryStateTime::REF 2839200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 733662278 # Time in different power states +system.physmem_0.memoryStateTime::ACT 716299514 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3001320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1637625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13540800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3107160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1695375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13657800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2301878880 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48982450500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56854458645 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.854443 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81486384408 # Time in different power states -system.physmem_1.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_1.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2285718525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 49010649750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56868303810 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.833418 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81532427147 # Time in different power states +system.physmem_1.memoryStateTime::REF 2839200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 678791592 # Time in different power states +system.physmem_1.memoryStateTime::ACT 654496603 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85929478 # Number of BP lookups -system.cpu.branchPred.condPredicted 68409655 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6016514 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40103730 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39019729 # Number of BTB hits +system.cpu.branchPred.lookups 85926168 # Number of BP lookups +system.cpu.branchPred.condPredicted 68405800 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6016539 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40105937 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39014203 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.297007 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3701200 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81899 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.277874 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3700977 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81896 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170016628 # number of cpu cycles simulated +system.cpu.numCycles 170054019 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5612512 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349284796 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85929478 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42720929 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158258026 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12046973 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1522 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5612946 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349281739 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85926168 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42715180 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158272644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12047045 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1757 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2068 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78953849 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17938 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169897637 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150791 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.046975 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2232 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78951619 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17953 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169913124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150597 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17345965 10.21% 10.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30201314 17.78% 27.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31838054 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90512304 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17360928 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30199989 17.77% 27.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31841897 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90510310 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169897637 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505418 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.054416 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17565023 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17095500 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122663721 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6724834 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5848559 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11136257 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190151 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306621954 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27645544 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5848559 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37752791 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8406678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 578098 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108929543 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8381968 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278665579 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13416120 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3045260 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842372 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187359 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 31268 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 80203 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483123422 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196973277 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297590130 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005585 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169913124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505287 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.053946 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17565564 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17109843 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122664763 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6724358 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5848596 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11135936 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189930 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306620744 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27649027 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5848596 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37751386 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8466295 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579465 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108929053 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8338329 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278664885 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13415182 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3050613 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842331 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187361 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 37352 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26454 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483122463 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196977553 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297589838 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006277 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190146493 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23524 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23418 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13341047 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34139788 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476953 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2546690 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1793951 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264825375 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214906973 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5192109 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82644277 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219958197 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169897637 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264920 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017502 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190145534 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23432 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13338171 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34140942 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14477069 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2549253 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1790153 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264824262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45858 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214907174 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5191222 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82643318 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219950944 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 642 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169913124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264806 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017451 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52826553 31.09% 31.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36096362 21.25% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65782146 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13572889 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571303 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47864 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 520 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52840350 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36091754 21.24% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65793999 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13568282 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571301 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47256 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 182 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169897637 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169913124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35601312 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152935 0.28% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35600908 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152918 0.28% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available @@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35738 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 318 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 241 0.00% 66.46% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 812 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34382 0.06% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 216 0.00% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1033 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34370 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14078938 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3947834 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14078817 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3947857 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167350726 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918985 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167349433 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918954 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -523,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33019 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165198 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245711 0.11% 78.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460475 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460497 0.21% 78.75% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 206696 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32004909 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373295 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32005154 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13374554 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214906973 # Type of FU issued -system.cpu.iq.rate 1.264035 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53853755 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250591 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654805304 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 345511813 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204602678 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3952143 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2010627 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806422 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266627552 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2133176 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1600193 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214907174 # Type of FU issued +system.cpu.iq.rate 1.263758 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53853149 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250588 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654819591 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 345508564 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204603377 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952252 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011834 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806382 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266627232 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133091 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600790 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6243644 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7556 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7106 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1832319 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6244798 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7531 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7120 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832435 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 661 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25844 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 768 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5848559 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5681569 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 36478 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264887188 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5848596 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5681557 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36821 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264886087 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34139788 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476953 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3814 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29479 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7106 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3233640 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247282 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6480922 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207527385 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30721175 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7379588 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34140942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14477069 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23450 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3913 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7120 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3233413 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247375 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6480788 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207526427 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30720305 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7380747 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15963 # number of nop insts executed -system.cpu.iew.exec_refs 43860513 # number of memory reference insts executed -system.cpu.iew.exec_branches 44937173 # Number of branches executed -system.cpu.iew.exec_stores 13139338 # Number of stores executed -system.cpu.iew.exec_rate 1.220630 # Inst execution rate -system.cpu.iew.wb_sent 206744227 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206409100 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129466460 # num instructions producing a value -system.cpu.iew.wb_consumers 221676348 # num instructions consuming a value +system.cpu.iew.exec_nop 15967 # number of nop insts executed +system.cpu.iew.exec_refs 43860812 # number of memory reference insts executed +system.cpu.iew.exec_branches 44937004 # Number of branches executed +system.cpu.iew.exec_stores 13140507 # Number of stores executed +system.cpu.iew.exec_rate 1.220356 # Inst execution rate +system.cpu.iew.wb_sent 206744573 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206409759 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129475490 # num instructions producing a value +system.cpu.iew.wb_consumers 221697589 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.214052 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584034 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213789 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584018 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69543087 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69541306 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5841587 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158455572 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146380 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646562 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5841613 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158471260 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146267 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646384 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73674398 46.50% 46.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41276379 26.05% 72.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22551197 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9630660 6.08% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3550983 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2150131 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1280461 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 988669 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3352694 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73683520 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41279039 26.05% 72.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22557642 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9629639 6.08% 92.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3553008 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2147976 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1280790 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 986719 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3352927 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158455572 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158471260 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,186 +655,186 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction -system.cpu.commit.bw_lim_events 3352694 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3352927 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 406291105 # The number of ROB reads -system.cpu.rob.rob_writes 513842853 # The number of ROB writes -system.cpu.timesIdled 3394 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 118991 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 406304779 # The number of ROB reads +system.cpu.rob.rob_writes 513839131 # The number of ROB writes +system.cpu.timesIdled 3408 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 140895 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986730 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986730 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013448 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013448 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218960053 # number of integer regfile reads -system.cpu.int_regfile_writes 114514072 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904445 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441481 # number of floating regfile writes -system.cpu.cc_regfile_reads 709585079 # number of cc regfile reads -system.cpu.cc_regfile_writes 229544416 # number of cc regfile writes -system.cpu.misc_regfile_reads 59313443 # number of misc regfile reads +system.cpu.cpi 0.986947 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986947 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013225 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013225 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218958782 # number of integer regfile reads +system.cpu.int_regfile_writes 114515411 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904346 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441525 # number of floating regfile writes +system.cpu.cc_regfile_reads 709584302 # number of cc regfile reads +system.cpu.cc_regfile_writes 229541480 # number of cc regfile writes +system.cpu.misc_regfile_reads 59315386 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72897 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.439547 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41117509 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73409 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.115367 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 497141250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.439547 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998905 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998905 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72889 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.417696 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41115745 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73401 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.152382 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 506067250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.417696 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998863 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82532283 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82532283 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28730746 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28730746 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341850 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341850 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82529901 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82529901 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28729389 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28729389 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341441 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341441 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22145 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22145 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41072596 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41072596 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41072957 # number of overall hits -system.cpu.dcache.overall_hits::total 41072957 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89111 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22437 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22437 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 262 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 262 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 111548 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 111548 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 111666 # number of overall misses -system.cpu.dcache.overall_misses::total 111666 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 835319240 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 835319240 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 222952999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 222952999 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2325000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2325000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1058272239 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1058272239 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1058272239 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1058272239 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28819857 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28819857 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 41070830 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41070830 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41071191 # number of overall hits +system.cpu.dcache.overall_hits::total 41071191 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89283 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89283 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22846 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22846 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112129 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112245 # number of overall misses +system.cpu.dcache.overall_misses::total 112245 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 853218237 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 853218237 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 244809935 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 244809935 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2319500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2319500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1098028172 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1098028172 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1098028172 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1098028172 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28818672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28818672 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 477 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 477 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41184144 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41184144 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41184623 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41184623 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003092 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003092 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001815 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001815 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002709 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002709 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9373.918371 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9373.918371 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9936.845345 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9936.845345 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8874.045802 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8874.045802 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9487.146690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9487.146690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9477.121407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9477.121407 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7730 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41182959 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41182959 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41183436 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41183436 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003098 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003098 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001848 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001848 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.243187 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.243187 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002723 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002725 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002725 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9556.334767 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9556.334767 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10715.658540 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10715.658540 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8921.153846 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8921.153846 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9792.544052 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9792.544052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9782.423912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9782.423912 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 167 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10490 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 532 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14.530075 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 844 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.428910 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64874 # number of writebacks -system.cpu.dcache.writebacks::total 64874 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24383 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24383 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13871 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 13871 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38254 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38254 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38254 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38254 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64728 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64728 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8566 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8566 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73294 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73294 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73409 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73409 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 491417758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 491417758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74043249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 74043249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 565461007 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 565461007 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 566443507 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 566443507 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 64871 # number of writebacks +system.cpu.dcache.writebacks::total 64871 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24560 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24560 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14281 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14281 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38841 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38841 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38841 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38841 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64723 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64723 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8565 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8565 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73288 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73288 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73401 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73401 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 526941010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 526941010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81775757 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 81775757 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 905500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 905500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 608716767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 608716767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 609622267 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 609622267 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.236897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.236897 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7592.042980 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7592.042980 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8643.853491 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8643.853491 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8543.478261 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8543.478261 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7714.969943 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7714.969943 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7716.267855 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7716.267855 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8141.479999 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8141.479999 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9547.665733 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9547.665733 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8013.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8013.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8305.817692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8305.817692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8305.367325 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8305.367325 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54440 # number of replacements -system.cpu.icache.tags.tagsinuse 510.617911 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78896507 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54952 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1435.734951 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84258685250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.617911 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997301 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 54441 # number of replacements +system.cpu.icache.tags.tagsinuse 510.602621 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78893897 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54953 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1435.661329 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84271974250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.602621 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997271 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997271 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id @@ -842,188 +842,188 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 272 system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157962600 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157962600 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78896507 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78896507 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78896507 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78896507 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78896507 # number of overall hits -system.cpu.icache.overall_hits::total 78896507 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57317 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57317 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57317 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57317 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57317 # number of overall misses -system.cpu.icache.overall_misses::total 57317 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 586515679 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 586515679 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 586515679 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 586515679 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 586515679 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 586515679 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78953824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78953824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78953824 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78953824 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78953824 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78953824 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000726 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000726 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000726 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000726 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000726 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000726 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10232.839803 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10232.839803 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10232.839803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10232.839803 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 47827 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 10 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2525 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.941386 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 157958145 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157958145 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78893897 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78893897 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78893897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78893897 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78893897 # number of overall hits +system.cpu.icache.overall_hits::total 78893897 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57699 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57699 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57699 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57699 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57699 # number of overall misses +system.cpu.icache.overall_misses::total 57699 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 607673936 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 607673936 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 607673936 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 607673936 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 607673936 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 607673936 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78951596 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78951596 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78951596 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78951596 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78951596 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78951596 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000731 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000731 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000731 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000731 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000731 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000731 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10531.793203 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10531.793203 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10531.793203 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10531.793203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10531.793203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10531.793203 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 55459 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 532 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2752 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.152253 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 177.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2365 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2365 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2365 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2365 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2365 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2365 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54952 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54952 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54952 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54952 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54952 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54952 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 466993997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 466993997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 466993997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 466993997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 466993997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 466993997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2746 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2746 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2746 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2746 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2746 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2746 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54953 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54953 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54953 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54953 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54953 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54953 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 509320483 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 509320483 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 509320483 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 509320483 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 509320483 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 509320483 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000696 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000696 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000696 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8498.216571 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8498.216571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8498.216571 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8498.216571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8498.216571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8498.216571 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9268.292595 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9268.292595 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9268.292595 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9268.292595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9268.292595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9268.292595 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 9345 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9345 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 9289 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9289 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1367 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 1375 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2661.020186 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 178437 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3588 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 49.731605 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2667.127708 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 178431 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3576 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 49.896812 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 702.071269 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1377.111854 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 421.096641 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 160.740422 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.042851 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.025702 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009811 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.162416 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 262 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3326 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 701.951887 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1376.042782 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 417.094048 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 172.038991 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.042844 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.083987 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.025457 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010500 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.162789 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 260 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3316 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 86 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 749 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 83 # 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16505250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16505250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120193759 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49633000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 169826759 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120193759 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49633000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68601184 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 238427943 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.007828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020816 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021323 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010150 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021269 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035470 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52440.613991 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58060.679612 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53597.422062 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34908.254405 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56717.021277 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56717.021277 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53865.272196 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46304.115967 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035355 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60551.012091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65340.729783 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61525.485152 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37943.132743 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69349.789916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69349.789916 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60551.012091 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66621.476510 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62207.604029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60551.012091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66621.476510 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52540.313574 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 119724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 119724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8637 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8637 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 321596 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12367040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2213 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 195448 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011323 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105804 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 119718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 119718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64871 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109906 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211673 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 321579 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8849408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12366400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2155 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 195380 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011030 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104442 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 193235 98.87% 98.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 2213 1.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 193225 98.90% 98.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 2155 1.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 195448 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 161491500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 195380 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 161483500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82814471 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82836732 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110208992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110205232 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3617 # Transaction distribution -system.membus.trans_dist::ReadResp 3617 # Transaction distribution -system.membus.trans_dist::ReadExReq 235 # Transaction distribution -system.membus.trans_dist::ReadExResp 235 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7704 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 246528 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3602 # Transaction distribution +system.membus.trans_dist::ReadResp 3602 # Transaction distribution +system.membus.trans_dist::ReadExReq 238 # Transaction distribution +system.membus.trans_dist::ReadExResp 238 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7680 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 245760 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3852 # Request fanout histogram +system.membus.snoop_fanout::samples 3840 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3852 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3840 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3852 # Request fanout histogram -system.membus.reqLayer0.occupancy 5007645 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3840 # Request fanout histogram +system.membus.reqLayer0.occupancy 4975502 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36124927 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20238053 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 7ececc2b6..e6a9622eb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491000 # Number of ticks simulated final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1699536 # Simulator instruction rate (inst/s) -host_op_rate 1791584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 982302061 # Simulator tick rate (ticks/s) -host_mem_usage 304728 # Number of bytes of host memory used -host_seconds 101.39 # Real time elapsed on the host +host_inst_rate 1940320 # Simulator instruction rate (inst/s) +host_op_rate 2045410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1121471108 # Simulator tick rate (ticks/s) +host_mem_usage 304628 # Number of bytes of host memory used +host_seconds 88.81 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 181650341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 230024466 # Request fanout histogram -system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram +system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::3 189860051 82.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 230024466 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 62a10ca2c..6ce1a7f0e 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.230173 # Number of seconds simulated -sim_ticks 230173357000 # Number of ticks simulated -final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 230173357500 # Number of ticks simulated +final_tick 230173357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1229194 # Simulator instruction rate (inst/s) -host_op_rate 1295881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1646435898 # Simulator tick rate (ticks/s) -host_mem_usage 312932 # Number of bytes of host memory used -host_seconds 139.80 # Real time elapsed on the host +host_inst_rate 1098511 # Simulator instruction rate (inst/s) +host_op_rate 1158108 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1471393960 # Simulator tick rate (ticks/s) +host_mem_usage 313104 # Number of bytes of host memory used +host_seconds 156.43 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 181165370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 460346714 # number of cpu cycles simulated +system.cpu.numCycles 460346715 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842483 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 40540779 # nu system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460346713.998000 # Number of busy cycles +system.cpu.num_busy_cycles 460346714.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 40300311 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650742 # Class of executed instruction system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.619277 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619277 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id @@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788 system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34437000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34437000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58544500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58544500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92981500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92981500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93035000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 93035000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -329,24 +329,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50053.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50053.779070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53222.272727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53222.272727 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52003.076063 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52003.076063 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.992598 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992604 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992598 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id @@ -370,12 +370,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112370500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112370500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112370500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112370500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112370500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112370500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses @@ -388,12 +388,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.711242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36830.711242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36830.711242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36830.711242 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,34 +408,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106268500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 106268500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106268500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 106268500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106268500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 106268500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 107794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 107794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 107794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 107794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 107794500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 107794500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34830.711242 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34830.711242 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35330.875123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35330.875123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.663358 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1675.663349 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036753 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588818 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_misses::total 3453 # nu system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses system.cpu.l2cache.overall_misses::total 3453 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89997500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32887000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 122884500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56814500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56814500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 89997500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 89701500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179699000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 89997500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 89701500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179699000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 90862500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33203000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 124065500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses) @@ -508,17 +508,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52051.764025 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.392405 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52047.649301 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52027.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52027.930403 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52041.413264 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52041.413264 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52536.392405 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52547.861076 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3453 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70024500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69822000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 139846500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70024500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69822000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 139846500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses @@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution @@ -585,19 +585,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4856 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -624,9 +622,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |