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-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini62
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr1
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/o3-timing/simout11
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt16
4 files changed, 56 insertions, 34 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 963ba1258..a3174479b 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -135,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
@@ -145,11 +146,7 @@ eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
numThreads=1
-predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -157,6 +154,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -191,6 +189,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
@@ -208,7 +207,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
@@ -498,8 +496,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
+forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
@@ -558,6 +557,7 @@ id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
@@ -565,6 +565,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
@@ -582,7 +583,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
@@ -607,6 +607,7 @@ children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
@@ -628,19 +629,27 @@ mem_side=system.membus.slave[1]
[system.cpu.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu.l2cache.tags]
@@ -657,13 +666,16 @@ size=1048576
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -673,14 +685,16 @@ eventq_index=0
type=LiveProcess
cmd=twolf smred
cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
@@ -710,11 +724,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
@@ -745,7 +762,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
@@ -754,6 +771,7 @@ clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
index 1a4f96712..341b479f7 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
@@ -1 +1,2 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index 8dd189a74..e77a79916 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -1,12 +1,15 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 21:53:28
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 12:02:59
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x4f074c0
+ 0: system.cpu.isa: ISA system set to: 0 0x2e8fab0
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
@@ -22,4 +25,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 74056845500 because target called exit()
+122 123 124 Exiting @ tick 85027009000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 93505db81..3b1c45895 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.085027 # Nu
sim_ticks 85027009000 # Number of ticks simulated
final_tick 85027009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 134467 # Simulator instruction rate (inst/s)
-host_op_rate 141751 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 66356016 # Simulator tick rate (ticks/s)
-host_mem_usage 312828 # Number of bytes of host memory used
-host_seconds 1281.38 # Real time elapsed on the host
+host_inst_rate 123827 # Simulator instruction rate (inst/s)
+host_op_rate 130534 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61105425 # Simulator tick rate (ticks/s)
+host_mem_usage 242728 # Number of bytes of host memory used
+host_seconds 1391.48 # Real time elapsed on the host
sim_insts 172303021 # Number of instructions simulated
sim_ops 181635953 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -448,7 +448,7 @@ system.cpu.iq.iqInstsAdded 264824262 # Nu
system.cpu.iq.iqNonSpecInstsAdded 45858 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 214907174 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 5191222 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 82643318 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 83234167 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 219950944 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 642 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 169913124 # Number of insts issued each cycle
@@ -541,10 +541,10 @@ system.cpu.iq.rate 1.263758 # In
system.cpu.iq.fu_busy_cnt 53853149 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.250588 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 654819591 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 345508564 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_writes 346099299 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 204603377 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3952252 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2011834 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 2011948 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1806382 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 266627232 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2133091 # Number of floating point alu accesses