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-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini37
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/o3-timing/simout12
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt452
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini37
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt15
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini72
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/simple-timing/simout8
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt396
9 files changed, 626 insertions, 411 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index ce56be1ef..eef0e971d 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -136,20 +136,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -444,20 +437,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -492,20 +478,13 @@ is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -529,12 +508,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index 442ecd78f..d10088405 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -1,14 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:20
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
-Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
-Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:37:09
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 83e315e2a..98dddaff0 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.105851 # Nu
sim_ticks 105850842000 # Number of ticks simulated
final_tick 105850842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 46914 # Simulator instruction rate (inst/s)
-host_tick_rate 26320721 # Simulator tick rate (ticks/s)
-host_mem_usage 259812 # Number of bytes of host memory used
-host_seconds 4021.58 # Real time elapsed on the host
-sim_insts 188667627 # Number of instructions simulated
+host_inst_rate 122767 # Simulator instruction rate (inst/s)
+host_op_rate 134419 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 75414821 # Simulator tick rate (ticks/s)
+host_mem_usage 227032 # Number of bytes of host memory used
+host_seconds 1403.58 # Real time elapsed on the host
+sim_insts 172314144 # Number of instructions simulated
+sim_ops 188667627 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 239936 # Number of bytes read from this memory
system.physmem.bytes_inst_read 128320 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
@@ -280,7 +282,8 @@ system.cpu.iew.wb_penalized 0 # nu
system.cpu.iew.wb_rate 1.155893 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.599323 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 188682015 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 172328532 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 188682015 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 146244510 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1636018 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 9791900 # The number of times a branch was mispredicted
@@ -301,7 +304,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 188552607 # Number of insts commited each cycle
-system.cpu.commit.count 188682015 # Number of instructions committed
+system.cpu.commit.committedInsts 172328532 # Number of instructions committed
+system.cpu.commit.committedOps 188682015 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 42498565 # Number of memory references committed
system.cpu.commit.loads 29851708 # Number of loads committed
@@ -316,12 +320,13 @@ system.cpu.rob.rob_reads 519029825 # Th
system.cpu.rob.rob_writes 693007050 # The number of ROB writes
system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 58483 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 188667627 # Number of Instructions Simulated
-system.cpu.committedInsts_total 188667627 # Number of Instructions Simulated
-system.cpu.cpi 1.122088 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.122088 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.891196 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.891196 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 172314144 # Number of Instructions Simulated
+system.cpu.committedOps 188667627 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 172314144 # Number of Instructions Simulated
+system.cpu.cpi 1.228580 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.228580 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.813948 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.813948 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1111988877 # number of integer regfile reads
system.cpu.int_regfile_writes 407368356 # number of integer regfile writes
system.cpu.fp_regfile_reads 2928539 # number of floating regfile reads
@@ -334,26 +339,39 @@ system.cpu.icache.total_refs 40615441 # To
system.cpu.icache.sampled_refs 3640 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 11158.088187 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1329.301324 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.649073 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 40615441 # number of ReadReq hits
-system.cpu.icache.demand_hits 40615441 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 40615441 # number of overall hits
-system.cpu.icache.ReadReq_misses 4234 # number of ReadReq misses
-system.cpu.icache.demand_misses 4234 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 4234 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 101275500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 101275500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 101275500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 40619675 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 40619675 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 40619675 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000104 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000104 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000104 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 23919.579594 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 23919.579594 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 23919.579594 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1329.301324 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.649073 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.649073 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 40615441 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 40615441 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 40615441 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 40615441 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 40615441 # number of overall hits
+system.cpu.icache.overall_hits::total 40615441 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 4234 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 4234 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 4234 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 4234 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 4234 # number of overall misses
+system.cpu.icache.overall_misses::total 4234 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 101275500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 101275500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 101275500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 101275500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 101275500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 101275500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 40619675 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 40619675 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 40619675 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 40619675 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 40619675 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 40619675 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000104 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000104 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000104 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23919.579594 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -362,27 +380,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 594 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 594 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 594 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 3640 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 3640 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 3640 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 74572500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 74572500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 74572500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 20486.950549 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 594 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 594 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 594 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 594 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 594 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3640 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 3640 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 3640 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 3640 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 3640 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 3640 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74572500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 74572500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74572500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 74572500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74572500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 74572500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20486.950549 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 53 # number of replacements
system.cpu.dcache.tagsinuse 1403.723956 # Cycle average of tags in use
@@ -390,40 +411,63 @@ system.cpu.dcache.total_refs 48643693 # To
system.cpu.dcache.sampled_refs 1846 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 26350.862947 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 1403.723956 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.342706 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 36234545 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 12356727 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 27791 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits 24630 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 48591272 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 48591272 # number of overall hits
-system.cpu.dcache.ReadReq_misses 1808 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 7560 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses 9368 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 9368 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 59529000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 237156500 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency 296685500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 296685500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 36236353 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 27793 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses 24630 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 48600640 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 48600640 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.000050 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate 0.000193 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.000193 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 32925.331858 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 31369.907407 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 31670.100342 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 31670.100342 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 1403.723956 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.342706 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.342706 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 36234545 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 36234545 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 12356727 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 12356727 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 27791 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 27791 # number of LoadLockedReq hits
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+system.cpu.dcache.StoreCondReq_hits::total 24630 # number of StoreCondReq hits
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+system.cpu.dcache.overall_hits::total 48591272 # number of overall hits
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+system.cpu.dcache.overall_misses::total 9368 # number of overall misses
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+system.cpu.dcache.LoadLockedReq_accesses::total 27793 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.StoreCondReq_accesses::total 24630 # number of StoreCondReq accesses(hits+misses)
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+system.cpu.dcache.overall_accesses::total 48600640 # number of overall (read+write) accesses
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+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000611 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000072 # miss rate for LoadLockedReq accesses
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+system.cpu.dcache.overall_miss_rate::cpu.data 0.000193 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32925.331858 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31369.907407 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31750 # average LoadLockedReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -432,33 +476,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 18 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 1053 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 6469 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 7522 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 7522 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 755 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 1091 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 1846 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 1846 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 24116500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 38344000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 62460500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 62460500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.000038 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.000038 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31942.384106 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33835.590466 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33835.590466 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33835.590466 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1923.480613 # Cycle average of tags in use
@@ -466,36 +519,75 @@ system.cpu.l2cache.total_refs 1714 # To
system.cpu.l2cache.sampled_refs 2676 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.640508 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 1919.476269 # Average occupied blocks per context
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-system.cpu.l2cache.occ_percent::1 0.000122 # Average percentage of cache occupancy
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-system.cpu.l2cache.ReadReq_avg_miss_latency 34286.460276 # average ReadReq miss latency
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34347.922849 # average ReadReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34359.054670 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -504,31 +596,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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-system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits
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-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.606826 # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.739783 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.952254 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.952254 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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+system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2005 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 662 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 2667 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2005 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1744 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 3749 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2005 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1744 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 3749 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62251500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20643500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82895000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33590000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33590000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62251500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54233500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 116485000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62251500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54233500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 116485000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876821 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31048.129676 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31183.534743 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.362292 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 01def30a3..8e458b793 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
@@ -64,7 +95,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -88,7 +119,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
index f2a9f0661..36b361cbc 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -1,12 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:50:48
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:37:27
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 079a70f11..5d6608220 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.103107 # Nu
sim_ticks 103106771000 # Number of ticks simulated
final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3006793 # Simulator instruction rate (inst/s)
-host_tick_rate 1643182108 # Simulator tick rate (ticks/s)
-host_mem_usage 213456 # Number of bytes of host memory used
-host_seconds 62.75 # Real time elapsed on the host
-sim_insts 188670900 # Number of instructions simulated
+host_inst_rate 3118510 # Simulator instruction rate (inst/s)
+host_op_rate 3414466 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1865971013 # Simulator tick rate (ticks/s)
+host_mem_usage 216012 # Number of bytes of host memory used
+host_seconds 55.26 # Real time elapsed on the host
+sim_insts 172317417 # Number of instructions simulated
+sim_ops 188670900 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 869973902 # Number of bytes read from this memory
system.physmem.bytes_inst_read 759440240 # Number of instructions bytes read from this memory
system.physmem.bytes_written 45252940 # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 400 # Nu
system.cpu.numCycles 206213543 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 188670900 # Number of instructions executed
+system.cpu.committedInsts 172317417 # Number of instructions committed
+system.cpu.committedOps 188670900 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3504894 # number of times a function call or return occured
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index 3f54c6512..f90360da8 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
@@ -94,20 +106,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -115,9 +120,21 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
@@ -130,25 +147,18 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
@@ -159,7 +169,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
@@ -167,7 +177,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
index b21763742..322e5b2f2 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,12 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:52:01
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:38:33
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index d861ddab1..f86e3b057 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.232077 # Nu
sim_ticks 232077154000 # Number of ticks simulated
final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1497030 # Simulator instruction rate (inst/s)
-host_tick_rate 1846187485 # Simulator tick rate (ticks/s)
-host_mem_usage 222460 # Number of bytes of host memory used
-host_seconds 125.71 # Real time elapsed on the host
-sim_insts 188185929 # Number of instructions simulated
+host_inst_rate 1867609 # Simulator instruction rate (inst/s)
+host_op_rate 2045232 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2522247357 # Simulator tick rate (ticks/s)
+host_mem_usage 224952 # Number of bytes of host memory used
+host_seconds 92.01 # Real time elapsed on the host
+sim_insts 171842491 # Number of instructions simulated
+sim_ops 188185929 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 220992 # Number of bytes read from this memory
system.physmem.bytes_inst_read 110656 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
@@ -64,7 +66,8 @@ system.cpu.workload.num_syscalls 400 # Nu
system.cpu.numCycles 464154308 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 188185929 # Number of instructions executed
+system.cpu.committedInsts 171842491 # Number of instructions committed
+system.cpu.committedOps 188185929 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3504894 # number of times a function call or return occured
@@ -88,26 +91,39 @@ system.cpu.icache.total_refs 189857010 # To
system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 62227.797443 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1147.981155 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.560538 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 189857010 # number of ReadReq hits
-system.cpu.icache.demand_hits 189857010 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 189857010 # number of overall hits
-system.cpu.icache.ReadReq_misses 3051 # number of ReadReq misses
-system.cpu.icache.demand_misses 3051 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 3051 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 115332000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 115332000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 115332000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 189860061 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 189860061 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 189860061 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 37801.376598 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 37801.376598 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1147.981155 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.560538 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.560538 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 189857010 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 189857010 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 189857010 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 189857010 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 189857010 # number of overall hits
+system.cpu.icache.overall_hits::total 189857010 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses
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+system.cpu.icache.overall_misses::total 3051 # number of overall misses
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+system.cpu.icache.ReadReq_miss_latency::total 115332000 # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total 115332000 # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total 115332000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 189860061 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -116,26 +132,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 3051 # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses 3051 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 106179000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 106179000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 106179000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000016 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000016 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000016 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 40 # number of replacements
system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use
@@ -143,36 +157,57 @@ system.cpu.dcache.total_refs 42007359 # To
system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 23480.916154 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.ReadReq_misses 689 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 1100 # number of WriteReq misses
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-system.cpu.dcache.ReadReq_miss_latency 36190000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 61264000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 97454000 # number of demand (read+write) miss cycles
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-system.cpu.dcache.ReadReq_accesses 29600047 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.overall_accesses 41964334 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.000023 # miss rate for ReadReq accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency 52525.399129 # average ReadReq miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -181,30 +216,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 16 # number of writebacks
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-system.cpu.dcache.ReadReq_mshr_misses 689 # number of ReadReq MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency 34123000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use
@@ -212,36 +249,75 @@ system.cpu.l2cache.total_refs 1379 # To
system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.582102 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
+system.cpu.l2cache.overall_misses::total 3453 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89908000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32864000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 122772000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56784000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 56784000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 89908000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 89648000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 179556000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 89908000 # number of overall miss cycles
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+system.cpu.l2cache.overall_miss_latency::total 179556000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -250,30 +326,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 2361 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 1092 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 3453 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 3453 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 94440000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 43680000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 138120000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 138120000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631283 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992727 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.713430 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.713430 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------