diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt | 2066 |
1 files changed, 1033 insertions, 1033 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 62a8ddc44..c833a13ad 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,1037 +1,1037 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.102721 # Number of seconds simulated -sim_ticks 102721386000 # Number of ticks simulated -final_tick 102721386000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115023 # Simulator instruction rate (inst/s) -host_op_rate 192789 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89461870 # Simulator tick rate (ticks/s) -host_mem_usage 308536 # Number of bytes of host memory used -host_seconds 1148.21 # Real time elapsed on the host -sim_insts 132071192 # Number of instructions simulated -sim_ops 221363384 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 235072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130944 # Number of bytes read from this memory -system.physmem.bytes_read::total 366016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 235072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 235072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3673 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2046 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5719 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2288443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1274749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3563192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2288443 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2288443 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2288443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1274749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3563192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5719 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5719 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 366016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 366016 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 315 # Per bank write bursts -system.physmem.perBankRdBursts::1 393 # Per bank write bursts -system.physmem.perBankRdBursts::2 481 # Per bank write bursts -system.physmem.perBankRdBursts::3 362 # Per bank write bursts -system.physmem.perBankRdBursts::4 367 # Per bank write bursts -system.physmem.perBankRdBursts::5 335 # Per bank write bursts -system.physmem.perBankRdBursts::6 442 # Per bank write bursts -system.physmem.perBankRdBursts::7 357 # Per bank write bursts -system.physmem.perBankRdBursts::8 405 # Per bank write bursts -system.physmem.perBankRdBursts::9 298 # Per bank write bursts -system.physmem.perBankRdBursts::10 258 # Per bank write bursts -system.physmem.perBankRdBursts::11 270 # Per bank write bursts -system.physmem.perBankRdBursts::12 235 # Per bank write bursts -system.physmem.perBankRdBursts::13 489 # Per bank write bursts -system.physmem.perBankRdBursts::14 424 # Per bank write bursts -system.physmem.perBankRdBursts::15 288 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 102721127000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5719 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 987 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1259 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 289.245433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.404896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.969258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 547 43.45% 43.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 270 21.45% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 107 8.50% 73.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51 4.05% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 47 3.73% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 64 5.08% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 1.91% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.99% 90.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 124 9.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1259 # Bytes accessed per row activation -system.physmem.totQLat 198070500 # Total ticks spent queuing -system.physmem.totMemAccLat 305301750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 28595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34633.76 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53383.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.56 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4452 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 17961379.09 # Average gap between requests -system.physmem.pageHitRate 77.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5319300 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2808300 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 21791280 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 308549280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 94282560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 17303520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 739487790 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 445716000 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 23991769245 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 25627073595 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.481384 # Core power per rank (mW) -system.physmem_0.totalIdleTime 102469123000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 33581500 # Time in different power states -system.physmem_0.memoryStateTime::REF 131264000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 99687058000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1160707250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87094500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1621680750 # Time in different power states -system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1969605 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19042380 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 233563200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 75326640 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12588960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 599034660 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 319716000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 24137455500 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 25402424025 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.294404 # Core power per rank (mW) -system.physmem_1.totalIdleTime 102523153750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 23880000 # Time in different power states -system.physmem_1.memoryStateTime::REF 99310000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 100377149750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 832585250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 74819500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1313641500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40475108 # Number of BP lookups -system.cpu.branchPred.condPredicted 40475108 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6616133 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 34806541 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3130768 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 590894 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 34806541 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 9997740 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 24808801 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 4890379 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 205442773 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 45893468 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 415890095 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40475108 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13128508 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 151898710 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14677491 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 200 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 64355 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 603 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 40893606 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1496111 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 12 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 205202132 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.402306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.658033 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 98918732 48.21% 48.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5142243 2.51% 50.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5340112 2.60% 53.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5342271 2.60% 55.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5947890 2.90% 58.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5817544 2.84% 61.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5684313 2.77% 64.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4746268 2.31% 66.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68262759 33.27% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 205202132 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.197014 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.024360 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31935878 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86571693 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 61623233 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17732583 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7338745 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 585424017 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7338745 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 41662208 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46227710 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28975 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68218759 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41725735 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 547333455 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1808 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36710047 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4936211 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 172798 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 624155686 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1473918398 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 966803184 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 14714209 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 364726236 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2257 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2274 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89803577 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 127813025 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 45569326 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 76700063 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25076085 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 486700618 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 63617 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 336591199 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1075816 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 265400851 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 520101355 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 62372 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 205202132 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.640291 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.801229 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72558879 35.36% 35.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46563371 22.69% 58.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32833591 16.00% 74.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20829399 10.15% 84.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 14957397 7.29% 91.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8327086 4.06% 95.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5158088 2.51% 98.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2335665 1.14% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1638656 0.80% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 205202132 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 746075 18.99% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2709270 68.98% 87.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 425878 10.84% 98.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 43262 1.10% 99.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 3383 0.09% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212158 0.36% 0.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 215249611 63.95% 64.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800532 0.24% 64.55% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7048368 2.09% 66.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1789279 0.53% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 82235879 24.43% 91.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26412297 7.85% 99.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 1712250 0.51% 99.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 130825 0.04% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 336591199 # Type of FU issued -system.cpu.iq.rate 1.638370 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3927868 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011670 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 875283157 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 737961913 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 314539873 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8105057 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 15024545 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3526208 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 335233754 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4073155 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18221671 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 71163438 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 53029 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 858947 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 25053609 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50433 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7338745 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35257397 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 584477 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 486764235 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1231542 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 127813025 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 45569326 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23100 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 542722 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38323 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 858947 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1297189 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6715157 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8012346 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 324846022 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 80370790 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11745177 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 105939673 # number of memory reference insts executed -system.cpu.iew.exec_branches 18800592 # Number of branches executed -system.cpu.iew.exec_stores 25568883 # Number of stores executed -system.cpu.iew.exec_rate 1.581200 # Inst execution rate -system.cpu.iew.wb_sent 321037948 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 318066081 # cumulative count of insts written-back -system.cpu.iew.wb_producers 255309822 # num instructions producing a value -system.cpu.iew.wb_consumers 434053597 # num instructions consuming a value -system.cpu.iew.wb_rate 1.548198 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588199 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 265431223 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6620631 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 163283495 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.355700 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.936592 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 66681947 40.84% 40.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 54877402 33.61% 74.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13218916 8.10% 82.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10716769 6.56% 89.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5408933 3.31% 92.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3143149 1.92% 94.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1097453 0.67% 95.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1149760 0.70% 95.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6989166 4.28% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 163283495 # Number of insts commited each cycle -system.cpu.commit.committedInsts 132071192 # Number of instructions committed -system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 77165304 # Number of memory references committed -system.cpu.commit.loads 56649587 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 12326938 # Number of branches committed -system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. -system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. -system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 55945136 25.27% 90.41% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20410230 9.22% 99.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 704451 0.32% 99.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6989166 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 643088936 # The number of ROB reads -system.cpu.rob.rob_writes 1015902477 # The number of ROB writes -system.cpu.timesIdled 2803 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 240641 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 132071192 # Number of Instructions Simulated -system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.555546 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.555546 # CPI: Total CPI of All Threads -system.cpu.ipc 0.642861 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.642861 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 522853571 # number of integer regfile reads -system.cpu.int_regfile_writes 287693953 # number of integer regfile writes -system.cpu.fp_regfile_reads 4488277 # number of floating regfile reads -system.cpu.fp_regfile_writes 3288210 # number of floating regfile writes -system.cpu.cc_regfile_reads 106934935 # number of cc regfile reads -system.cpu.cc_regfile_writes 65654592 # number of cc regfile writes -system.cpu.misc_regfile_reads 175824659 # number of misc regfile reads -system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 101 # number of replacements -system.cpu.dcache.tags.tagsinuse 1519.152295 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 82373071 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2121 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 38836.902876 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1519.152295 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.370887 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.370887 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2020 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 426 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1452 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.493164 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 164753603 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 164753603 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 61858750 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 61858750 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513717 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513717 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 82372467 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 82372467 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 82372467 # number of overall hits -system.cpu.dcache.overall_hits::total 82372467 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1260 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1260 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2014 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2014 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3274 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3274 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3274 # number of overall misses -system.cpu.dcache.overall_misses::total 3274 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128800000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128800000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 138047000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 138047000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 266847000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 266847000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 266847000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 266847000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 61860010 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 61860010 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82375741 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82375741 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82375741 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82375741 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000098 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000098 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102222.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 102222.222222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68543.694141 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68543.694141 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81504.886988 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81504.886988 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81504.886988 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81504.886988 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 58 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 127 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 22 # number of writebacks -system.cpu.dcache.writebacks::total 22 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 652 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 652 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 663 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 663 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 663 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 663 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 608 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2003 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2611 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2611 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2611 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2611 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79597500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 79597500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135457500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 135457500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215055000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215055000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215055000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215055000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 130916.940789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 130916.940789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67627.309036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67627.309036 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82364.994255 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82364.994255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82364.994255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82364.994255 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 6438 # number of replacements -system.cpu.icache.tags.tagsinuse 1691.823634 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 40880551 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8435 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4846.538352 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1691.823634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.826086 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.826086 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1997 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 850 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 731 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.975098 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 81796128 # Number of tag accesses -system.cpu.icache.tags.data_accesses 81796128 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 40880552 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 40880552 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 40880552 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 40880552 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 40880552 # number of overall hits -system.cpu.icache.overall_hits::total 40880552 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13050 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13050 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13050 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13050 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13050 # number of overall misses -system.cpu.icache.overall_misses::total 13050 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 646702000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 646702000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 646702000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 646702000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 646702000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 646702000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 40893602 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 40893602 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 40893602 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 40893602 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 40893602 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 40893602 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000319 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000319 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000319 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000319 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000319 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000319 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49555.708812 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49555.708812 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49555.708812 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49555.708812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49555.708812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49555.708812 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2923 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 38 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 76.921053 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6438 # number of writebacks -system.cpu.icache.writebacks::total 6438 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4125 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4125 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4125 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4125 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4125 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4125 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8925 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 8925 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 8925 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 8925 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 8925 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 8925 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 457055500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 457055500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 457055500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 457055500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 457055500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 457055500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000218 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000218 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51210.700280 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51210.700280 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51210.700280 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51210.700280 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51210.700280 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51210.700280 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3920.889398 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 11824 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5719 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.067494 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2430.261173 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.628224 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074166 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.045490 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.119656 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5719 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1010 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 536 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3957 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.174530 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 146063 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 146063 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 22 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 22 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6400 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6400 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 490 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 490 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4761 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4761 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 67 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 67 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4761 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 75 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 4836 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4761 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 75 # number of overall hits -system.cpu.l2cache.overall_hits::total 4836 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1507 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1507 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3673 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3673 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 539 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 539 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2046 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5719 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3673 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2046 # number of overall misses -system.cpu.l2cache.overall_misses::total 5719 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 126886000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 126886000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 392741000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 392741000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 77762500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 77762500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 392741000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 204648500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 597389500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 392741000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 204648500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 597389500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 22 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 22 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6400 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6400 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 490 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 490 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1515 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1515 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8434 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 8434 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 606 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 606 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8434 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2121 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 10555 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8434 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2121 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 10555 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994719 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994719 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.435499 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.435499 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.889439 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.889439 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.435499 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964639 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.541829 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.435499 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964639 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.541829 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84197.743862 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84197.743862 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106926.490607 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106926.490607 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 144271.799629 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 144271.799629 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106926.490607 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100023.704790 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 104456.985487 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106926.490607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100023.704790 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 104456.985487 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3673 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3673 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 539 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 539 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5719 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2046 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5719 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111816000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111816000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 356011000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 356011000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 72372500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 72372500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 356011000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 184188500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 540199500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 356011000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 184188500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 540199500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994719 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994719 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.435499 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.889439 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.889439 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964639 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.541829 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964639 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.541829 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74197.743862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74197.743862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96926.490607 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96926.490607 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 134271.799629 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 134271.799629 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96926.490607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90023.704790 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94456.985487 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96926.490607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90023.704790 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94456.985487 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18075 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 6619 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 9530 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6438 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1515 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1515 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 8925 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 606 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23796 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5323 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 29119 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 951744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1088896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 491 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 31424 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11536 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.091713 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.288633 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10478 90.83% 90.83% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1058 9.17% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11536 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15497500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13386000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3426999 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5719 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4212 # Transaction distribution -system.membus.trans_dist::ReadExReq 1507 # Transaction distribution -system.membus.trans_dist::ReadExResp 1507 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4212 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11438 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11438 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11438 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 366016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 366016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 366016 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5719 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5719 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5719 # Request fanout histogram -system.membus.reqLayer0.occupancy 6957500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 30309750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +sim_seconds 0.102720 +sim_ticks 102720088500 +final_tick 102720088500 +sim_freq 1000000000000 +host_inst_rate 110078 +host_op_rate 184500 +host_tick_rate 85614304 +host_mem_usage 318036 +host_seconds 1199.80 +sim_insts 132071192 +sim_ops 221363384 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.physmem.bytes_read::cpu.inst 235072 +system.physmem.bytes_read::cpu.data 130880 +system.physmem.bytes_read::total 365952 +system.physmem.bytes_inst_read::cpu.inst 235072 +system.physmem.bytes_inst_read::total 235072 +system.physmem.num_reads::cpu.inst 3673 +system.physmem.num_reads::cpu.data 2045 +system.physmem.num_reads::total 5718 +system.physmem.bw_read::cpu.inst 2288472 +system.physmem.bw_read::cpu.data 1274142 +system.physmem.bw_read::total 3562614 +system.physmem.bw_inst_read::cpu.inst 2288472 +system.physmem.bw_inst_read::total 2288472 +system.physmem.bw_total::cpu.inst 2288472 +system.physmem.bw_total::cpu.data 1274142 +system.physmem.bw_total::total 3562614 +system.physmem.readReqs 5718 +system.physmem.writeReqs 0 +system.physmem.readBursts 5718 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 365952 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 365952 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 308 +system.physmem.perBankRdBursts::1 393 +system.physmem.perBankRdBursts::2 481 +system.physmem.perBankRdBursts::3 362 +system.physmem.perBankRdBursts::4 367 +system.physmem.perBankRdBursts::5 342 +system.physmem.perBankRdBursts::6 448 +system.physmem.perBankRdBursts::7 369 +system.physmem.perBankRdBursts::8 368 +system.physmem.perBankRdBursts::9 301 +system.physmem.perBankRdBursts::10 254 +system.physmem.perBankRdBursts::11 270 +system.physmem.perBankRdBursts::12 266 +system.physmem.perBankRdBursts::13 486 +system.physmem.perBankRdBursts::14 412 +system.physmem.perBankRdBursts::15 291 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 102719826000 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 5718 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 4465 +system.physmem.rdQLenPdf::1 986 +system.physmem.rdQLenPdf::2 224 +system.physmem.rdQLenPdf::3 32 +system.physmem.rdQLenPdf::4 9 +system.physmem.rdQLenPdf::5 2 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 1260 +system.physmem.bytesPerActivate::mean 288.914286 +system.physmem.bytesPerActivate::gmean 165.287070 +system.physmem.bytesPerActivate::stdev 321.712301 +system.physmem.bytesPerActivate::0-127 547 43.41% 43.41% +system.physmem.bytesPerActivate::128-255 272 21.59% 65.00% +system.physmem.bytesPerActivate::256-383 106 8.41% 73.41% +system.physmem.bytesPerActivate::384-511 51 4.05% 77.46% +system.physmem.bytesPerActivate::512-639 47 3.73% 81.19% +system.physmem.bytesPerActivate::640-767 65 5.16% 86.35% +system.physmem.bytesPerActivate::768-895 23 1.83% 88.17% +system.physmem.bytesPerActivate::896-1023 25 1.98% 90.16% +system.physmem.bytesPerActivate::1024-1151 124 9.84% 100.00% +system.physmem.bytesPerActivate::total 1260 +system.physmem.totQLat 196407250 +system.physmem.totMemAccLat 303619750 +system.physmem.totBusLat 28590000 +system.physmem.avgQLat 34348.94 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 53098.94 +system.physmem.avgRdBW 3.56 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 3.56 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 0.03 +system.physmem.busUtilRead 0.03 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.05 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 4449 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 77.81 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 17964292.76 +system.physmem.pageHitRate 77.81 +system.physmem_0.actEnergy 5397840 +system.physmem_0.preEnergy 2846250 +system.physmem_0.readEnergy 21919800 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 308549280.000000 +system.physmem_0.actBackEnergy 94558440 +system.physmem_0.preBackEnergy 17132160 +system.physmem_0.actPowerDownEnergy 742713990 +system.physmem_0.prePowerDownEnergy 449076000 +system.physmem_0.selfRefreshEnergy 23986517265 +system.physmem_0.totalEnergy 25628757345 +system.physmem_0.averagePower 249.500927 +system.physmem_0.totalIdleTime 102467665750 +system.physmem_0.memoryStateTime::IDLE 33083500 +system.physmem_0.memoryStateTime::REF 131252000 +system.physmem_0.memoryStateTime::SREF 99669779750 +system.physmem_0.memoryStateTime::PRE_PDN 1169466500 +system.physmem_0.memoryStateTime::ACT 87760750 +system.physmem_0.memoryStateTime::ACT_PDN 1628746000 +system.physmem_1.actEnergy 3662820 +system.physmem_1.preEnergy 1935450 +system.physmem_1.readEnergy 18906720 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 232333920.000000 +system.physmem_1.actBackEnergy 74817060 +system.physmem_1.preBackEnergy 12559200 +system.physmem_1.actPowerDownEnergy 593057070 +system.physmem_1.prePowerDownEnergy 320340000 +system.physmem_1.selfRefreshEnergy 24140187000 +system.physmem_1.totalEnergy 25397799240 +system.physmem_1.averagePower 247.252505 +system.physmem_1.totalIdleTime 102523033750 +system.physmem_1.memoryStateTime::IDLE 23868000 +system.physmem_1.memoryStateTime::REF 98790000 +system.physmem_1.memoryStateTime::SREF 100388528750 +system.physmem_1.memoryStateTime::PRE_PDN 834205000 +system.physmem_1.memoryStateTime::ACT 74170500 +system.physmem_1.memoryStateTime::ACT_PDN 1300526250 +system.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.cpu.branchPred.lookups 40475084 +system.cpu.branchPred.condPredicted 40475084 +system.cpu.branchPred.condIncorrect 6616129 +system.cpu.branchPred.BTBLookups 34806523 +system.cpu.branchPred.BTBHits 0 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 0.000000 +system.cpu.branchPred.usedRAS 3130762 +system.cpu.branchPred.RASInCorrect 590891 +system.cpu.branchPred.indirectLookups 34806523 +system.cpu.branchPred.indirectHits 9997741 +system.cpu.branchPred.indirectMisses 24808782 +system.cpu.branchPredindirectMispredicted 4890378 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.cpu.workload.numSyscalls 400 +system.cpu.pwrStateResidencyTicks::ON 102720088500 +system.cpu.numCycles 205440178 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.fetch.icacheStallCycles 45893457 +system.cpu.fetch.Insts 415890076 +system.cpu.fetch.Branches 40475084 +system.cpu.fetch.predictedBranches 13128503 +system.cpu.fetch.Cycles 151898082 +system.cpu.fetch.SquashCycles 14677483 +system.cpu.fetch.TlbCycles 200 +system.cpu.fetch.MiscStallCycles 5835 +system.cpu.fetch.PendingTrapStallCycles 64355 +system.cpu.fetch.PendingQuiesceStallCycles 603 +system.cpu.fetch.IcacheWaitRetryStallCycles 216 +system.cpu.fetch.CacheLines 40893606 +system.cpu.fetch.IcacheSquashes 1496125 +system.cpu.fetch.ItlbSquashes 12 +system.cpu.fetch.rateDist::samples 205201489 +system.cpu.fetch.rateDist::mean 3.402316 +system.cpu.fetch.rateDist::stdev 3.658034 +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% +system.cpu.fetch.rateDist::0 98918093 48.21% 48.21% +system.cpu.fetch.rateDist::1 5142251 2.51% 50.71% +system.cpu.fetch.rateDist::2 5340115 2.60% 53.31% +system.cpu.fetch.rateDist::3 5342270 2.60% 55.92% +system.cpu.fetch.rateDist::4 5947887 2.90% 58.82% +system.cpu.fetch.rateDist::5 5817548 2.84% 61.65% +system.cpu.fetch.rateDist::6 5684311 2.77% 64.42% +system.cpu.fetch.rateDist::7 4746260 2.31% 66.73% +system.cpu.fetch.rateDist::8 68262754 33.27% 100.00% +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% +system.cpu.fetch.rateDist::min_value 0 +system.cpu.fetch.rateDist::max_value 8 +system.cpu.fetch.rateDist::total 205201489 +system.cpu.fetch.branchRate 0.197016 +system.cpu.fetch.rate 2.024385 +system.cpu.decode.IdleCycles 31935868 +system.cpu.decode.BlockedCycles 86571071 +system.cpu.decode.RunCycles 61623221 +system.cpu.decode.UnblockCycles 17732588 +system.cpu.decode.SquashCycles 7338741 +system.cpu.decode.DecodedInsts 585423984 +system.cpu.rename.SquashCycles 7338741 +system.cpu.rename.IdleCycles 41662198 +system.cpu.rename.BlockCycles 46227032 +system.cpu.rename.serializeStallCycles 28975 +system.cpu.rename.RunCycles 68218755 +system.cpu.rename.UnblockCycles 41725788 +system.cpu.rename.RenamedInsts 547333443 +system.cpu.rename.ROBFullEvents 1805 +system.cpu.rename.IQFullEvents 36710058 +system.cpu.rename.LQFullEvents 4936211 +system.cpu.rename.SQFullEvents 172839 +system.cpu.rename.RenamedOperands 624155655 +system.cpu.rename.RenameLookups 1473918429 +system.cpu.rename.int_rename_lookups 966803164 +system.cpu.rename.fp_rename_lookups 14714209 +system.cpu.rename.CommittedMaps 259429450 +system.cpu.rename.UndoneMaps 364726205 +system.cpu.rename.serializingInsts 2257 +system.cpu.rename.tempSerializingInsts 2274 +system.cpu.rename.skidInsts 89803547 +system.cpu.memDep0.insertedLoads 127813041 +system.cpu.memDep0.insertedStores 45569331 +system.cpu.memDep0.conflictingLoads 76700066 +system.cpu.memDep0.conflictingStores 25076087 +system.cpu.iq.iqInstsAdded 486700641 +system.cpu.iq.iqNonSpecInstsAdded 63617 +system.cpu.iq.iqInstsIssued 336591190 +system.cpu.iq.iqSquashedInstsIssued 1075815 +system.cpu.iq.iqSquashedInstsExamined 265400874 +system.cpu.iq.iqSquashedOperandsExamined 520101528 +system.cpu.iq.iqSquashedNonSpecRemoved 62372 +system.cpu.iq.issued_per_cycle::samples 205201489 +system.cpu.iq.issued_per_cycle::mean 1.640296 +system.cpu.iq.issued_per_cycle::stdev 1.801230 +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% +system.cpu.iq.issued_per_cycle::0 72558251 35.36% 35.36% +system.cpu.iq.issued_per_cycle::1 46563358 22.69% 58.05% +system.cpu.iq.issued_per_cycle::2 32833586 16.00% 74.05% +system.cpu.iq.issued_per_cycle::3 20829408 10.15% 84.20% +system.cpu.iq.issued_per_cycle::4 14957393 7.29% 91.49% +system.cpu.iq.issued_per_cycle::5 8327082 4.06% 95.55% +system.cpu.iq.issued_per_cycle::6 5158084 2.51% 98.06% +system.cpu.iq.issued_per_cycle::7 2335666 1.14% 99.20% +system.cpu.iq.issued_per_cycle::8 1638661 0.80% 100.00% +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::min_value 0 +system.cpu.iq.issued_per_cycle::max_value 8 +system.cpu.iq.issued_per_cycle::total 205201489 +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% +system.cpu.iq.fu_full::IntAlu 746083 18.99% 18.99% +system.cpu.iq.fu_full::IntMult 0 0.00% 18.99% +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.99% +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.99% +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.99% +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.99% +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.99% +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.99% +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.99% +system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.99% +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.99% +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.99% +system.cpu.iq.fu_full::MemRead 2709271 68.98% 87.97% +system.cpu.iq.fu_full::MemWrite 425877 10.84% 98.81% +system.cpu.iq.fu_full::FloatMemRead 43262 1.10% 99.91% +system.cpu.iq.fu_full::FloatMemWrite 3383 0.09% 100.00% +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::No_OpClass 1212158 0.36% 0.36% +system.cpu.iq.FU_type_0::IntAlu 215249595 63.95% 64.31% +system.cpu.iq.FU_type_0::IntMult 800532 0.24% 64.55% +system.cpu.iq.FU_type_0::IntDiv 7048368 2.09% 66.64% +system.cpu.iq.FU_type_0::FloatAdd 1789279 0.53% 67.17% +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.17% +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.17% +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.17% +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.17% +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.17% +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.17% +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.17% +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.17% +system.cpu.iq.FU_type_0::MemRead 82235884 24.43% 91.61% +system.cpu.iq.FU_type_0::MemWrite 26412299 7.85% 99.45% +system.cpu.iq.FU_type_0::FloatMemRead 1712250 0.51% 99.96% +system.cpu.iq.FU_type_0::FloatMemWrite 130825 0.04% 100.00% +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::total 336591190 +system.cpu.iq.rate 1.638390 +system.cpu.iq.fu_busy_cnt 3927876 +system.cpu.iq.fu_busy_rate 0.011670 +system.cpu.iq.int_inst_queue_reads 875282503 +system.cpu.iq.int_inst_queue_writes 737961959 +system.cpu.iq.int_inst_queue_wakeup_accesses 314539840 +system.cpu.iq.fp_inst_queue_reads 8105057 +system.cpu.iq.fp_inst_queue_writes 15024545 +system.cpu.iq.fp_inst_queue_wakeup_accesses 3526208 +system.cpu.iq.int_alu_accesses 335233753 +system.cpu.iq.fp_alu_accesses 4073155 +system.cpu.iew.lsq.thread0.forwLoads 18221651 +system.cpu.iew.lsq.thread0.invAddrLoads 0 +system.cpu.iew.lsq.thread0.squashedLoads 71163454 +system.cpu.iew.lsq.thread0.ignoredResponses 53032 +system.cpu.iew.lsq.thread0.memOrderViolation 858947 +system.cpu.iew.lsq.thread0.squashedStores 25053614 +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 +system.cpu.iew.lsq.thread0.blockedLoads 0 +system.cpu.iew.lsq.thread0.rescheduledLoads 50433 +system.cpu.iew.lsq.thread0.cacheBlocked 53 +system.cpu.iew.iewIdleCycles 0 +system.cpu.iew.iewSquashCycles 7338741 +system.cpu.iew.iewBlockCycles 35257404 +system.cpu.iew.iewUnblockCycles 584478 +system.cpu.iew.iewDispatchedInsts 486764258 +system.cpu.iew.iewDispSquashedInsts 1231534 +system.cpu.iew.iewDispLoadInsts 127813041 +system.cpu.iew.iewDispStoreInsts 45569331 +system.cpu.iew.iewDispNonSpecInsts 23100 +system.cpu.iew.iewIQFullEvents 542722 +system.cpu.iew.iewLSQFullEvents 38323 +system.cpu.iew.memOrderViolationEvents 858947 +system.cpu.iew.predictedTakenIncorrect 1297186 +system.cpu.iew.predictedNotTakenIncorrect 6715153 +system.cpu.iew.branchMispredicts 8012339 +system.cpu.iew.iewExecutedInsts 324846005 +system.cpu.iew.iewExecLoadInsts 80370798 +system.cpu.iew.iewExecSquashedInsts 11745185 +system.cpu.iew.exec_swp 0 +system.cpu.iew.exec_nop 0 +system.cpu.iew.exec_refs 105939683 +system.cpu.iew.exec_branches 18800586 +system.cpu.iew.exec_stores 25568885 +system.cpu.iew.exec_rate 1.581219 +system.cpu.iew.wb_sent 321037921 +system.cpu.iew.wb_count 318066048 +system.cpu.iew.wb_producers 255309802 +system.cpu.iew.wb_consumers 434053551 +system.cpu.iew.wb_rate 1.548217 +system.cpu.iew.wb_fanout 0.588199 +system.cpu.commit.commitSquashedInsts 265431246 +system.cpu.commit.commitNonSpecStalls 1245 +system.cpu.commit.branchMispredicts 6620627 +system.cpu.commit.committed_per_cycle::samples 163282867 +system.cpu.commit.committed_per_cycle::mean 1.355705 +system.cpu.commit.committed_per_cycle::stdev 1.936594 +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% +system.cpu.commit.committed_per_cycle::0 66681317 40.84% 40.84% +system.cpu.commit.committed_per_cycle::1 54877393 33.61% 74.45% +system.cpu.commit.committed_per_cycle::2 13218924 8.10% 82.54% +system.cpu.commit.committed_per_cycle::3 10716776 6.56% 89.11% +system.cpu.commit.committed_per_cycle::4 5408932 3.31% 92.42% +system.cpu.commit.committed_per_cycle::5 3143155 1.92% 94.34% +system.cpu.commit.committed_per_cycle::6 1097443 0.67% 95.02% +system.cpu.commit.committed_per_cycle::7 1149762 0.70% 95.72% +system.cpu.commit.committed_per_cycle::8 6989165 4.28% 100.00% +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% +system.cpu.commit.committed_per_cycle::min_value 0 +system.cpu.commit.committed_per_cycle::max_value 8 +system.cpu.commit.committed_per_cycle::total 163282867 +system.cpu.commit.committedInsts 132071192 +system.cpu.commit.committedOps 221363384 +system.cpu.commit.swp_count 0 +system.cpu.commit.refs 77165304 +system.cpu.commit.loads 56649587 +system.cpu.commit.membars 0 +system.cpu.commit.branches 12326938 +system.cpu.commit.fp_insts 2162459 +system.cpu.commit.int_insts 219019985 +system.cpu.commit.function_calls 797818 +system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% +system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% +system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% +system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% +system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.14% +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.14% +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% +system.cpu.commit.op_class_0::MemRead 55945136 25.27% 90.41% +system.cpu.commit.op_class_0::MemWrite 20410230 9.22% 99.63% +system.cpu.commit.op_class_0::FloatMemRead 704451 0.32% 99.95% +system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% +system.cpu.commit.op_class_0::total 221363384 +system.cpu.commit.bw_lim_events 6989165 +system.cpu.rob.rob_reads 643088332 +system.cpu.rob.rob_writes 1015902506 +system.cpu.timesIdled 2802 +system.cpu.idleCycles 238689 +system.cpu.committedInsts 132071192 +system.cpu.committedOps 221363384 +system.cpu.cpi 1.555526 +system.cpu.cpi_total 1.555526 +system.cpu.ipc 0.642869 +system.cpu.ipc_total 0.642869 +system.cpu.int_regfile_reads 522853545 +system.cpu.int_regfile_writes 287693923 +system.cpu.fp_regfile_reads 4488277 +system.cpu.fp_regfile_writes 3288210 +system.cpu.cc_regfile_reads 106934925 +system.cpu.cc_regfile_writes 65654580 +system.cpu.misc_regfile_reads 175824659 +system.cpu.misc_regfile_writes 1689 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.cpu.dcache.tags.replacements 62 +system.cpu.dcache.tags.tagsinuse 1518.622789 +system.cpu.dcache.tags.total_refs 82373091 +system.cpu.dcache.tags.sampled_refs 2122 +system.cpu.dcache.tags.avg_refs 38818.610273 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 1518.622789 +system.cpu.dcache.tags.occ_percent::cpu.data 0.370758 +system.cpu.dcache.tags.occ_percent::total 0.370758 +system.cpu.dcache.tags.occ_task_id_blocks::1024 2060 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 94 +system.cpu.dcache.tags.age_task_id_blocks_1024::3 426 +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1495 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.502930 +system.cpu.dcache.tags.tag_accesses 164753648 +system.cpu.dcache.tags.data_accesses 164753648 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.cpu.dcache.ReadReq_hits::cpu.data 61858770 +system.cpu.dcache.ReadReq_hits::total 61858770 +system.cpu.dcache.WriteReq_hits::cpu.data 20513717 +system.cpu.dcache.WriteReq_hits::total 20513717 +system.cpu.dcache.demand_hits::cpu.data 82372487 +system.cpu.dcache.demand_hits::total 82372487 +system.cpu.dcache.overall_hits::cpu.data 82372487 +system.cpu.dcache.overall_hits::total 82372487 +system.cpu.dcache.ReadReq_misses::cpu.data 1262 +system.cpu.dcache.ReadReq_misses::total 1262 +system.cpu.dcache.WriteReq_misses::cpu.data 2014 +system.cpu.dcache.WriteReq_misses::total 2014 +system.cpu.dcache.demand_misses::cpu.data 3276 +system.cpu.dcache.demand_misses::total 3276 +system.cpu.dcache.overall_misses::cpu.data 3276 +system.cpu.dcache.overall_misses::total 3276 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 127973000 +system.cpu.dcache.ReadReq_miss_latency::total 127973000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 138062500 +system.cpu.dcache.WriteReq_miss_latency::total 138062500 +system.cpu.dcache.demand_miss_latency::cpu.data 266035500 +system.cpu.dcache.demand_miss_latency::total 266035500 +system.cpu.dcache.overall_miss_latency::cpu.data 266035500 +system.cpu.dcache.overall_miss_latency::total 266035500 +system.cpu.dcache.ReadReq_accesses::cpu.data 61860032 +system.cpu.dcache.ReadReq_accesses::total 61860032 +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 +system.cpu.dcache.WriteReq_accesses::total 20515731 +system.cpu.dcache.demand_accesses::cpu.data 82375763 +system.cpu.dcache.demand_accesses::total 82375763 +system.cpu.dcache.overall_accesses::cpu.data 82375763 +system.cpu.dcache.overall_accesses::total 82375763 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000098 +system.cpu.dcache.WriteReq_miss_rate::total 0.000098 +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 +system.cpu.dcache.demand_miss_rate::total 0.000040 +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 +system.cpu.dcache.overall_miss_rate::total 0.000040 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 101404.912837 +system.cpu.dcache.ReadReq_avg_miss_latency::total 101404.912837 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68551.390268 +system.cpu.dcache.WriteReq_avg_miss_latency::total 68551.390268 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81207.417582 +system.cpu.dcache.demand_avg_miss_latency::total 81207.417582 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81207.417582 +system.cpu.dcache.overall_avg_miss_latency::total 81207.417582 +system.cpu.dcache.blocked_cycles::no_mshrs 635 +system.cpu.dcache.blocked_cycles::no_targets 58 +system.cpu.dcache.blocked::no_mshrs 5 +system.cpu.dcache.blocked::no_targets 1 +system.cpu.dcache.avg_blocked_cycles::no_mshrs 127 +system.cpu.dcache.avg_blocked_cycles::no_targets 58 +system.cpu.dcache.writebacks::writebacks 22 +system.cpu.dcache.writebacks::total 22 +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 653 +system.cpu.dcache.ReadReq_mshr_hits::total 653 +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 +system.cpu.dcache.WriteReq_mshr_hits::total 11 +system.cpu.dcache.demand_mshr_hits::cpu.data 664 +system.cpu.dcache.demand_mshr_hits::total 664 +system.cpu.dcache.overall_mshr_hits::cpu.data 664 +system.cpu.dcache.overall_mshr_hits::total 664 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 609 +system.cpu.dcache.ReadReq_mshr_misses::total 609 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003 +system.cpu.dcache.WriteReq_mshr_misses::total 2003 +system.cpu.dcache.demand_mshr_misses::cpu.data 2612 +system.cpu.dcache.demand_mshr_misses::total 2612 +system.cpu.dcache.overall_mshr_misses::cpu.data 2612 +system.cpu.dcache.overall_mshr_misses::total 2612 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78734500 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 78734500 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135473000 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 135473000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214207500 +system.cpu.dcache.demand_mshr_miss_latency::total 214207500 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214207500 +system.cpu.dcache.overall_mshr_miss_latency::total 214207500 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 129284.893268 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 129284.893268 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67635.047429 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67635.047429 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82008.996937 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82008.996937 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82008.996937 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82008.996937 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.cpu.icache.tags.replacements 6438 +system.cpu.icache.tags.tagsinuse 1691.819793 +system.cpu.icache.tags.total_refs 40880550 +system.cpu.icache.tags.sampled_refs 8435 +system.cpu.icache.tags.avg_refs 4846.538234 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 1691.819793 +system.cpu.icache.tags.occ_percent::cpu.inst 0.826084 +system.cpu.icache.tags.occ_percent::total 0.826084 +system.cpu.icache.tags.occ_task_id_blocks::1024 1997 +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 +system.cpu.icache.tags.age_task_id_blocks_1024::1 165 +system.cpu.icache.tags.age_task_id_blocks_1024::2 849 +system.cpu.icache.tags.age_task_id_blocks_1024::3 153 +system.cpu.icache.tags.age_task_id_blocks_1024::4 731 +system.cpu.icache.tags.occ_task_id_percent::1024 0.975098 +system.cpu.icache.tags.tag_accesses 81796128 +system.cpu.icache.tags.data_accesses 81796128 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.cpu.icache.ReadReq_hits::cpu.inst 40880551 +system.cpu.icache.ReadReq_hits::total 40880551 +system.cpu.icache.demand_hits::cpu.inst 40880551 +system.cpu.icache.demand_hits::total 40880551 +system.cpu.icache.overall_hits::cpu.inst 40880551 +system.cpu.icache.overall_hits::total 40880551 +system.cpu.icache.ReadReq_misses::cpu.inst 13051 +system.cpu.icache.ReadReq_misses::total 13051 +system.cpu.icache.demand_misses::cpu.inst 13051 +system.cpu.icache.demand_misses::total 13051 +system.cpu.icache.overall_misses::cpu.inst 13051 +system.cpu.icache.overall_misses::total 13051 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 645910000 +system.cpu.icache.ReadReq_miss_latency::total 645910000 +system.cpu.icache.demand_miss_latency::cpu.inst 645910000 +system.cpu.icache.demand_miss_latency::total 645910000 +system.cpu.icache.overall_miss_latency::cpu.inst 645910000 +system.cpu.icache.overall_miss_latency::total 645910000 +system.cpu.icache.ReadReq_accesses::cpu.inst 40893602 +system.cpu.icache.ReadReq_accesses::total 40893602 +system.cpu.icache.demand_accesses::cpu.inst 40893602 +system.cpu.icache.demand_accesses::total 40893602 +system.cpu.icache.overall_accesses::cpu.inst 40893602 +system.cpu.icache.overall_accesses::total 40893602 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000319 +system.cpu.icache.ReadReq_miss_rate::total 0.000319 +system.cpu.icache.demand_miss_rate::cpu.inst 0.000319 +system.cpu.icache.demand_miss_rate::total 0.000319 +system.cpu.icache.overall_miss_rate::cpu.inst 0.000319 +system.cpu.icache.overall_miss_rate::total 0.000319 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49491.226726 +system.cpu.icache.ReadReq_avg_miss_latency::total 49491.226726 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49491.226726 +system.cpu.icache.demand_avg_miss_latency::total 49491.226726 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49491.226726 +system.cpu.icache.overall_avg_miss_latency::total 49491.226726 +system.cpu.icache.blocked_cycles::no_mshrs 2923 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 38 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs 76.921053 +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 6438 +system.cpu.icache.writebacks::total 6438 +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4126 +system.cpu.icache.ReadReq_mshr_hits::total 4126 +system.cpu.icache.demand_mshr_hits::cpu.inst 4126 +system.cpu.icache.demand_mshr_hits::total 4126 +system.cpu.icache.overall_mshr_hits::cpu.inst 4126 +system.cpu.icache.overall_mshr_hits::total 4126 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8925 +system.cpu.icache.ReadReq_mshr_misses::total 8925 +system.cpu.icache.demand_mshr_misses::cpu.inst 8925 +system.cpu.icache.demand_mshr_misses::total 8925 +system.cpu.icache.overall_mshr_misses::cpu.inst 8925 +system.cpu.icache.overall_mshr_misses::total 8925 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 456195500 +system.cpu.icache.ReadReq_mshr_miss_latency::total 456195500 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 456195500 +system.cpu.icache.demand_mshr_miss_latency::total 456195500 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 456195500 +system.cpu.icache.overall_mshr_miss_latency::total 456195500 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000218 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000218 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000218 +system.cpu.icache.demand_mshr_miss_rate::total 0.000218 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 +system.cpu.icache.overall_mshr_miss_rate::total 0.000218 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51114.341737 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51114.341737 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51114.341737 +system.cpu.icache.demand_avg_mshr_miss_latency::total 51114.341737 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51114.341737 +system.cpu.icache.overall_avg_mshr_miss_latency::total 51114.341737 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.cpu.l2cache.tags.replacements 0 +system.cpu.l2cache.tags.tagsinuse 3919.914171 +system.cpu.l2cache.tags.total_refs 11787 +system.cpu.l2cache.tags.sampled_refs 5718 +system.cpu.l2cache.tags.avg_refs 2.061385 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2430.246024 +system.cpu.l2cache.tags.occ_blocks::cpu.data 1489.668147 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074165 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.045461 +system.cpu.l2cache.tags.occ_percent::total 0.119626 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5718 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1011 +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 535 +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3956 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.174500 +system.cpu.l2cache.tags.tag_accesses 145758 +system.cpu.l2cache.tags.data_accesses 145758 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.cpu.l2cache.WritebackDirty_hits::writebacks 22 +system.cpu.l2cache.WritebackDirty_hits::total 22 +system.cpu.l2cache.WritebackClean_hits::writebacks 6398 +system.cpu.l2cache.WritebackClean_hits::total 6398 +system.cpu.l2cache.UpgradeReq_hits::cpu.data 490 +system.cpu.l2cache.UpgradeReq_hits::total 490 +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 +system.cpu.l2cache.ReadExReq_hits::total 8 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4761 +system.cpu.l2cache.ReadCleanReq_hits::total 4761 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 69 +system.cpu.l2cache.ReadSharedReq_hits::total 69 +system.cpu.l2cache.demand_hits::cpu.inst 4761 +system.cpu.l2cache.demand_hits::cpu.data 77 +system.cpu.l2cache.demand_hits::total 4838 +system.cpu.l2cache.overall_hits::cpu.inst 4761 +system.cpu.l2cache.overall_hits::cpu.data 77 +system.cpu.l2cache.overall_hits::total 4838 +system.cpu.l2cache.ReadExReq_misses::cpu.data 1507 +system.cpu.l2cache.ReadExReq_misses::total 1507 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3673 +system.cpu.l2cache.ReadCleanReq_misses::total 3673 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 538 +system.cpu.l2cache.ReadSharedReq_misses::total 538 +system.cpu.l2cache.demand_misses::cpu.inst 3673 +system.cpu.l2cache.demand_misses::cpu.data 2045 +system.cpu.l2cache.demand_misses::total 5718 +system.cpu.l2cache.overall_misses::cpu.inst 3673 +system.cpu.l2cache.overall_misses::cpu.data 2045 +system.cpu.l2cache.overall_misses::total 5718 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 126901500 +system.cpu.l2cache.ReadExReq_miss_latency::total 126901500 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 391879000 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 391879000 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 76877000 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 76877000 +system.cpu.l2cache.demand_miss_latency::cpu.inst 391879000 +system.cpu.l2cache.demand_miss_latency::cpu.data 203778500 +system.cpu.l2cache.demand_miss_latency::total 595657500 +system.cpu.l2cache.overall_miss_latency::cpu.inst 391879000 +system.cpu.l2cache.overall_miss_latency::cpu.data 203778500 +system.cpu.l2cache.overall_miss_latency::total 595657500 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 22 +system.cpu.l2cache.WritebackDirty_accesses::total 22 +system.cpu.l2cache.WritebackClean_accesses::writebacks 6398 +system.cpu.l2cache.WritebackClean_accesses::total 6398 +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 490 +system.cpu.l2cache.UpgradeReq_accesses::total 490 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1515 +system.cpu.l2cache.ReadExReq_accesses::total 1515 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8434 +system.cpu.l2cache.ReadCleanReq_accesses::total 8434 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 607 +system.cpu.l2cache.ReadSharedReq_accesses::total 607 +system.cpu.l2cache.demand_accesses::cpu.inst 8434 +system.cpu.l2cache.demand_accesses::cpu.data 2122 +system.cpu.l2cache.demand_accesses::total 10556 +system.cpu.l2cache.overall_accesses::cpu.inst 8434 +system.cpu.l2cache.overall_accesses::cpu.data 2122 +system.cpu.l2cache.overall_accesses::total 10556 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994719 +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994719 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.435499 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.435499 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886326 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886326 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.435499 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963713 +system.cpu.l2cache.demand_miss_rate::total 0.541682 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.435499 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963713 +system.cpu.l2cache.overall_miss_rate::total 0.541682 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84208.029197 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84208.029197 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106691.805064 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106691.805064 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 142894.052045 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 142894.052045 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106691.805064 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99647.188264 +system.cpu.l2cache.demand_avg_miss_latency::total 104172.350472 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106691.805064 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99647.188264 +system.cpu.l2cache.overall_avg_miss_latency::total 104172.350472 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 +system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3673 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3673 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 538 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 538 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3673 +system.cpu.l2cache.demand_mshr_misses::cpu.data 2045 +system.cpu.l2cache.demand_mshr_misses::total 5718 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3673 +system.cpu.l2cache.overall_mshr_misses::cpu.data 2045 +system.cpu.l2cache.overall_mshr_misses::total 5718 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111831500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111831500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 355149000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 355149000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 71497000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 71497000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 355149000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183328500 +system.cpu.l2cache.demand_mshr_miss_latency::total 538477500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 355149000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183328500 +system.cpu.l2cache.overall_mshr_miss_latency::total 538477500 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994719 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994719 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.435499 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.435499 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.886326 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.886326 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.435499 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963713 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.541682 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.435499 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963713 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.541682 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74208.029197 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74208.029197 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96691.805064 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96691.805064 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 132894.052045 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 132894.052045 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96691.805064 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89647.188264 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94172.350472 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96691.805064 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89647.188264 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94172.350472 +system.cpu.toL2Bus.snoop_filter.tot_requests 18037 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 6582 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 979 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.cpu.toL2Bus.trans_dist::ReadResp 9531 +system.cpu.toL2Bus.trans_dist::WritebackDirty 22 +system.cpu.toL2Bus.trans_dist::WritebackClean 6438 +system.cpu.toL2Bus.trans_dist::CleanEvict 40 +system.cpu.toL2Bus.trans_dist::UpgradeReq 490 +system.cpu.toL2Bus.trans_dist::UpgradeResp 490 +system.cpu.toL2Bus.trans_dist::ReadExReq 1515 +system.cpu.toL2Bus.trans_dist::ReadExResp 1515 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 8925 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 607 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23796 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5286 +system.cpu.toL2Bus.pkt_count::total 29082 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 951744 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137216 +system.cpu.toL2Bus.pkt_size::total 1088960 +system.cpu.toL2Bus.snoops 491 +system.cpu.toL2Bus.snoopTraffic 31424 +system.cpu.toL2Bus.snoop_fanout::samples 11537 +system.cpu.toL2Bus.snoop_fanout::mean 0.091878 +system.cpu.toL2Bus.snoop_fanout::stdev 0.288867 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 10477 90.81% 90.81% +system.cpu.toL2Bus.snoop_fanout::1 1060 9.19% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 11537 +system.cpu.toL2Bus.reqLayer0.occupancy 15478500 +system.cpu.toL2Bus.reqLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 13386000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 3428499 +system.cpu.toL2Bus.respLayer1.utilization 0.0 +system.membus.snoop_filter.tot_requests 5718 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 102720088500 +system.membus.trans_dist::ReadResp 4211 +system.membus.trans_dist::ReadExReq 1507 +system.membus.trans_dist::ReadExResp 1507 +system.membus.trans_dist::ReadSharedReq 4211 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11436 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11436 +system.membus.pkt_count::total 11436 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 365952 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 365952 +system.membus.pkt_size::total 365952 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 5718 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 5718 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 5718 +system.membus.reqLayer0.occupancy 6956000 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 30307000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- |