diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/x86/linux/o3-timing')
3 files changed, 280 insertions, 204 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 9f72e3b54..82a282d96 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -442,20 +435,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -494,20 +480,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -531,12 +510,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 0b6a80ec2..99b3e7f21 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 9 2012 12:45:55 -gem5 started Feb 9 2012 12:46:40 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:02:46 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 2a68affc2..0aeabdea4 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.096266 # Nu sim_ticks 96266258000 # Number of ticks simulated final_tick 96266258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60515 # Simulator instruction rate (inst/s) -host_tick_rate 26316743 # Simulator tick rate (ticks/s) -host_mem_usage 262352 # Number of bytes of host memory used -host_seconds 3657.99 # Real time elapsed on the host -sim_insts 221363017 # Number of instructions simulated +host_inst_rate 89516 # Simulator instruction rate (inst/s) +host_op_rate 150037 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65247901 # Simulator tick rate (ticks/s) +host_mem_usage 229524 # Number of bytes of host memory used +host_seconds 1475.39 # Real time elapsed on the host +sim_insts 132071227 # Number of instructions simulated +sim_ops 221363017 # Number of ops (including micro ops) simulated system.physmem.bytes_read 339712 # Number of bytes read from this memory system.physmem.bytes_inst_read 214912 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -235,7 +237,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.457634 # insts written-back per cycle system.cpu.iew.wb_fanout 0.601730 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions +system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions system.cpu.commit.commitSquashedInsts 174222633 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 2892920 # The number of times a branch was mispredicted @@ -256,7 +259,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 168869292 # Number of insts commited each cycle -system.cpu.commit.count 221363017 # Number of instructions committed +system.cpu.commit.committedInsts 132071227 # Number of instructions committed +system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed system.cpu.commit.loads 56649590 # Number of loads committed @@ -271,12 +275,13 @@ system.cpu.rob.rob_reads 560089335 # Th system.cpu.rob.rob_writes 814800236 # The number of ROB writes system.cpu.timesIdled 1747 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 80351 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 221363017 # Number of Instructions Simulated -system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.869759 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.869759 # CPI: Total CPI of All Threads -system.cpu.ipc 1.149744 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.149744 # IPC: Total IPC of All Threads +system.cpu.committedInsts 132071227 # Number of Instructions Simulated +system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated +system.cpu.cpi 1.457793 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.457793 # CPI: Total CPI of All Threads +system.cpu.ipc 0.685968 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.685968 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 530367480 # number of integer regfile reads system.cpu.int_regfile_writes 288604591 # number of integer regfile writes system.cpu.fp_regfile_reads 3608788 # number of floating regfile reads @@ -289,26 +294,39 @@ system.cpu.icache.total_refs 28751182 # To system.cpu.icache.sampled_refs 6167 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4662.101832 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1597.649860 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.780102 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28751182 # number of ReadReq hits -system.cpu.icache.demand_hits 28751182 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28751182 # number of overall hits -system.cpu.icache.ReadReq_misses 7479 # number of ReadReq misses -system.cpu.icache.demand_misses 7479 # number of demand (read+write) misses -system.cpu.icache.overall_misses 7479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 173725000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 173725000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28758661 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28758661 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000260 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000260 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000260 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23228.372777 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23228.372777 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23228.372777 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1597.649860 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.780102 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.780102 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 28751182 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 28751182 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 28751182 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 28751182 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 28751182 # number of overall hits +system.cpu.icache.overall_hits::total 28751182 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 7479 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 7479 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 7479 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 7479 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 7479 # number of overall misses +system.cpu.icache.overall_misses::total 7479 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 173725000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 173725000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 173725000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 173725000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 173725000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 173725000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 28758661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 28758661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 28758661 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 28758661 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 28758661 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 28758661 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000260 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000260 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000260 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23228.372777 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -317,27 +335,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1119 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1119 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 6360 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 6360 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 125233500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000221 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19690.801887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1119 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1119 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1119 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1119 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1119 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1119 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6360 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6360 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6360 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6360 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6360 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6360 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 125233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 125233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125233500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 125233500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19690.801887 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 56 # number of replacements system.cpu.dcache.tagsinuse 1415.486536 # Cycle average of tags in use @@ -345,32 +366,49 @@ system.cpu.dcache.total_refs 72938173 # To system.cpu.dcache.sampled_refs 1987 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 36707.686462 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1415.486536 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 52423955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20513973 # number of WriteReq hits -system.cpu.dcache.demand_hits 72937928 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 72937928 # number of overall hits -system.cpu.dcache.ReadReq_misses 771 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1757 # number of WriteReq misses -system.cpu.dcache.demand_misses 2528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 24605500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 66582500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 91188000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 52424726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 72940456 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 72940456 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000086 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000035 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31913.748379 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37895.560615 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 36071.202532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 36071.202532 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1415.486536 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345578 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.345578 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 52423955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 52423955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513973 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513973 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 72937928 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 72937928 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 72937928 # number of overall hits +system.cpu.dcache.overall_hits::total 72937928 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 771 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 771 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1757 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1757 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2528 # number of overall misses +system.cpu.dcache.overall_misses::total 2528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24605500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24605500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66582500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66582500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91188000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91188000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91188000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91188000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 72940456 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 72940456 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 72940456 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 72940456 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31913.748379 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37895.560615 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,32 +417,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 344 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 346 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 346 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1755 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14039500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61244500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 75284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 75284000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000086 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000030 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000030 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32879.391101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34897.150997 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34502.291476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34502.291476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 13 # number of writebacks +system.cpu.dcache.writebacks::total 13 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 344 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 346 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 346 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 346 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 346 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 427 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1755 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1755 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2182 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2182 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 75284000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 75284000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 75284000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 75284000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000086 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32879.391101 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34897.150997 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2496.824684 # Cycle average of tags in use @@ -412,39 +458,80 @@ system.cpu.l2cache.total_refs 2842 # To system.cpu.l2cache.sampled_refs 3755 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.756858 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2494.880189 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.944495 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.076138 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000059 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2840 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 13 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2848 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2848 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3753 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 193 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1555 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5308 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 128533500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53066500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 181600000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 181600000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 6593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 193 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8156 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8156 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.569240 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.994882 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.650809 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.650809 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34248.201439 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34126.366559 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34212.509420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34212.509420 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 1.944495 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2209.976363 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 284.903826 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000059 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.067443 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.008695 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.076197 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2809 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2840 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2809 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2848 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2809 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 39 # 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number of overall misses +system.cpu.l2cache.overall_misses::total 5308 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 115037500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13496000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 128533500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53066500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 53066500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 115037500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 66562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 181600000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 115037500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 66562500 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1989 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8156 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6167 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1989 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8156 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.544511 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.927230 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.544511 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980392 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.544511 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980392 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34257.742704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34167.088608 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34126.366559 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,34 +540,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3753 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 193 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5308 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5308 # 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mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.650809 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.784972 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31017.684887 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.462698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.462698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3358 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 395 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12238000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116413500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5983000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5983000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48232500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48232500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104175500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60470500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 164646000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104175500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60470500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 164646000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.079214 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30982.278481 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31017.684887 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |