diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 004f7b9ea..1372cb624 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.250954 # Number of seconds simulated -sim_ticks 250953956000 # Number of ticks simulated -final_tick 250953956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 250953957000 # Number of ticks simulated +final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 580885 # Simulator instruction rate (inst/s) -host_op_rate 973614 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1103763503 # Simulator tick rate (ticks/s) -host_mem_usage 316652 # Number of bytes of host memory used -host_seconds 227.36 # Real time elapsed on the host +host_inst_rate 308460 # Simulator instruction rate (inst/s) +host_op_rate 517006 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 586117013 # Simulator tick rate (ticks/s) +host_mem_usage 316420 # Number of bytes of host memory used +host_seconds 428.16 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated -sim_ops 221362962 # Number of ops (including micro ops) simulated +sim_ops 221362963 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory system.physmem.bytes_read::total 303040 # Number of bytes read from this memory @@ -28,35 +28,35 @@ system.physmem.bw_total::cpu.inst 724276 # To system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501907912 # number of cpu cycles simulated +system.cpu.numCycles 501907914 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed -system.cpu.committedOps 221362962 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 220339552 # Number of integer alu accesses +system.cpu.committedOps 221362963 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 220339552 # number of integer instructions +system.cpu.num_int_insts 220339554 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 616958553 # number of times the integer registers were read -system.cpu.num_int_register_writes 257597201 # number of times the integer registers were written +system.cpu.num_int_register_reads 616958558 # number of times the integer registers were read +system.cpu.num_int_register_writes 257597203 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_mem_refs 77165303 # number of memory refs -system.cpu.num_load_insts 56649586 # Number of load instructions +system.cpu.num_mem_refs 77165304 # number of memory refs +system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 501907912 # Number of busy cycles +system.cpu.num_busy_cycles 501907914 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.tagsinuse 1455.296648 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1455.296642 # Cycle average of tags in use system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1455.296648 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2058.178694 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2058.178686 # Cycle average of tags in use system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1829.978587 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.178363 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy @@ -265,22 +265,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use -system.cpu.dcache.total_refs 77195830 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1363.457571 # Cycle average of tags in use +system.cpu.dcache.total_refs 77195831 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40522.745932 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.457576 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77195830 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77195830 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77195830 # number of overall hits -system.cpu.dcache.overall_hits::total 77195830 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits +system.cpu.dcache.overall_hits::total 77195831 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses @@ -297,14 +297,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 104356500 system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77197735 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77197735 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77197735 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77197735 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses |