diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/x86/linux/simple-timing')
4 files changed, 73 insertions, 10 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 00a43a175..b3c95dee1 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -76,6 +82,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -84,6 +91,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -98,18 +106,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -120,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -128,6 +141,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -142,12 +156,15 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -158,16 +175,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -178,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -186,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -200,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -224,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +eventq_index=0 +executable=/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -238,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -255,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -264,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index b436e7f9e..cc37865c7 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:51:48 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 22:12:53 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 9cfd1bb27..2eac3bbbe 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957000 # Number of ticks simulated final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 789102 # Simulator instruction rate (inst/s) -host_op_rate 1322606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1499404446 # Simulator tick rate (ticks/s) -host_mem_usage 274284 # Number of bytes of host memory used -host_seconds 167.37 # Real time elapsed on the host +host_inst_rate 770398 # Simulator instruction rate (inst/s) +host_op_rate 1291257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1463865173 # Simulator tick rate (ticks/s) +host_mem_usage 276604 # Number of bytes of host memory used +host_seconds 171.43 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory system.physmem.bytes_read::total 303040 # Number of bytes read from this memory @@ -44,6 +46,8 @@ system.membus.reqLayer0.occupancy 4753500 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 501907914 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,6 +82,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 346993430 # Number of tag accesses +system.cpu.icache.tags.data_accesses 346993430 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits @@ -160,6 +173,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 57590 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 57590 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits @@ -292,6 +314,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits |