diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref/x86/linux/simple-timing')
4 files changed, 65 insertions, 63 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 15a571204..c487d8f46 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -61,21 +61,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -90,7 +91,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -99,21 +100,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -122,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -139,30 +141,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -172,10 +175,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory -clock=1 +bandwidth=73.000000 +clock=1000 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr index ac4ad20a5..f5691fd64 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index 623b8af30..ea7ae2fe0 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:57:57 +gem5 compiled Dec 30 2012 00:35:18 +gem5 started Dec 30 2012 01:16:52 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav @@ -26,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 250980994000 because target called exit() +122 123 124 Exiting @ tick 250953956000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 82f566301..37f9d1943 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.250954 # Number of seconds simulated -sim_ticks 250953955000 # Number of ticks simulated -final_tick 250953955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 250953956000 # Number of ticks simulated +final_tick 250953956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 366685 # Simulator instruction rate (inst/s) -host_op_rate 614596 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 696753053 # Simulator tick rate (ticks/s) -host_mem_usage 236244 # Number of bytes of host memory used -host_seconds 360.18 # Real time elapsed on the host +host_inst_rate 472281 # Simulator instruction rate (inst/s) +host_op_rate 791585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 897401473 # Simulator tick rate (ticks/s) +host_mem_usage 283668 # Number of bytes of host memory used +host_seconds 279.65 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated -sim_ops 221362961 # Number of ops (including micro ops) simulated +sim_ops 221362962 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory system.physmem.bytes_read::total 303040 # Number of bytes read from this memory @@ -28,35 +28,35 @@ system.physmem.bw_total::cpu.inst 724276 # To system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501907910 # number of cpu cycles simulated +system.cpu.numCycles 501907912 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed -system.cpu.committedOps 221362961 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 220339550 # Number of integer alu accesses +system.cpu.committedOps 221362962 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 220339552 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 220339550 # number of integer instructions +system.cpu.num_int_insts 220339552 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 616958548 # number of times the integer registers were read -system.cpu.num_int_register_writes 257597200 # number of times the integer registers were written +system.cpu.num_int_register_reads 616958553 # number of times the integer registers were read +system.cpu.num_int_register_writes 257597201 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_mem_refs 77165302 # number of memory refs +system.cpu.num_mem_refs 77165303 # number of memory refs system.cpu.num_load_insts 56649586 # Number of load instructions -system.cpu.num_store_insts 20515716 # Number of store instructions +system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 501907910 # Number of busy cycles +system.cpu.num_busy_cycles 501907912 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.tagsinuse 1455.296654 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1455.296648 # Cycle average of tags in use system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1455.296654 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1455.296648 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits @@ -129,22 +129,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.tagsinuse 1363.457581 # Cycle average of tags in use -system.cpu.dcache.total_refs 77195829 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use +system.cpu.dcache.total_refs 77195830 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40522.744882 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.457581 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 1363.457576 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514152 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77195829 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77195829 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77195829 # number of overall hits -system.cpu.dcache.overall_hits::total 77195829 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77195830 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195830 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195830 # number of overall hits +system.cpu.dcache.overall_hits::total 77195830 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses @@ -163,12 +163,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data 104356500 system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77197734 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77197734 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77197734 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77197734 # number of overall (read+write) accesses +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 77197735 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197735 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197735 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197735 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses @@ -229,14 +229,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2058.178702 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2058.178694 # Cycle average of tags in use system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1829.978594 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.178364 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1829.978587 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 228.178363 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy |