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-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini37
-rwxr-xr-xtests/long/se/70.twolf/ref/x86/linux/o3-timing/simout10
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt27
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini10
-rwxr-xr-xtests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout4
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini27
-rwxr-xr-xtests/long/se/70.twolf/ref/x86/linux/simple-timing/simout4
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt210
9 files changed, 173 insertions, 166 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 0c6ed2a4b..c97d77597 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -514,7 +519,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index e62279342..617f03c25 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,14 @@
+Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 23:04:52
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 19:08:30
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 8854dc0e6..daaac056b 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.082648 # Nu
sim_ticks 82648140000 # Number of ticks simulated
final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 100436 # Simulator instruction rate (inst/s)
-host_op_rate 168340 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 62851400 # Simulator tick rate (ticks/s)
-host_mem_usage 270508 # Number of bytes of host memory used
-host_seconds 1314.98 # Real time elapsed on the host
+host_inst_rate 59257 # Simulator instruction rate (inst/s)
+host_op_rate 99320 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37082179 # Simulator tick rate (ticks/s)
+host_mem_usage 321776 # Number of bytes of host memory used
+host_seconds 2228.78 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221362961 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory
@@ -185,18 +185,19 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 15454021.88 # Average gap between requests
+system.cpu.branchPred.lookups 19953215 # Number of BP lookups
+system.cpu.branchPred.condPredicted 19953215 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2011335 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 13840594 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13098591 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 94.638937 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 165296281 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 19953215 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 19953215 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2011335 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 13840594 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 13098591 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed
system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index b8455592d..222b14efd 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -83,6 +86,9 @@ int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
index 82f0dcff5..7bcffd6bf 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atom
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:50:19
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:05:52
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index c5a1b588f..4c14b976b 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu
sim_ticks 131393067500 # Number of ticks simulated
final_tick 131393067500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 889897 # Simulator instruction rate (inst/s)
-host_op_rate 1491546 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 885328041 # Simulator tick rate (ticks/s)
-host_mem_usage 275216 # Number of bytes of host memory used
-host_seconds 148.41 # Real time elapsed on the host
+host_inst_rate 897941 # Simulator instruction rate (inst/s)
+host_op_rate 1505028 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 893330062 # Simulator tick rate (ticks/s)
+host_mem_usage 308196 # Number of bytes of host memory used
+host_seconds 147.08 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362962 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index c487d8f46..368cbf930 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -63,21 +66,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -102,21 +100,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -133,6 +126,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
@@ -152,21 +148,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
index ea7ae2fe0..ff40493ec 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 01:16:52
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:30:54
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 37f9d1943..004f7b9ea 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu
sim_ticks 250953956000 # Number of ticks simulated
final_tick 250953956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 472281 # Simulator instruction rate (inst/s)
-host_op_rate 791585 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 897401473 # Simulator tick rate (ticks/s)
-host_mem_usage 283668 # Number of bytes of host memory used
-host_seconds 279.65 # Real time elapsed on the host
+host_inst_rate 580885 # Simulator instruction rate (inst/s)
+host_op_rate 973614 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1103763503 # Simulator tick rate (ticks/s)
+host_mem_usage 316652 # Number of bytes of host memory used
+host_seconds 227.36 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362962 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
@@ -128,106 +128,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 41 # number of replacements
-system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use
-system.cpu.dcache.total_refs 77195830 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1363.457576 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 77195830 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 77195830 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 77195830 # number of overall hits
-system.cpu.dcache.overall_hits::total 77195830 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
-system.cpu.dcache.overall_misses::total 1905 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 77197735 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 77197735 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 77197735 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 77197735 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
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-system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.dcache.writebacks::total 7 # number of writebacks
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-system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2058.178694 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks.
@@ -364,5 +264,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 41 # number of replacements
+system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use
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+system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------