diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref')
8 files changed, 2138 insertions, 2138 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index c057cfc04..aad21c6d0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.042012 # Number of seconds simulated -sim_ticks 42012413000 # Number of ticks simulated -final_tick 42012413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042001 # Number of seconds simulated +sim_ticks 42001440000 # Number of ticks simulated +final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107145 # Simulator instruction rate (inst/s) -host_op_rate 107145 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48980163 # Simulator tick rate (ticks/s) -host_mem_usage 222716 # Number of bytes of host memory used -host_seconds 857.74 # Real time elapsed on the host +host_inst_rate 75192 # Simulator instruction rate (inst/s) +host_op_rate 75192 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34364250 # Simulator tick rate (ticks/s) +host_mem_usage 223172 # Number of bytes of host memory used +host_seconds 1222.24 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4256266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3266082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7522348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4256266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4256266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4256266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3266082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7522348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4257378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3266936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7524313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4257378 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4257378 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4257378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3266936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7524313 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -43,10 +43,10 @@ system.cpu.dtb.data_hits 26498122 # DT system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 26498155 # DTB accesses -system.cpu.itb.fetch_hits 10034924 # ITB hits +system.cpu.itb.fetch_hits 10035828 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10034973 # ITB accesses +system.cpu.itb.fetch_accesses 10035877 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,42 +60,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 84024827 # number of cpu cycles simulated +system.cpu.numCycles 84002881 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 13564834 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9782438 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4497092 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 7991226 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 3849853 # Number of BTB hits +system.cpu.branch_predictor.lookups 13564877 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9782208 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4497797 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7992443 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3850454 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 121 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 48.176000 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 5999065 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7565769 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73744929 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 48.176183 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5999677 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7565200 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73745294 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136320401 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136320766 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38529057 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26768938 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3519911 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 976323 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4496234 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5744468 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.905525 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57470438 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 38528678 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26769096 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3520460 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 976479 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4496939 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5743763 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.912410 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57470351 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83640241 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83639631 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 11659 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7743859 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76280968 # Number of cycles cpu stages are processed. -system.cpu.activity 90.783844 # Percentage of cycles cpu is active +system.cpu.timesIdled 11378 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7720370 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76282511 # Number of cycles cpu stages are processed. +system.cpu.activity 90.809399 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -107,144 +107,144 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.914277 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.914038 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.914277 # CPI: Total CPI of All Threads -system.cpu.ipc 1.093761 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.914038 # CPI: Total CPI of All Threads +system.cpu.ipc 1.094046 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.093761 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27805541 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56219286 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.907946 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34577681 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49447146 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.848257 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34047365 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49977462 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.479399 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65995198 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029629 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.457502 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30080947 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53943880 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.199930 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 8128 # number of replacements -system.cpu.icache.tagsinuse 1492.257079 # Cycle average of tags in use -system.cpu.icache.total_refs 10023168 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10013 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1001.015480 # Average number of references to valid blocks. +system.cpu.ipc_total 1.094046 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27781439 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56221442 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.927993 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34555420 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49447461 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.864006 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34024816 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.495656 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65973303 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029578 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.463047 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30058791 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53944090 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.216952 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 8127 # number of replacements +system.cpu.icache.tagsinuse 1492.293343 # Cycle average of tags in use +system.cpu.icache.total_refs 10024070 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1001.205553 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.257079 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728641 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728641 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10023168 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10023168 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10023168 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10023168 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10023168 # number of overall hits -system.cpu.icache.overall_hits::total 10023168 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11752 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11752 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11752 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11752 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11752 # number of overall misses -system.cpu.icache.overall_misses::total 11752 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 302404500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 302404500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 302404500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 302404500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 302404500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 302404500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 10034920 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 10034920 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 10034920 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 10034920 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 10034920 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 10034920 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1492.293343 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728659 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728659 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10024070 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10024070 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10024070 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10024070 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10024070 # number of overall hits +system.cpu.icache.overall_hits::total 10024070 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11754 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11754 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11754 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11754 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11754 # number of overall misses +system.cpu.icache.overall_misses::total 11754 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 284626500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 284626500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 284626500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 284626500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 284626500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 284626500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10035824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10035824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10035824 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10035824 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10035824 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10035824 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25732.173247 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25732.173247 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25732.173247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25732.173247 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24215.288412 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24215.288412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24215.288412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 91000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 92000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 15166.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 15333.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1739 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1739 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1739 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1739 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1739 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1739 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10013 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10013 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10013 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10013 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10013 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10013 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234933000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 234933000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234933000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 234933000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234933000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 234933000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1742 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1742 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1742 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1742 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1742 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231904000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 231904000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231904000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 231904000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231904000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 231904000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23462.798362 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23462.798362 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23162.604874 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23162.604874 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.425760 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491190 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.465399 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491189 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.864597 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.864148 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.425760 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351911 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351911 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995640 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995640 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 1441.465399 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351920 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351920 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995639 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995639 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6495550 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6495550 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491190 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491190 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491190 # number of overall hits -system.cpu.dcache.overall_hits::total 26491190 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 558 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 558 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 26491189 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491189 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491189 # number of overall hits +system.cpu.dcache.overall_hits::total 26491189 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 559 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 559 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5553 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5553 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6111 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6111 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6111 # number of overall misses -system.cpu.dcache.overall_misses::total 6111 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29911500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29911500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 335932500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 335932500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 365844000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 365844000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 365844000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 365844000 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 6112 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6112 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6112 # number of overall misses +system.cpu.dcache.overall_misses::total 6112 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28955000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28955000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 305088500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 305088500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 334043500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 334043500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 334043500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 334043500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -261,32 +261,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53604.838710 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53604.838710 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60495.678012 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60495.678012 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59866.470299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59866.470299 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51797.853309 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51797.853309 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54941.202953 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54941.202953 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41291000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41228500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49928.657799 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49853.083434 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3805 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 3805 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3888 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3888 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3888 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3888 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3889 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3889 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3889 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3889 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24206500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24206500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96919000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 96919000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 121125500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 121125500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 121125500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 121125500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24156000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24156000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96637000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 96637000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 120793000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 120793000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 120793000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 120793000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50961.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50961.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55445.652174 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55445.652174 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50854.736842 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50854.736842 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55284.324943 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55284.324943 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.621103 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7286 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2189.683531 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.219988 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.844366 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.786741 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 350.989996 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.845444 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.840268 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 350.997820 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055566 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066822 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7219 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066824 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7272 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7219 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 7218 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7298 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7219 # number of overall hits +system.cpu.l2cache.demand_hits::total 7297 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7218 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 7298 # number of overall hits +system.cpu.l2cache.overall_hits::total 7297 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149287500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23083500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 172371000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94426500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 94426500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 149287500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 117510000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266797500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 149287500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 117510000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266797500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10013 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149399500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23132500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 172532000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94615000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 94615000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 149399500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 117747500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 267147000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 149399500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 117747500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 267147000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 10488 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10013 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 10012 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 12236 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10013 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12235 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10012 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 12236 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279037 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 12235 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279065 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.306636 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.306665 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279037 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279065 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.403563 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279037 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.403596 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.403563 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53431.460272 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54700.236967 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53597.947761 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54835.365854 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54835.365854 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54029.465371 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54029.465371 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53471.546170 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54816.350711 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53648.009950 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54944.831591 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54944.831591 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54100.243013 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54100.243013 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115196500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17936000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133132500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73235000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73235000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115196500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91171000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 206367500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115196500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91171000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 206367500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115312500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17984000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133296500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73481500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73481500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91465500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 206778000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91465500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 206778000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306636 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.403563 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.403563 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41229.957051 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42502.369668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41396.921642 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42529.036005 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42529.036005 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41271.474588 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42616.113744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41447.916667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42672.183508 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42672.183508 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 79c8453b1..4339a22dc 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023661 # Number of seconds simulated -sim_ticks 23661066000 # Number of ticks simulated -final_tick 23661066000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023660 # Number of seconds simulated +sim_ticks 23659827000 # Number of ticks simulated +final_tick 23659827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163409 # Simulator instruction rate (inst/s) -host_op_rate 163409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45930776 # Simulator tick rate (ticks/s) -host_mem_usage 223740 # Number of bytes of host memory used -host_seconds 515.15 # Real time elapsed on the host +host_inst_rate 114539 # Simulator instruction rate (inst/s) +host_op_rate 114539 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32192844 # Simulator tick rate (ticks/s) +host_mem_usage 224192 # Number of bytes of host memory used +host_seconds 734.94 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 197312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 197632 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory -system.physmem.bytes_read::total 335744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 197312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 197312 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3083 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 336064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 197632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 197632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3088 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5246 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8339100 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5850624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14189724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8339100 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8339100 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8339100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5850624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14189724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 5251 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8353062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5850930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14203992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8353062 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8353062 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8353062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5850930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14203992 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23226472 # DTB read hits -system.cpu.dtb.read_misses 199471 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23425943 # DTB read accesses -system.cpu.dtb.write_hits 7079215 # DTB write hits -system.cpu.dtb.write_misses 1341 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 7080556 # DTB write accesses -system.cpu.dtb.data_hits 30305687 # DTB hits -system.cpu.dtb.data_misses 200812 # DTB misses -system.cpu.dtb.data_acv 5 # DTB access violations -system.cpu.dtb.data_accesses 30506499 # DTB accesses -system.cpu.itb.fetch_hits 14950241 # ITB hits -system.cpu.itb.fetch_misses 107 # ITB misses +system.cpu.dtb.read_hits 23229098 # DTB read hits +system.cpu.dtb.read_misses 198676 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 23427774 # DTB read accesses +system.cpu.dtb.write_hits 7078776 # DTB write hits +system.cpu.dtb.write_misses 1365 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7080141 # DTB write accesses +system.cpu.dtb.data_hits 30307874 # DTB hits +system.cpu.dtb.data_misses 200041 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 30507915 # DTB accesses +system.cpu.itb.fetch_hits 14959914 # ITB hits +system.cpu.itb.fetch_misses 83 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14950348 # ITB accesses +system.cpu.itb.fetch_accesses 14959997 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,146 +60,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47322133 # number of cpu cycles simulated +system.cpu.numCycles 47319655 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15026940 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10894124 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 964629 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8768677 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7072325 # Number of BTB hits +system.cpu.BPredUnit.lookups 15036576 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10900203 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 965407 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8822625 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7081383 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1489344 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3225 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15650036 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128237375 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15026940 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8561669 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22385381 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4637420 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5548184 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2165 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14950241 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 337394 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47225069 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.715451 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.372476 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1488044 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3227 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15623244 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128299344 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15036576 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8569427 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22397875 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4641617 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5564099 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1980 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14959914 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 337946 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47229880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.716487 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.372485 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24839688 52.60% 52.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2391446 5.06% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1209126 2.56% 60.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1776446 3.76% 63.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2802962 5.94% 69.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1171165 2.48% 72.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1227887 2.60% 75.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 787448 1.67% 76.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11018901 23.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24832005 52.58% 52.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2392801 5.07% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1209799 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1776867 3.76% 63.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2804961 5.94% 69.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1173464 2.48% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1230763 2.61% 75.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 789158 1.67% 76.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11020062 23.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47225069 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317546 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.709882 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17490874 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4250840 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20765641 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090220 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3627494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2542741 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12176 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125152088 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32110 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3627494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18655906 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 966254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8182 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20668416 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3298817 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122169743 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 401900 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2424267 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89702215 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158657740 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148914395 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9743345 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47229880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317766 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.711333 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17466031 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4264969 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20777128 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090965 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3630787 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2547167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12222 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125218187 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32252 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3630787 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18637244 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 968362 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8091 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20675127 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3310269 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122217574 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 404537 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2431302 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89737060 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158727741 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148984302 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9743439 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21274854 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1091 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1100 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8739612 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25558040 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8300974 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2604808 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 921406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106164029 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2236 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96990974 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 187003 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21520200 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16153199 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1847 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47225069 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.053803 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875376 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21309699 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1072 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1080 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8762996 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25566964 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8306109 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2633900 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 924738 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106206807 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2480 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 97009064 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188398 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21564802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16193043 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2091 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47229880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.053977 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.874944 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12469931 26.41% 26.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9437048 19.98% 46.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8469534 17.93% 64.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6320288 13.38% 77.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4943441 10.47% 88.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2849790 6.03% 94.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723941 3.65% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 801134 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 209962 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12465875 26.39% 26.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9434862 19.98% 46.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8477387 17.95% 64.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6321383 13.38% 77.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4949351 10.48% 88.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2846830 6.03% 94.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1724266 3.65% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801279 1.70% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 208647 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47225069 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47229880 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 187127 11.94% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 172 0.01% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7127 0.45% 12.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5609 0.36% 12.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843370 53.79% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445220 28.40% 94.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79228 5.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189791 12.08% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 221 0.01% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7127 0.45% 12.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5711 0.36% 12.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843066 53.68% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445505 28.36% 94.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79246 5.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58991306 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480706 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59007350 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480907 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802495 2.89% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115483 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386219 2.46% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311493 0.32% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759735 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2801835 2.89% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115568 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386144 2.46% 66.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311424 0.32% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759643 0.78% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued @@ -221,84 +221,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23972181 24.72% 92.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7171030 7.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23975074 24.71% 92.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7170793 7.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96990974 # Type of FU issued -system.cpu.iq.rate 2.049590 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1567853 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016165 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227829224 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118898019 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87368354 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15132649 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8823096 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7068677 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90563080 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7995740 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518780 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 97009064 # Type of FU issued +system.cpu.iq.rate 2.050080 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1570667 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016191 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227877046 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118983933 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87385352 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15130027 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8824854 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7067767 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90585387 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7994337 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1520935 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5561842 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19579 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34790 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1799871 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5570766 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20063 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34811 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1805006 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10523 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3627494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 132338 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17118 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116467170 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 392102 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25558040 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8300974 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2236 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2929 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 49 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34790 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 570155 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508194 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1078349 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95694648 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23426609 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1296326 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3630787 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133855 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17474 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116506957 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 391259 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25566964 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8306109 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2480 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3139 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 46 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34811 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 570809 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508196 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1079005 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95710462 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23428475 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1298602 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10300905 # number of nop insts executed -system.cpu.iew.exec_refs 30507339 # number of memory reference insts executed -system.cpu.iew.exec_branches 12077728 # Number of branches executed -system.cpu.iew.exec_stores 7080730 # Number of stores executed -system.cpu.iew.exec_rate 2.022196 # Inst execution rate -system.cpu.iew.wb_sent 94980194 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94437031 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64621172 # num instructions producing a value -system.cpu.iew.wb_consumers 90003030 # num instructions consuming a value +system.cpu.iew.exec_nop 10297670 # number of nop insts executed +system.cpu.iew.exec_refs 30508815 # number of memory reference insts executed +system.cpu.iew.exec_branches 12080088 # Number of branches executed +system.cpu.iew.exec_stores 7080340 # Number of stores executed +system.cpu.iew.exec_rate 2.022637 # Inst execution rate +system.cpu.iew.wb_sent 94996847 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94453119 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64630172 # num instructions producing a value +system.cpu.iew.wb_consumers 90018458 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.995621 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717989 # average fanout of values written-back +system.cpu.iew.wb_rate 1.996065 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24565165 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24605076 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 952869 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43597575 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.107985 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.734489 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 953560 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43599093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.107912 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.734433 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17052737 39.11% 39.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9973933 22.88% 61.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4509329 10.34% 72.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2295130 5.26% 77.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1618190 3.71% 81.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1123694 2.58% 83.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722585 1.66% 85.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 817482 1.88% 87.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5484495 12.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17053308 39.11% 39.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9978024 22.89% 62.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4508053 10.34% 72.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2287531 5.25% 77.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1622514 3.72% 81.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1125878 2.58% 83.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 721380 1.65% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820634 1.88% 87.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5481771 12.57% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43597575 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43599093 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -309,70 +309,70 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5484495 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5481771 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154580260 # The number of ROB reads -system.cpu.rob.rob_writes 236588154 # The number of ROB writes -system.cpu.timesIdled 2240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 97064 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154624413 # The number of ROB reads +system.cpu.rob.rob_writes 236671244 # The number of ROB writes +system.cpu.timesIdled 1995 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 89775 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.562156 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.562156 # CPI: Total CPI of All Threads -system.cpu.ipc 1.778865 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.778865 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129472042 # number of integer regfile reads -system.cpu.int_regfile_writes 70778136 # number of integer regfile writes -system.cpu.fp_regfile_reads 6192217 # number of floating regfile reads -system.cpu.fp_regfile_writes 6050128 # number of floating regfile writes -system.cpu.misc_regfile_reads 714420 # number of misc regfile reads +system.cpu.cpi 0.562127 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.562127 # CPI: Total CPI of All Threads +system.cpu.ipc 1.778959 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.778959 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129495815 # number of integer regfile reads +system.cpu.int_regfile_writes 70794338 # number of integer regfile writes +system.cpu.fp_regfile_reads 6191717 # number of floating regfile reads +system.cpu.fp_regfile_writes 6049387 # number of floating regfile writes +system.cpu.misc_regfile_reads 714327 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 10236 # number of replacements -system.cpu.icache.tagsinuse 1604.355346 # Cycle average of tags in use -system.cpu.icache.total_refs 14936697 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12175 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1226.833429 # Average number of references to valid blocks. +system.cpu.icache.replacements 10388 # number of replacements +system.cpu.icache.tagsinuse 1605.369069 # Cycle average of tags in use +system.cpu.icache.total_refs 14946221 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12326 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1212.576748 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1604.355346 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.783377 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.783377 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14936697 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14936697 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14936697 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14936697 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14936697 # number of overall hits -system.cpu.icache.overall_hits::total 14936697 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13544 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13544 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13544 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13544 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13544 # number of overall misses -system.cpu.icache.overall_misses::total 13544 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214516500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214516500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214516500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214516500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214516500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214516500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14950241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14950241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14950241 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14950241 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14950241 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14950241 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000906 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000906 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000906 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000906 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000906 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000906 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15838.489368 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15838.489368 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15838.489368 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15838.489368 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15838.489368 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15838.489368 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1605.369069 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.783872 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.783872 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14946221 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14946221 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14946221 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14946221 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14946221 # number of overall hits +system.cpu.icache.overall_hits::total 14946221 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13693 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13693 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13693 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13693 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13693 # number of overall misses +system.cpu.icache.overall_misses::total 13693 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 189030000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 189030000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 189030000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 189030000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 189030000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 189030000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14959914 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14959914 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14959914 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14959914 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14959914 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14959914 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000915 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000915 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13804.863799 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13804.863799 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13804.863799 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13804.863799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13804.863799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13804.863799 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,300 +381,300 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1369 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1369 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1369 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1369 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1369 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1369 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12175 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12175 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12175 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12175 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12175 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12175 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 142455000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 142455000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 142455000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 142455000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 142455000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 142455000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000814 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000814 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000814 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.616016 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.616016 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.616016 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.616016 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.616016 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.616016 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1367 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1367 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1367 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1367 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1367 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1367 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12326 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12326 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12326 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12326 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12326 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12326 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130707500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130707500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130707500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130707500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130707500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130707500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000824 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000824 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000824 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10604.210612 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10604.210612 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10604.210612 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10604.210612 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10604.210612 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10604.210612 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158 # number of replacements -system.cpu.dcache.tagsinuse 1456.192464 # Cycle average of tags in use -system.cpu.dcache.total_refs 28189208 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1458.278820 # Cycle average of tags in use +system.cpu.dcache.total_refs 28189701 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12567.636202 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12567.855996 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1456.192464 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.355516 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.355516 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21695723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21695723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493020 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493020 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 465 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 465 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28188743 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28188743 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28188743 # number of overall hits -system.cpu.dcache.overall_hits::total 28188743 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 984 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 984 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8083 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8083 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1458.278820 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.356025 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.356025 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21696214 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21696214 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493021 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493021 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 466 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 466 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28189235 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28189235 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28189235 # number of overall hits +system.cpu.dcache.overall_hits::total 28189235 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 958 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 958 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8082 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8082 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9067 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9067 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9067 # number of overall misses -system.cpu.dcache.overall_misses::total 9067 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32711000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32711000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 344620000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 344620000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 45000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 45000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 377331000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 377331000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 377331000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 377331000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21696707 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21696707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9040 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9040 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9040 # number of overall misses +system.cpu.dcache.overall_misses::total 9040 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29562000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29562000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 293120000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 293120000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 322682000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 322682000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 322682000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 322682000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21697172 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21697172 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28197810 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28197810 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28197810 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28197810 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 467 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28198275 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28198275 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28198275 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28198275 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001243 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001243 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000322 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000322 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000322 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000322 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33242.886179 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33242.886179 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42635.160213 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42635.160213 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41615.859711 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41615.859711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41615.859711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41615.859711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12500 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002141 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002141 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000321 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000321 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000321 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000321 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30858.037578 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30858.037578 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36268.250433 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36268.250433 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35694.911504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35694.911504 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 474 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6351 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6351 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6825 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6825 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6825 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6825 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 510 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 510 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 446 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 446 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6352 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6798 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6798 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6798 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6798 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1730 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1730 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 2242 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2242 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2242 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2242 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18104500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18104500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 68881000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 68881000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 68210000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 68210000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86985500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 86985500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 86985500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 86985500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86285000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 86285000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 86285000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 86285000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39769.630485 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39769.630485 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35302.734375 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35302.734375 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39427.745665 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39427.745665 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38798.171276 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38798.171276 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.250527 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.363851 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253224 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360423 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.250527 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.363851 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32072.656503 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34913.566740 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32439.406780 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35712.192263 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35712.192263 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32072.656503 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35543.458160 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33503.717118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32072.656503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35543.458160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33503.717118 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360423 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32108.160622 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35073.144105 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32491.116751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35808.211144 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35808.211144 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32108.160622 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35652.565881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33568.177490 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32108.160622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35652.565881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33568.177490 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index d3e99f110..220e3a05f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.118780 # Number of seconds simulated -sim_ticks 118779533000 # Number of ticks simulated -final_tick 118779533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.118729 # Number of seconds simulated +sim_ticks 118729316000 # Number of ticks simulated +final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1503058 # Simulator instruction rate (inst/s) -host_op_rate 1503057 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1942616372 # Simulator tick rate (ticks/s) -host_mem_usage 222720 # Number of bytes of host memory used -host_seconds 61.14 # Real time elapsed on the host +host_inst_rate 979371 # Simulator instruction rate (inst/s) +host_op_rate 979371 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1265246648 # Simulator tick rate (ticks/s) +host_mem_usage 223148 # Number of bytes of host memory used +host_seconds 93.84 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 167744 # Nu system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2567446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2567446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237559066 # number of cpu cycles simulated +system.cpu.numCycles 237458632 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237559066 # Number of busy cycles +system.cpu.num_busy_cycles 237458632 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 6681 # number of replacements -system.cpu.icache.tagsinuse 1417.992791 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.052773 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1417.992791 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.692379 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.692379 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 229226000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 229226000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 229226000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 229226000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 229226000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 229226000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26936.075206 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26936.075206 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26936.075206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26936.075206 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203696000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203696000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203696000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203696000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203696000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203696000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23936.075206 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23936.075206 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.982871 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.982871 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352047 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352047 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 2223 # n system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24380000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24380000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 96796000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 96796000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121176000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121176000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121176000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121176000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51326.315789 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51326.315789 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54510.121457 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54510.121457 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22955000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22955000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114507000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114507000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114507000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114507000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48326.315789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48326.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2073.981313 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2074.070560 # Cycle average of tags in use system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.795350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1704.943449 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.242515 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052031 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.063293 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.063296 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index e95f937b3..e11bd02ec 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.076020 # Number of seconds simulated -sim_ticks 76020082000 # Number of ticks simulated -final_tick 76020082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.075929 # Number of seconds simulated +sim_ticks 75929256000 # Number of ticks simulated +final_tick 75929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108434 # Simulator instruction rate (inst/s) -host_op_rate 118724 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47832871 # Simulator tick rate (ticks/s) -host_mem_usage 232824 # Number of bytes of host memory used -host_seconds 1589.29 # Real time elapsed on the host -sim_insts 172333166 # Number of instructions simulated -sim_ops 188686648 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 132416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112256 # Number of bytes read from this memory -system.physmem.bytes_read::total 244672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 132416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 132416 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1754 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3823 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1741856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1476662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3218518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1741856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1741856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1741856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1476662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3218518 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 99785 # Simulator instruction rate (inst/s) +host_op_rate 109254 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43964821 # Simulator tick rate (ticks/s) +host_mem_usage 238132 # Number of bytes of host memory used +host_seconds 1727.05 # Real time elapsed on the host +sim_insts 172333091 # Number of instructions simulated +sim_ops 188686573 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 132864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112384 # Number of bytes read from this memory +system.physmem.bytes_read::total 245248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 132864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 132864 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2076 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1756 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3832 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1749839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1480115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3229954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1749839 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1749839 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1749839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1480115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3229954 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,141 +70,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 152040165 # number of cpu cycles simulated +system.cpu.numCycles 151858513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 96858484 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76060964 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6563923 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46433794 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44260375 # Number of BTB hits +system.cpu.BPredUnit.lookups 96795637 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 76023233 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6554345 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46458722 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44211681 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4475068 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 89115 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40665802 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 388394971 # Number of instructions fetch has processed -system.cpu.fetch.Branches 96858484 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48735443 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82285186 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28468460 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7130109 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9134 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4476295 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 89485 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40599440 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 388212036 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96795637 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48687976 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 82231847 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28434690 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7095448 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8914 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 37715921 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1893970 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 151978869 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.797548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152738 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37656314 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1885789 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 151799953 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.799634 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153355 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69866943 45.97% 45.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5495765 3.62% 49.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10729414 7.06% 56.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10452168 6.88% 63.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8790327 5.78% 69.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6826108 4.49% 73.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6308927 4.15% 77.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8362057 5.50% 83.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25147160 16.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69738143 45.94% 45.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5498940 3.62% 49.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10708649 7.05% 56.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10436622 6.88% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8785452 5.79% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6828707 4.50% 73.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6299043 4.15% 77.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8356617 5.51% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25147780 16.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151978869 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.637059 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.554555 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46697521 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5834788 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76594287 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1116884 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21735389 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14843189 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162820 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401520259 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 676254 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21735389 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52210117 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 723485 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 695226 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72137663 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4476989 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 379210260 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 151799953 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.637407 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.556406 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46621790 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5807519 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76550031 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1109408 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21711205 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14812709 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162826 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401248063 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 743977 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21711205 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52126095 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 710072 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 694282 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72094443 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4463856 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 378978195 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 320036 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3584710 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 642738695 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1615361151 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1597815620 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17545531 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092371 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 344646324 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33437 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33435 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12677945 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 44005038 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16906133 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5806665 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3723076 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 335023972 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55533 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 252928025 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 900898 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 145168889 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 374298631 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4288 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151978869 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.664232 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759052 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 318341 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3575220 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 642418416 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1614444989 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1596851669 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17593320 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092251 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 344326165 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33370 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 33366 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12643089 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43991113 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16880527 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5791698 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3695359 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334838724 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55508 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 252834206 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 902162 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 144982237 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 373879643 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4278 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151799953 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.665575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.759908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58441388 38.45% 38.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23049169 15.17% 53.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25167243 16.56% 70.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20506081 13.49% 83.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12879623 8.47% 92.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6582625 4.33% 96.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4058401 2.67% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1110608 0.73% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 183731 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58349265 38.44% 38.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22992328 15.15% 53.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25145387 16.56% 70.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20486668 13.50% 83.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12884605 8.49% 92.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6585084 4.34% 96.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4053755 2.67% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1118158 0.74% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 184703 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151978869 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151799953 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 958151 37.34% 37.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5590 0.22% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 95 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 28 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1196632 46.64% 84.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 405192 15.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 967156 37.45% 37.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5599 0.22% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 95 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1198375 46.40% 84.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411308 15.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197423347 78.06% 78.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995576 0.39% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 197345283 78.05% 78.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 996010 0.39% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued @@ -223,167 +223,167 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33202 0.01% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33191 0.01% 78.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 163925 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254716 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76426 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467079 0.18% 78.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206343 0.08% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71849 0.03% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39030082 15.43% 94.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14205161 5.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164019 0.06% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254959 0.10% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76456 0.03% 78.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467688 0.18% 78.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206418 0.08% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71860 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39024792 15.43% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14193209 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 252928025 # Type of FU issued -system.cpu.iq.rate 1.663561 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2565688 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010144 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 657530631 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 478025695 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240682393 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3770874 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2241416 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1850793 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253600335 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1893378 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2031332 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 252834206 # Type of FU issued +system.cpu.iq.rate 1.664933 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2582566 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010214 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 657177755 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477646556 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 240591983 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3775338 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2248788 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1851684 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253520354 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1896418 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2029780 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14149525 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17193 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19478 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4255470 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14135615 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17349 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19653 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4229879 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21735389 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15851 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 654 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 335097391 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 841360 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 44005038 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16906133 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 32986 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 165 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19478 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4108816 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3932770 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8041586 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 245927260 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37410682 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7000765 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21711205 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12896 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 616 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334912035 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 838129 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43991113 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16880527 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 32938 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 266 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19653 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4103971 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3924992 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8028963 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 245839126 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37402304 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6995080 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17886 # number of nop insts executed -system.cpu.iew.exec_refs 51227779 # number of memory reference insts executed -system.cpu.iew.exec_branches 54055496 # Number of branches executed -system.cpu.iew.exec_stores 13817097 # Number of stores executed -system.cpu.iew.exec_rate 1.617515 # Inst execution rate -system.cpu.iew.wb_sent 243665877 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242533186 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150106940 # num instructions producing a value -system.cpu.iew.wb_consumers 269220391 # num instructions consuming a value +system.cpu.iew.exec_nop 17803 # number of nop insts executed +system.cpu.iew.exec_refs 51215601 # number of memory reference insts executed +system.cpu.iew.exec_branches 54034095 # Number of branches executed +system.cpu.iew.exec_stores 13813297 # Number of stores executed +system.cpu.iew.exec_rate 1.618870 # Inst execution rate +system.cpu.iew.wb_sent 243576806 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 242443667 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150073604 # num instructions producing a value +system.cpu.iew.wb_consumers 269189037 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.595192 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557562 # average fanout of values written-back +system.cpu.iew.wb_rate 1.596510 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557503 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 146396335 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6410682 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130243481 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.448833 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.161152 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 146211047 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51230 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6401258 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130088749 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.450556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.162504 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59985952 46.06% 46.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32109376 24.65% 70.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13980234 10.73% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7652770 5.88% 87.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4424001 3.40% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1333573 1.02% 91.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1734640 1.33% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1282307 0.98% 94.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7740628 5.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59880842 46.03% 46.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 32046581 24.63% 70.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13987597 10.75% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7657894 5.89% 87.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4414755 3.39% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1334314 1.03% 91.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1737378 1.34% 93.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1284458 0.99% 94.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7744930 5.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130243481 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347554 # Number of instructions committed -system.cpu.commit.committedOps 188701036 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130088749 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347479 # Number of instructions committed +system.cpu.commit.committedOps 188700961 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506176 # Number of memory references committed -system.cpu.commit.loads 29855513 # Number of loads committed +system.cpu.commit.refs 42506146 # Number of memory references committed +system.cpu.commit.loads 29855498 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40306340 # Number of branches committed +system.cpu.commit.branches 40306325 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130333 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130273 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7740628 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7744930 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457595023 # The number of ROB reads -system.cpu.rob.rob_writes 692049675 # The number of ROB writes -system.cpu.timesIdled 1805 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61296 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333166 # Number of Instructions Simulated -system.cpu.committedOps 188686648 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333166 # Number of Instructions Simulated -system.cpu.cpi 0.882246 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.882246 # CPI: Total CPI of All Threads -system.cpu.ipc 1.133471 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.133471 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092342028 # number of integer regfile reads -system.cpu.int_regfile_writes 388769433 # number of integer regfile writes -system.cpu.fp_regfile_reads 2911784 # number of floating regfile reads -system.cpu.fp_regfile_writes 2509539 # number of floating regfile writes -system.cpu.misc_regfile_reads 474699170 # number of misc regfile reads -system.cpu.misc_regfile_writes 832094 # number of misc regfile writes -system.cpu.icache.replacements 2665 # number of replacements -system.cpu.icache.tagsinuse 1365.695198 # Cycle average of tags in use -system.cpu.icache.total_refs 37710725 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4406 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8558.948025 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 457250626 # The number of ROB reads +system.cpu.rob.rob_writes 691654263 # The number of ROB writes +system.cpu.timesIdled 1589 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 58560 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333091 # Number of Instructions Simulated +system.cpu.committedOps 188686573 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333091 # Number of Instructions Simulated +system.cpu.cpi 0.881192 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.881192 # CPI: Total CPI of All Threads +system.cpu.ipc 1.134827 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.134827 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1091994433 # number of integer regfile reads +system.cpu.int_regfile_writes 388620965 # number of integer regfile writes +system.cpu.fp_regfile_reads 2912840 # number of floating regfile reads +system.cpu.fp_regfile_writes 2511233 # number of floating regfile writes +system.cpu.misc_regfile_reads 474441039 # number of misc regfile reads +system.cpu.misc_regfile_writes 832064 # number of misc regfile writes +system.cpu.icache.replacements 2657 # number of replacements +system.cpu.icache.tagsinuse 1370.154308 # Cycle average of tags in use +system.cpu.icache.total_refs 37651093 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4401 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8555.122245 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1365.695198 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.666843 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.666843 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37710725 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37710725 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37710725 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37710725 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37710725 # number of overall hits -system.cpu.icache.overall_hits::total 37710725 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5196 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5196 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5196 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5196 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5196 # number of overall misses -system.cpu.icache.overall_misses::total 5196 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 114882000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 114882000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 114882000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 114882000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 114882000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 114882000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37715921 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37715921 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37715921 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37715921 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37715921 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37715921 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000138 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000138 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000138 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000138 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000138 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22109.699769 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22109.699769 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22109.699769 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22109.699769 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22109.699769 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22109.699769 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1370.154308 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.669021 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.669021 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37651093 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37651093 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37651093 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37651093 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37651093 # number of overall hits +system.cpu.icache.overall_hits::total 37651093 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5221 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5221 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5221 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5221 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5221 # number of overall misses +system.cpu.icache.overall_misses::total 5221 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 109554000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 109554000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 109554000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 109554000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 109554000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 109554000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37656314 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37656314 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37656314 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37656314 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37656314 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37656314 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000139 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000139 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000139 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000139 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000139 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000139 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20983.336526 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20983.336526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20983.336526 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20983.336526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20983.336526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20983.336526 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,146 +392,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 790 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 790 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 790 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 790 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 790 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 790 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4406 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4406 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4406 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4406 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4406 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4406 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 80533500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 80533500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 80533500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 80533500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 80533500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 80533500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 819 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 819 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 819 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 819 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 819 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 819 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4402 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4402 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4402 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4402 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4402 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4402 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 80099500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 80099500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 80099500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 80099500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 80099500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 80099500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000117 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000117 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000117 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18278.143441 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18278.143441 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18278.143441 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18278.143441 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18278.143441 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18278.143441 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18196.160836 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18196.160836 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18196.160836 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18196.160836 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18196.160836 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18196.160836 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 59 # number of replacements -system.cpu.dcache.tagsinuse 1417.829919 # Cycle average of tags in use -system.cpu.dcache.total_refs 47315704 # Total number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1414.265666 # Cycle average of tags in use +system.cpu.dcache.total_refs 47308069 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1866 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25356.754555 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25352.662915 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1417.829919 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.346150 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.346150 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34900386 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34900386 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356583 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356583 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 30299 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 30299 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 28436 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 28436 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 47256969 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47256969 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 47256969 # number of overall hits -system.cpu.dcache.overall_hits::total 47256969 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1941 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1941 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7704 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7704 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1414.265666 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345280 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.345280 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34892726 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34892726 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356654 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356654 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 30268 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 30268 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 28421 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 28421 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 47249380 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47249380 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 47249380 # number of overall hits +system.cpu.dcache.overall_hits::total 47249380 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1980 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1980 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7633 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7633 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9645 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9645 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9645 # 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number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34902327 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34902327 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9613 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9613 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9613 # number of overall misses +system.cpu.dcache.overall_misses::total 9613 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63002000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63002000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 235161500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 235161500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 68000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 68000 # 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number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28436 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47266614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47266614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47266614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47266614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000623 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000623 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30270 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 30270 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28421 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28421 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 47258993 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47258993 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47258993 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47258993 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000057 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000057 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000617 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000617 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36811.179804 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36811.179804 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36974.493769 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36974.493769 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 40250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 40250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36941.627786 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36941.627786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36941.627786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36941.627786 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000203 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000203 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31819.191919 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31819.191919 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30808.528757 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30808.528757 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31016.696141 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31016.696141 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 18000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1165 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1165 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6614 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6614 # 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mshr miss rate for WriteReq accesses @@ -540,98 +540,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000039 system.cpu.dcache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34044.458763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34044.458763 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35573.853211 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35573.853211 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34937.834941 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34937.834941 # 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number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1866 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.470722 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.883871 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.532523 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991751 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.991751 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.470722 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.946945 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.612404 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.470722 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.946945 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.612404 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35257.955641 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36751.094891 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35628.669808 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34772.181146 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34772.181146 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35257.955641 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35539.332201 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 35387.399115 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35257.955641 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35539.332201 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 35387.399115 # average overall miss latency +system.cpu.l2cache.overall_accesses::total 6268 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.472740 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887468 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.535301 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991697 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.991697 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.472740 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.948017 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.614231 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.472740 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.948017 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.614231 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35251.802018 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36810.518732 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35641.621622 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34907.441860 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34907.441860 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35251.802018 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35654.041832 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 35436.623377 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35251.802018 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35654.041832 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 35436.623377 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,50 +649,50 @@ system.cpu.l2cache.demand_mshr_hits::total 18 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 18 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2069 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 672 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2741 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2069 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1754 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3823 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2069 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1754 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3823 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66421500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22618000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89039500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34148500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34148500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 56766500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 123188000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 56766500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 123188000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867097 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.529048 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939979 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.609534 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939979 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.609534 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32103.189947 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33657.738095 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32484.312295 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31560.536044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31560.536044 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32103.189947 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32364.025086 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32222.861627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32103.189947 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32364.025086 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32222.861627 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2076 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 681 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2757 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2076 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1756 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3832 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2076 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1756 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3832 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66628500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22957500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89586000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33945000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33945000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66628500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 56902500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 123531000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66628500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 56902500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 123531000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.471604 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870844 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.531829 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991697 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991697 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.471604 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941050 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.611359 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.471604 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941050 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.611359 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32094.653179 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33711.453744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32494.015234 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31576.744186 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31576.744186 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32094.653179 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32404.612756 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32236.691023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32094.653179 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32404.612756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32236.691023 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index ee5d7fbdb..fea3635fb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232090 # Number of seconds simulated -sim_ticks 232089948000 # Number of ticks simulated -final_tick 232089948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.232072 # Number of seconds simulated +sim_ticks 232072304000 # Number of ticks simulated +final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1108463 # Simulator instruction rate (inst/s) -host_op_rate 1213886 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1497086914 # Simulator tick rate (ticks/s) -host_mem_usage 230968 # Number of bytes of host memory used -host_seconds 155.03 # Real time elapsed on the host +host_inst_rate 603492 # Simulator instruction rate (inst/s) +host_op_rate 660888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 815011792 # Simulator tick rate (ticks/s) +host_mem_usage 237088 # Number of bytes of host memory used +host_seconds 284.75 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 188185920 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 110656 # Nu system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 476781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 475402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 952183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 476781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 476781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 476781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 475402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 952183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 476817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 475438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 952255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 476817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 476817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 464179896 # number of cpu cycles simulated +system.cpu.numCycles 464144608 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842483 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 42494119 # nu system.cpu.num_load_insts 29849484 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 464179896 # Number of busy cycles +system.cpu.num_busy_cycles 464144608 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1506 # number of replacements -system.cpu.icache.tagsinuse 1147.971530 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1147.986161 # Cycle average of tags in use system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1147.971530 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.560533 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.560533 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.560540 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits @@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 115332000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 115332000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 115332000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 115332000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 115332000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 115332000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112281000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112281000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112281000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112281000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112281000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112281000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses @@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37801.376598 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37801.376598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37801.376598 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36801.376598 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36801.376598 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36801.376598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36801.376598 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 40 # number of replacements -system.cpu.dcache.tagsinuse 1363.590777 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.590777 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332908 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332908 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits @@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 1789 # n system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36195000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36195000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 61264000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 61264000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 97459000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 97459000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 97459000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 97459000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52532.656023 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52532.656023 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55694.545455 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54476.802683 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54476.802683 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54476.802683 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54476.802683 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1789 system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34128000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34128000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92092000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92092000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92092000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92092000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49532.656023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49532.656023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51476.802683 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51476.802683 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51476.802683 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51476.802683 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1675.633213 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 1675.655740 # Cycle average of tags in use system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3.038052 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1169.018140 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 503.577021 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.051136 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 9d89c8f58..5837aae11 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.270629 # Number of seconds simulated -sim_ticks 270628667000 # Number of ticks simulated -final_tick 270628667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.270563 # Number of seconds simulated +sim_ticks 270563082000 # Number of ticks simulated +final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1532509 # Simulator instruction rate (inst/s) -host_op_rate 1532510 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2143977461 # Simulator tick rate (ticks/s) -host_mem_usage 235212 # Number of bytes of host memory used -host_seconds 126.23 # Real time elapsed on the host +host_inst_rate 662631 # Simulator instruction rate (inst/s) +host_op_rate 662631 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 926794797 # Simulator tick rate (ticks/s) +host_mem_usage 226156 # Number of bytes of host memory used +host_seconds 291.93 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 230208 # Nu system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 850642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 372703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1223344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 850642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 850642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 850642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 372703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1223344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541257334 # number of cpu cycles simulated +system.cpu.numCycles 541126164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444518 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 76733958 # nu system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 541257334 # Number of busy cycles +system.cpu.num_busy_cycles 541126164 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10362 # number of replacements -system.cpu.icache.tagsinuse 1591.550018 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.579171 # Cycle average of tags in use system.cpu.icache.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1591.550018 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777124 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777124 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 323106000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 323106000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 323106000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 323106000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 323106000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 323106000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310818000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310818000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310818000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310818000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310818000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26294.433594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26294.433594 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.433594 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25294.433594 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25294.433594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25294.433594 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2 # number of replacements -system.cpu.dcache.tagsinuse 1237.179149 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.203941 # Cycle average of tags in use system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1237.179149 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.302046 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.302046 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.302052 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits @@ -157,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data 1575 # n system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27888000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27888000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60312000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60312000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 56000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 56000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 88200000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 88200000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 88200000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 88200000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) @@ -187,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -249,18 +249,18 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2678.289604 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2678.340865 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2275.240623 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 403.048526 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069435 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.081735 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.081736 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 344b3932c..d3a442923 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,269 +1,269 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084417 # Number of seconds simulated -sim_ticks 84416735500 # Number of ticks simulated -final_tick 84416735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.084599 # Number of seconds simulated +sim_ticks 84599483500 # Number of ticks simulated +final_tick 84599483500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63787 # Simulator instruction rate (inst/s) -host_op_rate 106913 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40771301 # Simulator tick rate (ticks/s) -host_mem_usage 285396 # Number of bytes of host memory used -host_seconds 2070.49 # Real time elapsed on the host +host_inst_rate 50330 # Simulator instruction rate (inst/s) +host_op_rate 84358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32239425 # Simulator tick rate (ticks/s) +host_mem_usage 239332 # Number of bytes of host memory used +host_seconds 2624.10 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362960 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 220032 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124672 # Number of bytes read from this memory -system.physmem.bytes_read::total 344064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219392 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3428 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 344704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3438 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1948 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5376 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2598916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1476864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4075779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2598916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2598916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2598916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1476864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4075779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 5386 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2600867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1473673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4074540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2600867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2600867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2600867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1473673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4074540 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 168833472 # number of cpu cycles simulated +system.cpu.numCycles 169198968 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20699953 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20699953 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2254791 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15116204 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13734495 # Number of BTB hits +system.cpu.BPredUnit.lookups 20690463 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20690463 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2250102 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15079710 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13739283 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27236198 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227395589 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20699953 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13734495 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59717541 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19334489 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 64998537 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 379 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2980 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25696290 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 472102 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 168753880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.217952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.336457 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27218141 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227440359 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20690463 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13739283 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59726319 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19306281 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 65395131 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 224 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1651 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25701311 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 473765 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169122323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.213301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.334482 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 110699150 65.60% 65.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3224321 1.91% 67.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2475319 1.47% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3099058 1.84% 70.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3522120 2.09% 72.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3727832 2.21% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4580737 2.71% 77.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2798912 1.66% 79.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34626431 20.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 111062519 65.67% 65.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3230504 1.91% 67.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2469579 1.46% 69.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3091757 1.83% 70.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3527779 2.09% 72.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3730060 2.21% 75.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4582508 2.71% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2803800 1.66% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34623817 20.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 168753880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122606 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.346863 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40114666 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55275027 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46754888 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9811054 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16798245 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 365144878 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16798245 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47659212 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14495562 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23044 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48366883 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41410934 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355937871 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 38 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17144692 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22141197 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 410198872 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 987348929 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 977397781 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9951148 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169122323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122285 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.344218 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40123368 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55633776 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46741593 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9842729 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16780857 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 365282924 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16780857 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47679812 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14629061 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22937 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48366453 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41643203 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 356095908 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17377193 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22149388 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 410376112 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 987879370 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 977929387 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9949983 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 150770269 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1731 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1722 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89681152 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89661303 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32849139 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58579836 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19046101 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343008159 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4651 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 272074168 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 315487 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 121115880 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 246174480 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3405 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 168753880 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.612254 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.516605 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 150947509 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1877 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1873 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89979833 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89683170 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32866708 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59054771 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19177166 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343137266 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5038 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271920674 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 307949 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 121254430 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 247003349 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3792 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169122323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.607834 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.514763 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 47246333 28.00% 28.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46593223 27.61% 55.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33100078 19.61% 75.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20197900 11.97% 87.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13442909 7.97% 95.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5008835 2.97% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2434360 1.44% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 576818 0.34% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 153424 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 47444811 28.05% 28.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46907027 27.74% 55.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33033517 19.53% 75.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20154930 11.92% 87.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13461767 7.96% 95.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4965301 2.94% 98.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2426983 1.44% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 577544 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 150443 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 168753880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169122323 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 133668 5.05% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2245630 84.89% 89.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 265941 10.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 134207 5.09% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2238473 84.87% 89.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 264949 10.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212775 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177115116 65.10% 65.54% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.54% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1587982 0.58% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68640688 25.23% 91.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23517607 8.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212573 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177106081 65.13% 65.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1583088 0.58% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68507215 25.19% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23511717 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 272074168 # Type of FU issued -system.cpu.iq.rate 1.611494 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2645239 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009722 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 710552167 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 459825601 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 264280356 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5310775 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4610743 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2547999 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 270845077 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2661555 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19085225 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271920674 # Type of FU issued +system.cpu.iq.rate 1.607106 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2637629 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009700 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 710614385 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 460072874 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 264170911 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5294864 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4624558 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2540762 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 270691856 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2653874 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19027871 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33011717 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33669 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 313308 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12333423 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33033584 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33172 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 306303 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12350992 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49764 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 49574 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16798245 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 578433 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 255971 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343012810 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 262853 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89661303 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32849139 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1696 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 171518 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 28262 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 313308 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1334034 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1025575 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2359609 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 268880206 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67501088 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3193962 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16780857 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 570141 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 256886 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343142304 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 262882 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89683170 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32866708 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1845 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 170649 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 30071 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 306303 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1331965 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1023841 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2355806 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 268743201 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67386869 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3177473 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90609613 # number of memory reference insts executed -system.cpu.iew.exec_branches 14778913 # Number of branches executed -system.cpu.iew.exec_stores 23108525 # Number of stores executed -system.cpu.iew.exec_rate 1.592576 # Inst execution rate -system.cpu.iew.wb_sent 267790153 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 266828355 # cumulative count of insts written-back -system.cpu.iew.wb_producers 215466239 # num instructions producing a value -system.cpu.iew.wb_consumers 378707057 # num instructions consuming a value +system.cpu.iew.exec_refs 90490770 # number of memory reference insts executed +system.cpu.iew.exec_branches 14773340 # Number of branches executed +system.cpu.iew.exec_stores 23103901 # Number of stores executed +system.cpu.iew.exec_rate 1.588326 # Inst execution rate +system.cpu.iew.wb_sent 267665043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 266711673 # cumulative count of insts written-back +system.cpu.iew.wb_producers 215305025 # num instructions producing a value +system.cpu.iew.wb_consumers 378544002 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.580423 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.568952 # average fanout of values written-back +system.cpu.iew.wb_rate 1.576320 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.568771 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 121732782 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 121862932 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2255092 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151955635 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.456760 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.933041 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2250269 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 152341466 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.453071 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.928588 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52584491 34.61% 34.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57288776 37.70% 72.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13942421 9.18% 81.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11933178 7.85% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4288993 2.82% 92.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2988620 1.97% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1076250 0.71% 94.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 990012 0.65% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6862894 4.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52729760 34.61% 34.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57497101 37.74% 72.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14043120 9.22% 81.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11929275 7.83% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4291590 2.82% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2949185 1.94% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1071112 0.70% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 989747 0.65% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6840576 4.49% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151955635 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 152341466 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -274,70 +274,70 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6862894 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6840576 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 488188483 # The number of ROB reads -system.cpu.rob.rob_writes 703031879 # The number of ROB writes -system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 79592 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 488726782 # The number of ROB reads +system.cpu.rob.rob_writes 703273689 # The number of ROB writes +system.cpu.timesIdled 1665 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76645 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.278352 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.278352 # CPI: Total CPI of All Threads -system.cpu.ipc 0.782257 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.782257 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 568126600 # number of integer regfile reads -system.cpu.int_regfile_writes 302940757 # number of integer regfile writes -system.cpu.fp_regfile_reads 3504532 # number of floating regfile reads -system.cpu.fp_regfile_writes 2218521 # number of floating regfile writes -system.cpu.misc_regfile_reads 139578385 # number of misc regfile reads +system.cpu.cpi 1.281119 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.281119 # CPI: Total CPI of All Threads +system.cpu.ipc 0.780567 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.780567 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 567776084 # number of integer regfile reads +system.cpu.int_regfile_writes 302793169 # number of integer regfile writes +system.cpu.fp_regfile_reads 3492670 # number of floating regfile reads +system.cpu.fp_regfile_writes 2212557 # number of floating regfile writes +system.cpu.misc_regfile_reads 139469476 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5271 # number of replacements -system.cpu.icache.tagsinuse 1637.773069 # Cycle average of tags in use -system.cpu.icache.total_refs 25687510 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7238 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3548.979000 # Average number of references to valid blocks. +system.cpu.icache.replacements 5445 # number of replacements +system.cpu.icache.tagsinuse 1641.882453 # Cycle average of tags in use +system.cpu.icache.total_refs 25692314 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7414 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3465.378203 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1637.773069 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.799694 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.799694 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25687510 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25687510 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25687510 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25687510 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25687510 # number of overall hits -system.cpu.icache.overall_hits::total 25687510 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8780 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8780 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8780 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8780 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8780 # number of overall misses -system.cpu.icache.overall_misses::total 8780 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 192794500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 192794500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 192794500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 192794500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 192794500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 192794500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25696290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25696290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25696290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25696290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25696290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25696290 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000342 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000342 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000342 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000342 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000342 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000342 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21958.371298 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21958.371298 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21958.371298 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21958.371298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21958.371298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21958.371298 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1641.882453 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.801700 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.801700 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25692314 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25692314 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25692314 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25692314 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25692314 # number of overall hits +system.cpu.icache.overall_hits::total 25692314 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8997 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8997 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8997 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8997 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8997 # number of overall misses +system.cpu.icache.overall_misses::total 8997 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 180939500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 180939500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 180939500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 180939500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 180939500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 180939500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25701311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25701311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25701311 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25701311 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25701311 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25701311 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000350 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000350 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000350 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000350 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000350 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000350 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20111.092586 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20111.092586 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20111.092586 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20111.092586 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20111.092586 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20111.092586 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,94 +346,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1357 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1357 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1357 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1357 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1357 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1357 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7423 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7423 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7423 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7423 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7423 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7423 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 135764500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 135764500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 135764500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 135764500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 135764500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 135764500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000289 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000289 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000289 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18289.707665 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18289.707665 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18289.707665 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18289.707665 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18289.707665 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18289.707665 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1358 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1358 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1358 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1358 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1358 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1358 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7639 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7639 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7639 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7639 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7639 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7639 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 132852000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 132852000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 132852000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 132852000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 132852000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 132852000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000297 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000297 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17391.281581 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17391.281581 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17391.281581 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17391.281581 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17391.281581 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17391.281581 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1420.532831 # Cycle average of tags in use -system.cpu.dcache.total_refs 68760800 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1983 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34675.138679 # Average number of references to valid blocks. +system.cpu.dcache.replacements 56 # number of replacements +system.cpu.dcache.tagsinuse 1423.300553 # Cycle average of tags in use +system.cpu.dcache.total_refs 68703636 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34593.975831 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1420.532831 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.346810 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.346810 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48246578 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48246578 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513979 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513979 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68760557 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68760557 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66966000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95065500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95065500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95065500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95065500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48247389 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48247389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1423.300553 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.347485 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.347485 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48189408 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48189408 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513941 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513941 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68703349 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68703349 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68703349 # number of overall hits +system.cpu.dcache.overall_hits::total 68703349 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 819 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 819 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1789 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1789 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2608 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2608 # 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number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 68763119 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 68763119 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 68763119 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 68763119 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 68705957 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68705957 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68705957 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68705957 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34647.965475 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34647.965475 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38244.431753 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38244.431753 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37105.971897 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37105.971897 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37105.971897 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37105.971897 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000087 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000087 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32180.708181 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32180.708181 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37331.190609 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37331.190609 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35713.765337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35713.765337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35713.765337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35713.765337 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,138 +444,138 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 14 # number of writebacks system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 389 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 389 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 422 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2170 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2170 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2170 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2170 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14825500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14825500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61621000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61621000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 76446500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 76446500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 76446500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 76446500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 394 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 394 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 396 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 396 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 396 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 425 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1787 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1787 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2212 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2212 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2212 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2212 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14781500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14781500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63139500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 63139500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 77921000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 77921000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 77921000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 77921000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000085 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34679.742765 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35147.614892 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35013.860370 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 35099.238767 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35147.614892 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35013.860370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 35099.238767 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -584,58 +584,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3428 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 391 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3819 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 184 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 184 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1557 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1557 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3428 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3438 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 393 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995524 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981360 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.582891 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981360 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.582891 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31947.782964 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33129.156010 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32068.735271 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31297.687861 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31297.687861 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31947.782964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31665.297741 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31845.424107 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31947.782964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31665.297741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31845.424107 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 5386 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109859500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13039500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 122899000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6951000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6951000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48724500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48724500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109859500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61764000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 171623500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109859500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61764000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 171623500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926887 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.488835 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.995556 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.995556 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463780 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.572979 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463780 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.572979 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31954.479348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33179.389313 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32080.135735 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31031.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31334.083601 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31334.083601 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31954.479348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31706.365503 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31864.741924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31954.479348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31706.365503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31864.741924 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 2dc96ffd3..82f566301 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.250981 # Number of seconds simulated -sim_ticks 250980994000 # Number of ticks simulated -final_tick 250980994000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.250954 # Number of seconds simulated +sim_ticks 250953955000 # Number of ticks simulated +final_tick 250953955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 540200 # Simulator instruction rate (inst/s) -host_op_rate 905422 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1026566177 # Simulator tick rate (ticks/s) -host_mem_usage 281300 # Number of bytes of host memory used -host_seconds 244.49 # Real time elapsed on the host +host_inst_rate 366685 # Simulator instruction rate (inst/s) +host_op_rate 614596 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 696753053 # Simulator tick rate (ticks/s) +host_mem_usage 236244 # Number of bytes of host memory used +host_seconds 360.18 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 181760 # Nu system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 724198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 483224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1207422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 724198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 724198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 724198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 483224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1207422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501961988 # number of cpu cycles simulated +system.cpu.numCycles 501907910 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 77165302 # nu system.cpu.num_load_insts 56649586 # Number of load instructions system.cpu.num_store_insts 20515716 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 501961988 # Number of busy cycles +system.cpu.num_busy_cycles 501907910 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.tagsinuse 1455.271959 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1455.296654 # Cycle average of tags in use system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1455.271959 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.710582 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.710582 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1455.296654 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 185042500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 185042500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 185042500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 185042500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 185042500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 185042500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 180319000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 180319000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 180319000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 180319000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 180319000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 173494368 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 173494368 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 173494368 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39421.069450 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39421.069450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39421.069450 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39421.069450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39421.069450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39421.069450 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.784832 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38414.784832 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38414.784832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38414.784832 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170929000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170929000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170929000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170929000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170929000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170929000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170931000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 170931000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170931000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 170931000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170931000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 170931000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.358756 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.358756 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.358756 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.358756 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.358756 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.358756 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.784832 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.784832 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.tagsinuse 1363.439047 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1363.457581 # Cycle average of tags in use system.cpu.dcache.total_refs 77195829 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40522.744882 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.439047 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332871 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332871 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1363.457581 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits @@ -153,14 +153,14 @@ system.cpu.dcache.demand_misses::cpu.data 1905 # n system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses system.cpu.dcache.overall_misses::total 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18020000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18020000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 88243000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 88243000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106263000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106263000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106263000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106263000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) @@ -177,14 +177,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55107.033639 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.785805 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55920.785805 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55781.102362 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55781.102362 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55781.102362 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55781.102362 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,12 +205,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1905 system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83509000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83509000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100547500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 100547500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100547500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 100547500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses @@ -221,26 +221,26 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.785805 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.785805 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.839895 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.839895 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.839895 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.839895 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2058.146468 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2058.178702 # Cycle average of tags in use system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.021788 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1829.948778 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.175901 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1829.978594 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 228.178364 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055846 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.062810 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.062811 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits @@ -265,17 +265,17 @@ system.cpu.l2cache.demand_misses::total 4735 # nu system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147694000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147697000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 164335500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 164338500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 147694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 147697000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 246235500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 147694000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 246238500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 147697000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 246235500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 246238500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5021 # 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number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |