diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref')
24 files changed, 2195 insertions, 2185 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 4aef8f4de..db2911eab 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index 926d51412..b50317767 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:37:18 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 10:35:16 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 42005374000 because target called exit() +122 123 124 Exiting @ tick 42012413000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 60e11bdef..c057cfc04 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.042005 # Number of seconds simulated -sim_ticks 42005374000 # Number of ticks simulated -final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042012 # Number of seconds simulated +sim_ticks 42012413000 # Number of ticks simulated +final_tick 42012413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160903 # Simulator instruction rate (inst/s) -host_op_rate 160903 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73542430 # Simulator tick rate (ticks/s) -host_mem_usage 222752 # Number of bytes of host memory used -host_seconds 571.17 # Real time elapsed on the host +host_inst_rate 107145 # Simulator instruction rate (inst/s) +host_op_rate 107145 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48980163 # Simulator tick rate (ticks/s) +host_mem_usage 222716 # Number of bytes of host memory used +host_seconds 857.74 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4256979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3266630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7523609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4256979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4256979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4256979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3266630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7523609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4256266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3266082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7522348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4256266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4256266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4256266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3266082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7522348 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996214 # DTB read hits +system.cpu.dtb.read_hits 19996215 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996224 # DTB read accesses -system.cpu.dtb.write_hits 6501905 # DTB write hits +system.cpu.dtb.read_accesses 19996225 # DTB read accesses +system.cpu.dtb.write_hits 6501907 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501928 # DTB write accesses -system.cpu.dtb.data_hits 26498119 # DTB hits +system.cpu.dtb.write_accesses 6501930 # DTB write accesses +system.cpu.dtb.data_hits 26498122 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498152 # DTB accesses -system.cpu.itb.fetch_hits 10037351 # ITB hits +system.cpu.dtb.data_accesses 26498155 # DTB accesses +system.cpu.itb.fetch_hits 10034924 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10037400 # ITB accesses +system.cpu.itb.fetch_accesses 10034973 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,42 +60,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 84010749 # number of cpu cycles simulated +system.cpu.numCycles 84024827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 13563923 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9779691 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4496836 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 7950423 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 3848158 # Number of BTB hits +system.cpu.branch_predictor.lookups 13564834 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9782438 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4497092 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7991226 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3849853 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 123 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 48.401928 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 5997418 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7566505 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73742077 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 121 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 48.176000 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5999065 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7565769 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73744929 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136317549 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206798 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136320401 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058686 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38530251 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26765541 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3521133 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 974845 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4495978 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5744724 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.903025 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57471384 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 458266 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38529057 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26768938 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3519911 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 976323 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4496234 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5744468 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.905525 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57470438 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83632403 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83640241 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 11097 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7735993 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76274756 # Number of cycles cpu stages are processed. -system.cpu.activity 90.791663 # Percentage of cycles cpu is active +system.cpu.timesIdled 11659 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7743859 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76280968 # Number of cycles cpu stages are processed. +system.cpu.activity 90.783844 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -107,144 +107,144 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.914124 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.914277 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.914124 # CPI: Total CPI of All Threads -system.cpu.ipc 1.093944 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.914277 # CPI: Total CPI of All Threads +system.cpu.ipc 1.093761 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.093944 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27790213 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56220536 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.920646 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34560671 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49450078 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.861608 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34032650 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49978099 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.490124 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65981194 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029555 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.461010 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30068425 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53942324 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.208836 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 8111 # number of replacements -system.cpu.icache.tagsinuse 1492.322334 # Cycle average of tags in use -system.cpu.icache.total_refs 10025618 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9996 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1002.962985 # Average number of references to valid blocks. +system.cpu.ipc_total 1.093761 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27805541 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56219286 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.907946 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34577681 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49447146 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.848257 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34047365 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49977462 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.479399 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65995198 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029629 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.457502 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30080947 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53943880 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.199930 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 8128 # number of replacements +system.cpu.icache.tagsinuse 1492.257079 # Cycle average of tags in use +system.cpu.icache.total_refs 10023168 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10013 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1001.015480 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.322334 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728673 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728673 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10025618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10025618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10025618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10025618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10025618 # number of overall hits -system.cpu.icache.overall_hits::total 10025618 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11728 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11728 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11728 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11728 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11728 # number of overall misses -system.cpu.icache.overall_misses::total 11728 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 295393500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 295393500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 295393500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 295393500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 295393500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 295393500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 10037346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 10037346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 10037346 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 10037346 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 10037346 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 10037346 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001168 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001168 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001168 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001168 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001168 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001168 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25187.031037 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25187.031037 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25187.031037 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25187.031037 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1492.257079 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728641 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728641 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10023168 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10023168 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10023168 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10023168 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10023168 # number of overall hits +system.cpu.icache.overall_hits::total 10023168 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11752 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11752 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11752 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11752 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11752 # number of overall misses +system.cpu.icache.overall_misses::total 11752 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 302404500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 302404500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 302404500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 302404500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 302404500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 302404500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10034920 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10034920 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10034920 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10034920 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10034920 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10034920 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25732.173247 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25732.173247 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25732.173247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25732.173247 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 97000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 91000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 16166.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 15166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1732 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1732 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1732 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1732 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1732 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1732 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9996 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9996 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9996 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9996 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9996 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9996 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 228898000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 228898000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 228898000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 228898000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228898000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 228898000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000996 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000996 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000996 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22898.959584 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22898.959584 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22898.959584 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22898.959584 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1739 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1739 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1739 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1739 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1739 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1739 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10013 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10013 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10013 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10013 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10013 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10013 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234933000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 234933000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234933000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 234933000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234933000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 234933000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23462.798362 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23462.798362 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.511431 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491208 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.425760 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491190 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.872695 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.864597 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.511431 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351932 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351932 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995646 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995646 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6495562 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6495562 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491208 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491208 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491208 # number of overall hits -system.cpu.dcache.overall_hits::total 26491208 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 552 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 552 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5541 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5541 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6093 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6093 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6093 # number of overall misses -system.cpu.dcache.overall_misses::total 6093 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28391500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28391500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 303790500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 303790500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 332182000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 332182000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 332182000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 332182000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.425760 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351911 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351911 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995640 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995640 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6495550 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495550 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26491190 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491190 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491190 # number of overall hits +system.cpu.dcache.overall_hits::total 26491190 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 558 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 558 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5553 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5553 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6111 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6111 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6111 # number of overall misses +system.cpu.dcache.overall_misses::total 6111 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29911500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29911500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 335932500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 335932500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 365844000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 365844000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 365844000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 365844000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -255,38 +255,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000852 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000230 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51433.876812 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51433.876812 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54825.933947 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54825.933947 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54518.627934 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54518.627934 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000854 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000854 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53604.838710 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53604.838710 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60495.678012 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60495.678012 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59866.470299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59866.470299 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41043500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41291000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49870.595383 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49928.657799 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3793 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3793 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3870 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3870 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3870 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3870 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3805 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3805 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3888 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3888 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3888 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3888 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23216000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23216000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92995500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92995500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116211500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 116211500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116211500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 116211500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24206500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24206500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96919000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 96919000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 121125500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 121125500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 121125500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 121125500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48875.789474 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48875.789474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53201.086957 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53201.086957 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52276.878093 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52276.878093 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50961.052632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50961.052632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55445.652174 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55445.652174 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7269 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2189.621103 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7286 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.214808 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.219988 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.847253 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.879596 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.003621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.844366 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.786741 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 350.989996 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055569 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7202 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.055566 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066822 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7219 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7255 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7272 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7202 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 7219 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7281 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7202 # number of overall hits +system.cpu.l2cache.demand_hits::total 7298 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7219 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 7281 # number of overall hits +system.cpu.l2cache.overall_hits::total 7298 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146177000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22139000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 168316000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90566000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 90566000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 146177000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112705000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 258882000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 146177000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112705000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 258882000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 9996 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149287500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23083500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 172371000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94426500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 94426500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 149287500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 117510000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266797500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 149287500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 117510000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266797500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10013 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 10471 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 10488 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9996 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 10013 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 12219 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9996 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12236 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10013 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 12219 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279512 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 12236 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279037 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.307134 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.306636 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279512 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279037 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.404125 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279512 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.403563 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279037 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.404125 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.181818 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52462.085308 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52337.064677 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52593.495935 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52593.495935 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52426.488457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52426.488457 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.403563 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53431.460272 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54700.236967 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53597.947761 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54835.365854 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54835.365854 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54029.465371 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54029.465371 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112070000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129051000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69345500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69345500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112070000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86326500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 198396500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112070000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86326500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 198396500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115196500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17936000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133132500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73235000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73235000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115196500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91171000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 206367500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115196500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91171000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 206367500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306636 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.404125 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.403563 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.404125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.952040 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40239.336493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40127.798507 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40270.325203 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40270.325203 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40177.501013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40177.501013 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.403563 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41229.957051 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42502.369668 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41396.921642 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42529.036005 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42529.036005 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index d1830cc83..064828e12 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 157ee9690..bbfeb5540 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:41:57 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 10:49:45 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23635060000 because target called exit() +122 123 124 Exiting @ tick 23661066000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 42e01362d..dcc05c5e6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023635 # Number of seconds simulated -sim_ticks 23635060000 # Number of ticks simulated -final_tick 23635060000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023661 # Number of seconds simulated +sim_ticks 23661066000 # Number of ticks simulated +final_tick 23661066000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 242450 # Simulator instruction rate (inst/s) -host_op_rate 242450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68072464 # Simulator tick rate (ticks/s) -host_mem_usage 223772 # Number of bytes of host memory used -host_seconds 347.20 # Real time elapsed on the host +host_inst_rate 163409 # Simulator instruction rate (inst/s) +host_op_rate 163409 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45930776 # Simulator tick rate (ticks/s) +host_mem_usage 223740 # Number of bytes of host memory used +host_seconds 515.15 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 197248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 197312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory system.physmem.bytes_read::total 335744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 197248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 197248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 197312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 197312 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory system.physmem.num_reads::total 5246 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8345568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5859769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14205337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8345568 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8345568 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8345568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5859769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14205337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8339100 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5850624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14189724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8339100 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8339100 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8339100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5850624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14189724 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23228346 # DTB read hits -system.cpu.dtb.read_misses 200425 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 23428771 # DTB read accesses -system.cpu.dtb.write_hits 7078031 # DTB write hits -system.cpu.dtb.write_misses 1393 # DTB write misses -system.cpu.dtb.write_acv 5 # DTB write access violations -system.cpu.dtb.write_accesses 7079424 # DTB write accesses -system.cpu.dtb.data_hits 30306377 # DTB hits -system.cpu.dtb.data_misses 201818 # DTB misses +system.cpu.dtb.read_hits 23226472 # DTB read hits +system.cpu.dtb.read_misses 199471 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 23425943 # DTB read accesses +system.cpu.dtb.write_hits 7079215 # DTB write hits +system.cpu.dtb.write_misses 1341 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 7080556 # DTB write accesses +system.cpu.dtb.data_hits 30305687 # DTB hits +system.cpu.dtb.data_misses 200812 # DTB misses system.cpu.dtb.data_acv 5 # DTB access violations -system.cpu.dtb.data_accesses 30508195 # DTB accesses -system.cpu.itb.fetch_hits 14951144 # ITB hits +system.cpu.dtb.data_accesses 30506499 # DTB accesses +system.cpu.itb.fetch_hits 14950241 # ITB hits system.cpu.itb.fetch_misses 107 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14951251 # ITB accesses +system.cpu.itb.fetch_accesses 14950348 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,146 +60,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47270121 # number of cpu cycles simulated +system.cpu.numCycles 47322133 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15030146 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10897396 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 964237 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8689796 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7074632 # Number of BTB hits +system.cpu.BPredUnit.lookups 15026940 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10894124 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 964629 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8768677 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7072325 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1488592 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3325 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15628273 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128247685 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15030146 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8563224 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22387448 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4637135 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5522059 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1901 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14951144 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 336879 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47178795 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.718333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.372984 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1489344 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3225 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15650036 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128237375 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15026940 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8561669 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22385381 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4637420 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5548184 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2165 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14950241 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 337394 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47225069 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.715451 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.372476 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24791347 52.55% 52.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2391230 5.07% 57.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1207932 2.56% 60.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1776893 3.77% 63.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2805490 5.95% 69.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1170846 2.48% 72.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1228782 2.60% 74.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 789170 1.67% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11017105 23.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24839688 52.60% 52.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2391446 5.06% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1209126 2.56% 60.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1776446 3.76% 63.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2802962 5.94% 69.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1171165 2.48% 72.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1227887 2.60% 75.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 787448 1.67% 76.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11018901 23.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47178795 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317963 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.713081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17466562 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4227162 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20770000 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1087804 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3627267 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2544055 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12184 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125158453 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31894 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3627267 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18628524 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 960250 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8367 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20673426 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3280961 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122187472 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 401237 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2407508 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89717314 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158683253 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148939266 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9743987 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47225069 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317546 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.709882 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17490874 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4250840 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20765641 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090220 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3627494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2542741 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12176 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125152088 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32110 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3627494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18655906 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 966254 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8182 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20668416 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3298817 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122169743 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 401900 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2424267 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89702215 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158657740 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148914395 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9743345 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21289953 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1139 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1148 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8701053 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25559054 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8299979 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2600508 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 916071 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106169681 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2314 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96996119 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 187372 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21529768 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16156839 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1925 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47178795 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.055926 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875880 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21274854 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1091 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8739612 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25558040 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8300974 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2604808 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 921406 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106164029 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2236 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96990974 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 187003 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21520200 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16153199 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1847 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47225069 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.053803 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875376 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12439775 26.37% 26.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9421207 19.97% 46.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8463269 17.94% 64.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6318044 13.39% 77.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4948438 10.49% 88.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2848262 6.04% 94.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1729160 3.67% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 800900 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 209740 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12469931 26.41% 26.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9437048 19.98% 46.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8469534 17.93% 64.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6320288 13.38% 77.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4943441 10.47% 88.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2849790 6.03% 94.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723941 3.65% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801134 1.70% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 209962 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47178795 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47225069 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 186062 11.86% 11.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 228 0.01% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7118 0.45% 12.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5890 0.38% 12.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842932 53.71% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 447788 28.53% 94.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79372 5.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 187127 11.94% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 172 0.01% 11.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7127 0.45% 12.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5609 0.36% 12.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843370 53.79% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445220 28.40% 94.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79228 5.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58995521 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480822 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58991306 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480706 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802067 2.89% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115555 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2385721 2.46% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311403 0.32% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759596 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2802495 2.89% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115483 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386219 2.46% 66.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311493 0.32% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759735 0.78% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued @@ -221,86 +221,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23975443 24.72% 92.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7169665 7.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23972181 24.72% 92.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7171030 7.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96996119 # Type of FU issued -system.cpu.iq.rate 2.051954 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1569390 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016180 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227797779 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118919368 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87372371 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15130016 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8817376 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7067715 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90571077 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7994425 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518936 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96990974 # Type of FU issued +system.cpu.iq.rate 2.049590 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1567853 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016165 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227829224 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118898019 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87368354 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15132649 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8823096 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7068677 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90563080 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7995740 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1518780 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5562856 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19876 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35099 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1798876 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5561842 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19579 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34790 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1799871 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10509 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3627267 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 134249 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17377 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116472912 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 393481 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25559054 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8299979 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2314 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2868 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35099 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 569232 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508759 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1077991 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95699624 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23429474 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1296495 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3627494 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 132338 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17118 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116467170 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 392102 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25558040 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8300974 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2236 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2929 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 49 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34790 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 570155 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508194 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1078349 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95694648 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23426609 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1296326 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10300917 # number of nop insts executed -system.cpu.iew.exec_refs 30509089 # number of memory reference insts executed -system.cpu.iew.exec_branches 12078604 # Number of branches executed -system.cpu.iew.exec_stores 7079615 # Number of stores executed -system.cpu.iew.exec_rate 2.024527 # Inst execution rate -system.cpu.iew.wb_sent 94984897 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94440086 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64627368 # num instructions producing a value -system.cpu.iew.wb_consumers 90016132 # num instructions consuming a value +system.cpu.iew.exec_nop 10300905 # number of nop insts executed +system.cpu.iew.exec_refs 30507339 # number of memory reference insts executed +system.cpu.iew.exec_branches 12077728 # Number of branches executed +system.cpu.iew.exec_stores 7080730 # Number of stores executed +system.cpu.iew.exec_rate 2.022196 # Inst execution rate +system.cpu.iew.wb_sent 94980194 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94437031 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64621172 # num instructions producing a value +system.cpu.iew.wb_consumers 90003030 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.997881 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717953 # average fanout of values written-back +system.cpu.iew.wb_rate 1.995621 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717989 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24570867 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24565165 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 952438 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43551528 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.110214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.736227 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 952869 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43597575 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.107985 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.734489 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17031202 39.11% 39.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9950887 22.85% 61.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4509538 10.35% 72.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2291714 5.26% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1611645 3.70% 81.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1125442 2.58% 83.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722499 1.66% 85.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 819642 1.88% 87.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5488959 12.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17052737 39.11% 39.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9973933 22.88% 61.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4509329 10.34% 72.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2295130 5.26% 77.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1618190 3.71% 81.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1123694 2.58% 83.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722585 1.66% 85.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 817482 1.88% 87.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5484495 12.58% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43551528 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43597575 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -311,70 +311,70 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5488959 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5484495 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154535451 # The number of ROB reads -system.cpu.rob.rob_writes 236599608 # The number of ROB writes +system.cpu.rob.rob_reads 154580260 # The number of ROB reads +system.cpu.rob.rob_writes 236588154 # The number of ROB writes system.cpu.timesIdled 2240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 91326 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 97064 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.561538 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561538 # CPI: Total CPI of All Threads -system.cpu.ipc 1.780823 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.780823 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129477590 # number of integer regfile reads -system.cpu.int_regfile_writes 70782663 # number of integer regfile writes -system.cpu.fp_regfile_reads 6191536 # number of floating regfile reads -system.cpu.fp_regfile_writes 6049328 # number of floating regfile writes -system.cpu.misc_regfile_reads 714291 # number of misc regfile reads +system.cpu.cpi 0.562156 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.562156 # CPI: Total CPI of All Threads +system.cpu.ipc 1.778865 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.778865 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129472042 # number of integer regfile reads +system.cpu.int_regfile_writes 70778136 # number of integer regfile writes +system.cpu.fp_regfile_reads 6192217 # number of floating regfile reads +system.cpu.fp_regfile_writes 6050128 # number of floating regfile writes +system.cpu.misc_regfile_reads 714420 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 10215 # number of replacements -system.cpu.icache.tagsinuse 1600.385722 # Cycle average of tags in use -system.cpu.icache.total_refs 14937616 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12152 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1229.231073 # Average number of references to valid blocks. +system.cpu.icache.replacements 10236 # number of replacements +system.cpu.icache.tagsinuse 1604.355346 # Cycle average of tags in use +system.cpu.icache.total_refs 14936697 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12175 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1226.833429 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1600.385722 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.781438 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.781438 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14937616 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14937616 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14937616 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14937616 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14937616 # number of overall hits -system.cpu.icache.overall_hits::total 14937616 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13528 # number of overall misses -system.cpu.icache.overall_misses::total 13528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 201479500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 201479500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 201479500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 201479500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 201479500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 201479500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14951144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14951144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14951144 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14951144 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14951144 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14951144 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000905 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000905 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000905 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000905 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000905 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000905 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14893.517150 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14893.517150 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14893.517150 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14893.517150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14893.517150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14893.517150 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1604.355346 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.783377 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.783377 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14936697 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14936697 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14936697 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14936697 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14936697 # 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Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2244 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12562.838681 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 1456.192464 # Cycle average of tags in use +system.cpu.dcache.total_refs 28189208 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12567.636202 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1459.321585 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.356280 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.356280 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21697441 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21697441 # 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average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35997.704430 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35997.704430 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35362.226176 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35362.226176 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35362.226176 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35362.226176 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28197810 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28197810 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28197810 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28197810 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001243 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001243 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002146 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002146 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000322 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000322 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000322 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000322 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33242.886179 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33242.886179 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42635.160213 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42635.160213 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41615.859711 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41615.859711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41615.859711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41615.859711 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 380.675363 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.697335 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2024.265560 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 375.671774 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061652 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011617 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073809 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 9070 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.061776 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011465 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073780 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34325.275795 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34672.365989 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34468.452154 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1732 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1732 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12175 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2243 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 14418 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12175 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2243 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 14418 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.253224 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894325 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.279048 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984988 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984988 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.253224 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964333 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.363851 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.253224 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964333 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.363851 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35309.601038 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38040.481400 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35662.146893 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38893.610785 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38893.610785 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35309.601038 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38713.361073 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36713.019443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35309.601038 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38713.361073 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36713.019443 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3082 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 460 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3542 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1704 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1704 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3082 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3083 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 457 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3540 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3083 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 5246 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3082 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3083 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5246 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95761000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14382500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 110143500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53772000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53772000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95761000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68154500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 163915500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95761000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68154500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 163915500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.279646 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984971 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984971 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.364407 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.364407 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31071.057755 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31266.304348 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31096.414455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31556.338028 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31556.338028 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31071.057755 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31494.685767 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31245.806329 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31071.057755 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31494.685767 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31245.806329 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 98880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15955500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 114835500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60925000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60925000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 98880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76880500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 175760500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 98880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76880500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 175760500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.253224 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894325 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.279048 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984988 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984988 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.253224 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.363851 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253224 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.363851 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32072.656503 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34913.566740 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32439.406780 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35712.192263 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35712.192263 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32072.656503 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35543.458160 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33503.717118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32072.656503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35543.458160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33503.717118 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 7fbc3a2c7..218e77206 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout index 0bb9be5b6..86e423df3 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:47:30 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 10:59:12 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 118740049000 because target called exit() +122 123 124 Exiting @ tick 118779533000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index b947ca514..d3e99f110 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.118740 # Number of seconds simulated -sim_ticks 118740049000 # Number of ticks simulated -final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.118780 # Number of seconds simulated +sim_ticks 118779533000 # Number of ticks simulated +final_tick 118779533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2205371 # Simulator instruction rate (inst/s) -host_op_rate 2205370 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2849367775 # Simulator tick rate (ticks/s) -host_mem_usage 222752 # Number of bytes of host memory used -host_seconds 41.67 # Real time elapsed on the host +host_inst_rate 1503058 # Simulator instruction rate (inst/s) +host_op_rate 1503057 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1942616372 # Simulator tick rate (ticks/s) +host_mem_usage 222720 # Number of bytes of host memory used +host_seconds 61.14 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 167744 # Nu system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2568299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2568299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1412230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2567446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412230 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412230 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2567446 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237480098 # number of cpu cycles simulated +system.cpu.numCycles 237559066 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237480098 # Number of busy cycles +system.cpu.num_busy_cycles 237559066 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 6681 # number of replacements -system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1417.992791 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1418.037996 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.692401 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.692401 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1417.992791 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.692379 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.692379 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 229222000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 229222000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 229222000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 229222000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 229222000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 229222000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 229226000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 229226000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 229226000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 229226000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 229226000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 229226000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26935.605170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26935.605170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26935.605170 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26936.075206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26936.075206 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26936.075206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26936.075206 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203696000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 203696000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203696000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 203696000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203696000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 203696000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23936.075206 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23936.075206 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.982871 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1442.028823 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352058 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352058 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1441.982871 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352047 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352047 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 2223 # n system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24374000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24380000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24380000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 96796000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 96796000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121170000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121170000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121170000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121170000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121176000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121176000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121176000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121176000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51313.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51326.315789 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51326.315789 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54510.121457 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54510.121457 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22955000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22955000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114507000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114507000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114507000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114507000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48326.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48326.315789 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2073.981313 # Cycle average of tags in use system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.795183 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1704.999565 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.253845 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.795350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1704.943449 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.242515 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052032 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052031 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.063295 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.063293 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index bf679d420..3f37afa6e 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -497,7 +497,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -529,7 +529,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 6b424cab1..e4047fa1c 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:29:26 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 16:47:08 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -21,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 76049800000 because target called exit() +122 123 124 Exiting @ tick 76017712000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a9dc709bb..5df5997a1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.076050 # Number of seconds simulated -sim_ticks 76049800000 # Number of ticks simulated -final_tick 76049800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.076018 # Number of seconds simulated +sim_ticks 76017712000 # Number of ticks simulated +final_tick 76017712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156056 # Simulator instruction rate (inst/s) -host_op_rate 170865 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68866655 # Simulator tick rate (ticks/s) -host_mem_usage 238096 # Number of bytes of host memory used -host_seconds 1104.31 # Real time elapsed on the host -sim_insts 172333196 # Number of instructions simulated -sim_ops 188686678 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 132416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112128 # Number of bytes read from this memory -system.physmem.bytes_read::total 244544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 132416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 132416 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1752 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3821 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1741175 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1474402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3215577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1741175 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1741175 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1741175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1474402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3215577 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 156722 # Simulator instruction rate (inst/s) +host_op_rate 171594 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69131199 # Simulator tick rate (ticks/s) +host_mem_usage 238024 # Number of bytes of host memory used +host_seconds 1099.62 # Real time elapsed on the host +sim_insts 172333351 # Number of instructions simulated +sim_ops 188686833 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 131968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory +system.physmem.bytes_read::total 244160 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3815 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1736016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1475867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3211883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1736016 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1736016 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1736016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1475867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3211883 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,323 +70,323 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 152099601 # number of cpu cycles simulated +system.cpu.numCycles 152035425 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 96837963 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76071776 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6557528 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46441082 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44202196 # Number of BTB hits +system.cpu.BPredUnit.lookups 96736502 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 76001405 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6554044 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46407824 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44181263 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4477911 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 89401 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40623947 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 388565051 # Number of instructions fetch has processed -system.cpu.fetch.Branches 96837963 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48680107 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82289244 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28490098 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7220589 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8612 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4475583 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 89477 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40615724 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 388321121 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96736502 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48656846 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 82257766 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28468285 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7213696 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8844 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 37659031 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1889609 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 152039589 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.799223 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.154384 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37645633 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1886253 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 151974828 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.798620 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.154172 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69920012 45.99% 45.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5487559 3.61% 49.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10685692 7.03% 56.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10438123 6.87% 63.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8795207 5.78% 69.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6832085 4.49% 73.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6301825 4.14% 77.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8365502 5.50% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25213584 16.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69887899 45.99% 45.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5501348 3.62% 49.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10684945 7.03% 56.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10435662 6.87% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8784636 5.78% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6836908 4.50% 73.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6295744 4.14% 77.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8337493 5.49% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25210193 16.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152039589 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.636675 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.554675 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46670430 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5932664 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76574160 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1118361 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21743974 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14821262 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162795 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401681988 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 736800 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21743974 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52193760 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 715909 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 791714 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72108942 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4485290 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 379159906 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 316677 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3600241 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 642535255 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1615137204 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1597539210 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17597994 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092419 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 344442836 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 52681 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 52677 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12879836 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 44010443 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16892323 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5849879 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3738879 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 334925831 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 74527 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 252866200 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 897062 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 145077714 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 374156671 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 23276 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152039589 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.663160 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.758894 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151974828 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.636276 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.554149 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46658969 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5920762 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76552571 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1116980 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21725546 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14796577 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162492 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401466473 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 736417 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21725546 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52184597 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 714677 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 792157 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72083528 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4474323 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 378974639 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 320673 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3580560 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 14 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 642268895 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1614410837 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1596806412 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17604425 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092667 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 344176228 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 52668 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 52665 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12854506 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43974668 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16894662 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5833133 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3767851 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334792286 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 74530 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 252791404 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 896561 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 144952187 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 373840168 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 23248 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151974828 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.663377 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.758905 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58521655 38.49% 38.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23034636 15.15% 53.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25191735 16.57% 70.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20480082 13.47% 83.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12877411 8.47% 92.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6577788 4.33% 96.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4065173 2.67% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1110646 0.73% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 180463 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58489364 38.49% 38.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23011540 15.14% 53.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25193746 16.58% 70.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20486028 13.48% 83.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12864515 8.46% 92.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6577319 4.33% 96.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4059001 2.67% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1110893 0.73% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182422 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152039589 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151974828 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 967418 37.56% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5599 0.22% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 146 0.01% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 21 0.00% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1198100 46.52% 84.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 404230 15.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 966666 37.58% 37.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5596 0.22% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 136 0.01% 37.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 25 0.00% 37.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1199658 46.64% 84.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 400010 15.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197377765 78.06% 78.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 996285 0.39% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33143 0.01% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164246 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255557 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76455 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467877 0.19% 78.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206463 0.08% 78.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39025783 15.43% 94.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14190441 5.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 197331718 78.06% 78.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 995910 0.39% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33152 0.01% 78.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164284 0.06% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255235 0.10% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76457 0.03% 78.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467994 0.19% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206483 0.08% 78.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71867 0.03% 78.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38997717 15.43% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14190267 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 252866200 # Type of FU issued -system.cpu.iq.rate 1.662504 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2575514 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010185 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 657470724 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 477849498 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240611060 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3773841 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2247636 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1852910 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253547208 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1894506 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2021626 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 252791404 # Type of FU issued +system.cpu.iq.rate 1.662714 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2572091 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010175 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 657257029 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477588320 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 240562315 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3769259 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2249868 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1852626 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253473620 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1889875 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2022881 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14154924 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16760 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19840 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4241654 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14119118 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17181 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19942 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4243962 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21743974 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13418 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 622 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 335058586 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 832362 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 44010443 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16892323 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51985 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 162 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 263 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19840 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4108839 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3946041 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8054880 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 245860683 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37402341 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7005517 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21725546 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 15871 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 654 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334925114 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 838955 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43974668 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16894662 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51980 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19942 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4105078 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3945464 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8050542 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 245797206 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37379001 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6994198 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 58228 # number of nop insts executed -system.cpu.iew.exec_refs 51211338 # number of memory reference insts executed -system.cpu.iew.exec_branches 54022808 # Number of branches executed -system.cpu.iew.exec_stores 13808997 # Number of stores executed -system.cpu.iew.exec_rate 1.616445 # Inst execution rate -system.cpu.iew.wb_sent 243598204 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242463970 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150083518 # num instructions producing a value -system.cpu.iew.wb_consumers 269173561 # num instructions consuming a value +system.cpu.iew.exec_nop 58298 # number of nop insts executed +system.cpu.iew.exec_refs 51189045 # number of memory reference insts executed +system.cpu.iew.exec_branches 54004994 # Number of branches executed +system.cpu.iew.exec_stores 13810044 # Number of stores executed +system.cpu.iew.exec_rate 1.616710 # Inst execution rate +system.cpu.iew.wb_sent 243546363 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 242414941 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150055684 # num instructions producing a value +system.cpu.iew.wb_consumers 269132262 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.594113 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557572 # average fanout of values written-back +system.cpu.iew.wb_rate 1.594464 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557554 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 172347584 # The number of committed instructions -system.cpu.commit.commitCommittedOps 188701066 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 146357504 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51251 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6423604 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130295616 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.448253 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.160604 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 172347739 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188701221 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 146223871 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51282 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6420079 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130249283 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.448770 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.161298 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 60033353 46.07% 46.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32093498 24.63% 70.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14006031 10.75% 81.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7653781 5.87% 87.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4421161 3.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1332201 1.02% 91.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1737103 1.33% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1282008 0.98% 94.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7736480 5.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 60006705 46.07% 46.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 32087583 24.64% 70.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13984606 10.74% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7660285 5.88% 87.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4414959 3.39% 90.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1331514 1.02% 91.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1740633 1.34% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1281617 0.98% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7741381 5.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130295616 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347584 # Number of instructions committed -system.cpu.commit.committedOps 188701066 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130249283 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347739 # Number of instructions committed +system.cpu.commit.committedOps 188701221 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506188 # Number of memory references committed -system.cpu.commit.loads 29855519 # Number of loads committed +system.cpu.commit.refs 42506250 # Number of memory references committed +system.cpu.commit.loads 29855550 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40287717 # Number of branches committed +system.cpu.commit.branches 40287748 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130357 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130481 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7736480 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7741381 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457612505 # The number of ROB reads -system.cpu.rob.rob_writes 691979598 # The number of ROB writes -system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 60012 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333196 # Number of Instructions Simulated -system.cpu.committedOps 188686678 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333196 # Number of Instructions Simulated -system.cpu.cpi 0.882590 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.882590 # CPI: Total CPI of All Threads -system.cpu.ipc 1.133029 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.133029 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092071141 # number of integer regfile reads -system.cpu.int_regfile_writes 388656879 # number of integer regfile writes -system.cpu.fp_regfile_reads 2914235 # number of floating regfile reads -system.cpu.fp_regfile_writes 2512527 # number of floating regfile writes -system.cpu.misc_regfile_reads 474801777 # number of misc regfile reads -system.cpu.misc_regfile_writes 832106 # number of misc regfile writes -system.cpu.icache.replacements 2596 # number of replacements -system.cpu.icache.tagsinuse 1365.085421 # Cycle average of tags in use -system.cpu.icache.total_refs 37653918 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8680.017981 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 457427793 # The number of ROB reads +system.cpu.rob.rob_writes 691694403 # The number of ROB writes +system.cpu.timesIdled 1790 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60597 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333351 # Number of Instructions Simulated +system.cpu.committedOps 188686833 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333351 # Number of Instructions Simulated +system.cpu.cpi 0.882217 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.882217 # CPI: Total CPI of All Threads +system.cpu.ipc 1.133508 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.133508 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1091781968 # number of integer regfile reads +system.cpu.int_regfile_writes 388588148 # number of integer regfile writes +system.cpu.fp_regfile_reads 2914249 # number of floating regfile reads +system.cpu.fp_regfile_writes 2512479 # number of floating regfile writes +system.cpu.misc_regfile_reads 474590594 # number of misc regfile reads +system.cpu.misc_regfile_writes 832168 # number of misc regfile writes +system.cpu.icache.replacements 2661 # number of replacements +system.cpu.icache.tagsinuse 1361.223505 # Cycle average of tags in use +system.cpu.icache.total_refs 37640447 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4399 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8556.591725 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1365.085421 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.666546 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.666546 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37653921 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37653921 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37653921 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37653921 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37653921 # number of overall hits -system.cpu.icache.overall_hits::total 37653921 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5110 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5110 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5110 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5110 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5110 # number of overall misses -system.cpu.icache.overall_misses::total 5110 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 111334000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 111334000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 111334000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 111334000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 111334000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 111334000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37659031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37659031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37659031 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37659031 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37659031 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37659031 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000136 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22078.384111 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22078.384111 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22078.384111 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,110 +395,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 768 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 768 # 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Cycle average of tags in use +system.cpu.dcache.total_refs 47292959 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25371.759120 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1413.439257 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.345078 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.345078 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34901837 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34901837 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356702 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356702 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 29806 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 29806 # 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miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32324.608743 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32324.608743 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31300.593276 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31300.593276 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31501.642297 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31501.642297 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31501.642297 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31501.642297 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000203 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000203 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36739.545689 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36739.545689 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37030.390359 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37030.390359 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 40250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 40250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36971.528576 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36971.528576 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36971.528576 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36971.528576 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 10000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,138 +507,134 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 18 # number of writebacks -system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1071 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1071 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6498 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6498 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1154 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1154 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6553 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6553 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7569 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7569 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4400 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1864 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6264 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4400 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1864 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6264 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.470000 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.885057 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.532703 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993525 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.993525 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.470000 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.947961 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.612229 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.470000 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.947961 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.612229 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35215.667311 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36657.287157 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35577.508149 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34803.072626 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34803.072626 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35215.667311 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35530.277306 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 35360.625815 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35215.667311 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35530.277306 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 35360.625815 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -647,59 +643,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2069 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 677 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2746 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2069 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1752 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3821 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2069 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1752 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3821 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64256500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21124000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85380500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33377000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33377000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64256500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54501000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 118757500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64256500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54501000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 118757500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866837 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.536223 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991697 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991697 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939410 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.615794 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939410 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.615794 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.790720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31202.363368 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31092.680262 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31048.372093 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31048.372093 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.790720 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31107.876712 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31080.214604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.790720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31107.876712 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31080.214604 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 20 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2062 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 679 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2741 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1074 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1074 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2062 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3815 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2062 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3815 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66124000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22800500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 88924500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33930000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33930000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66124000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 56730500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 122854500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66124000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 56730500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 122854500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867178 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.528844 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993525 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993525 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940451 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.609036 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940451 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.609036 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32067.895247 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33579.528719 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32442.356804 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31592.178771 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31592.178771 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32067.895247 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32361.950941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32203.014417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32067.895247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32361.950941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32203.014417 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index 7a871da2f..e101e797a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index 0e8fdda90..fe3f7fc4c 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:30:46 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 17:03:03 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing/smred.sav +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -21,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 232077144000 because target called exit() +122 123 124 Exiting @ tick 232089948000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 4c3bb52b8..709a3b23f 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232077 # Number of seconds simulated -sim_ticks 232077144000 # Number of ticks simulated -final_tick 232077144000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.232090 # Number of seconds simulated +sim_ticks 232089948000 # Number of ticks simulated +final_tick 232089948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1482014 # Simulator instruction rate (inst/s) -host_op_rate 1622964 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2001492603 # Simulator tick rate (ticks/s) -host_mem_usage 236052 # Number of bytes of host memory used -host_seconds 115.95 # Real time elapsed on the host +host_inst_rate 1678684 # Simulator instruction rate (inst/s) +host_op_rate 1838338 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2267224735 # Simulator tick rate (ticks/s) +host_mem_usage 235976 # Number of bytes of host memory used +host_seconds 102.37 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 188185920 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 110656 # Nu system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 476807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 475428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 952235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 476807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 476807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 476807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 475428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 952235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 476781 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 475402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 952183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 476781 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 476781 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 476781 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 475402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 952183 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 464154288 # number of cpu cycles simulated +system.cpu.numCycles 464179896 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842483 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 42494119 # nu system.cpu.num_load_insts 29849484 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 464154288 # Number of busy cycles +system.cpu.num_busy_cycles 464179896 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1506 # number of replacements -system.cpu.icache.tagsinuse 1147.981203 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1147.971530 # Cycle average of tags in use system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1147.981203 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.560538 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.560538 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1147.971530 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.560533 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.560533 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits @@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 40 # number of replacements -system.cpu.dcache.tagsinuse 1363.604373 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1363.590777 # Cycle average of tags in use system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.604373 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332911 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332911 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1363.590777 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332908 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332908 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits @@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 1789 # n system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36190000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36190000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36195000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36195000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 61264000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 61264000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 97454000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 97454000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 97454000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 97454000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 97459000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 97459000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 97459000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 97459000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52525.399129 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52525.399129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52532.656023 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52532.656023 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55694.545455 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54474.007826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54474.007826 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54476.802683 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54476.802683 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54476.802683 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54476.802683 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1789 system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34128000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34128000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92092000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92092000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92092000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92092000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49532.656023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49532.656023 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51476.802683 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51476.802683 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51476.802683 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51476.802683 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1675.648101 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 1675.633213 # Cycle average of tags in use system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3.038048 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1169.027783 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 503.582269 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 3.038052 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1169.018140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 503.577021 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.051136 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index 35d8a380c..fd32216ef 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout index 8467606a8..123985114 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 15:02:43 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 12:35:14 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 info: Increasing stack size by one page. -122 123 124 Exiting @ tick 270576960000 because target called exit() +122 123 124 Exiting @ tick 270628681000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 170992582..23f251d47 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.270577 # Number of seconds simulated -sim_ticks 270576960000 # Number of ticks simulated -final_tick 270576960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.270629 # Number of seconds simulated +sim_ticks 270628681000 # Number of ticks simulated +final_tick 270628681000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1394951 # Simulator instruction rate (inst/s) -host_op_rate 1394952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1951161352 # Simulator tick rate (ticks/s) -host_mem_usage 227304 # Number of bytes of host memory used -host_seconds 138.67 # Real time elapsed on the host +host_inst_rate 1015199 # Simulator instruction rate (inst/s) +host_op_rate 1015200 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1420261450 # Simulator tick rate (ticks/s) +host_mem_usage 225612 # Number of bytes of host memory used +host_seconds 190.55 # Real time elapsed on the host sim_insts 193444531 # Number of instructions simulated sim_ops 193444769 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 230208 # Nu system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 850804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 372774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1223578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 850804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 850804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 850804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 372774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1223578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 850642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223344 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541153920 # number of cpu cycles simulated +system.cpu.numCycles 541257362 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444531 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 76733959 # nu system.cpu.num_load_insts 57735092 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 541153920 # Number of busy cycles +system.cpu.num_busy_cycles 541257362 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10362 # number of replacements -system.cpu.icache.tagsinuse 1591.571713 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.549936 # Cycle average of tags in use system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1591.571713 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777135 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777135 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1591.549936 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777124 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777124 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 193433261 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433261 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433261 # number of demand (read+write) hits @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2 # number of replacements -system.cpu.dcache.tagsinuse 1237.197455 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.179086 # Cycle average of tags in use system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1237.197455 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.302050 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.302050 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1237.179086 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.302046 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.302046 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 57734571 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734571 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits @@ -249,18 +249,18 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2678.289467 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.000454 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2275.271466 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 403.055215 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2275.240506 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 403.048505 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.069435 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.081735 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 24899e6d1..c72ea59c4 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -532,7 +532,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 34329ed9e..6f015db37 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:08:09 -gem5 started Jun 29 2012 00:01:11 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 14:16:35 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -22,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 87734048000 because target called exit() +122 123 124 Exiting @ tick 87870590500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 963d9307c..d6435aa8f 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.087734 # Number of seconds simulated -sim_ticks 87734048000 # Number of ticks simulated -final_tick 87734048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.087871 # Number of seconds simulated +sim_ticks 87870590500 # Number of ticks simulated +final_tick 87870590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104988 # Simulator instruction rate (inst/s) -host_op_rate 175969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69742772 # Simulator tick rate (ticks/s) -host_mem_usage 239080 # Number of bytes of host memory used -host_seconds 1257.97 # Real time elapsed on the host +host_inst_rate 71260 # Simulator instruction rate (inst/s) +host_op_rate 119437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47410913 # Simulator tick rate (ticks/s) +host_mem_usage 239040 # Number of bytes of host memory used +host_seconds 1853.38 # Real time elapsed on the host sim_insts 132071227 # Number of instructions simulated sim_ops 221363017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory -system.physmem.bytes_read::total 345024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219520 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3430 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5391 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2502107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1430505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3932612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2502107 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2502107 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2502107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1430505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3932612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 219328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125312 # Number of bytes read from this memory +system.physmem.bytes_read::total 344640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219328 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3427 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1958 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5385 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2496034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1426097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3922131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2496034 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2496034 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2496034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1426097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3922131 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 175468097 # number of cpu cycles simulated +system.cpu.numCycles 175741182 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20936810 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20936810 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2209025 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15519452 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13863485 # Number of BTB hits +system.cpu.BPredUnit.lookups 20899544 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20899544 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2209301 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15564510 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13831117 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27317448 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 226954156 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20936810 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13863485 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59860939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19465594 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 71226359 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7164 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25821692 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 473022 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 175391237 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.137569 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.300907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27321618 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227238507 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20899544 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13831117 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59893533 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19501221 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71423982 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 856 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5992 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25806035 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 465205 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 175660343 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.136482 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.300848 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 117206877 66.83% 66.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3231358 1.84% 68.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2482815 1.42% 70.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3136542 1.79% 71.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3542923 2.02% 73.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3767949 2.15% 76.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4531829 2.58% 78.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2825666 1.61% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34665278 19.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 117444586 66.86% 66.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3198914 1.82% 68.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2491940 1.42% 70.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3160979 1.80% 71.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3538324 2.01% 73.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3753773 2.14% 76.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4538217 2.58% 78.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2790941 1.59% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34742669 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 175391237 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119320 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.293421 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40660130 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 61009372 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46541390 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10201855 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16978490 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 366073396 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16978490 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48547252 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16251189 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23056 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48155491 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45435759 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 356858942 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 175660343 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.118922 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.293029 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40683921 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 61195549 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46567945 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10198566 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17014362 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 366345235 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17014362 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48576080 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16382165 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23120 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48162732 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45501884 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 357078991 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20674050 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22523448 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2249 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 506627728 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1130775437 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1120479419 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10296018 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 20682611 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22563031 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 2159 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 507023115 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1130829367 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1120559538 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10269829 # Number of floating rename lookups system.cpu.rename.CommittedMaps 320143989 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 186483739 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1903 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1897 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 95061023 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89836107 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 33126554 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59108509 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19466725 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344545895 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7937 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 270906839 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 256776 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122697293 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 297019638 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6691 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 175391237 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.544586 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.467556 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 186879126 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1752 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1748 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95224460 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89733433 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 33126423 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59021419 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19494501 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344814343 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7981 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271092174 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 252461 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122957683 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 297045432 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6735 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 175660343 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.543275 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.467777 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 49119269 28.01% 28.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 52565616 29.97% 57.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34331484 19.57% 77.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18982131 10.82% 88.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12721464 7.25% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4942775 2.82% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2076613 1.18% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 542627 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 109258 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 49300631 28.07% 28.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 52565821 29.92% 57.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34438082 19.60% 77.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18985110 10.81% 88.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12671961 7.21% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4951895 2.82% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2092177 1.19% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 542850 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 111816 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 175391237 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 175660343 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 90563 3.50% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90987 3.50% 3.50% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.50% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.50% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.50% # attempts to use FU when none available @@ -153,120 +153,120 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.50% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.50% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.50% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2225289 85.92% 89.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 273998 10.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2226720 85.76% 89.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 278883 10.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212985 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 176266302 65.07% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1595268 0.59% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68329319 25.22% 91.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23502965 8.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212971 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 176440740 65.09% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1591628 0.59% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68336239 25.21% 91.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23510596 8.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 270906839 # Type of FU issued -system.cpu.iq.rate 1.543909 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2589850 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009560 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 714739567 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 462675137 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 263287653 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5311974 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4876750 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2553148 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 269622080 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2661624 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18915593 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271092174 # Type of FU issued +system.cpu.iq.rate 1.542565 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2596590 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009578 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 715388458 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 463212218 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 263468773 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5305284 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4868318 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2548590 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 269817574 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2658219 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18900853 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33186517 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30708 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 305892 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12610838 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33083843 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 30126 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 305710 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12610707 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 47515 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 47697 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16978490 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 517280 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 233874 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 344553832 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 297077 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89836107 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 33126554 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1857 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 147591 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 33364 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 305892 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1298592 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1028927 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2327519 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 267790575 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67240366 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3116264 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17014362 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 531971 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 245364 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344822324 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 299116 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89733433 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 33126423 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1715 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 158423 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 34384 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 305710 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1300553 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1025953 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2326506 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 267978293 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67258020 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3113881 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90351837 # number of memory reference insts executed -system.cpu.iew.exec_branches 14775060 # Number of branches executed -system.cpu.iew.exec_stores 23111471 # Number of stores executed -system.cpu.iew.exec_rate 1.526150 # Inst execution rate -system.cpu.iew.wb_sent 266714598 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 265840801 # cumulative count of insts written-back -system.cpu.iew.wb_producers 214478617 # num instructions producing a value -system.cpu.iew.wb_consumers 504376698 # num instructions consuming a value +system.cpu.iew.exec_refs 90379162 # number of memory reference insts executed +system.cpu.iew.exec_branches 14791945 # Number of branches executed +system.cpu.iew.exec_stores 23121142 # Number of stores executed +system.cpu.iew.exec_rate 1.524846 # Inst execution rate +system.cpu.iew.wb_sent 266905236 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 266017363 # cumulative count of insts written-back +system.cpu.iew.wb_producers 214552655 # num instructions producing a value +system.cpu.iew.wb_consumers 504482299 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.515038 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.425235 # average fanout of values written-back +system.cpu.iew.wb_rate 1.513688 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.425293 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 123301880 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 123572958 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2209791 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158412747 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.397381 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.795092 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2210019 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158645981 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.395327 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.792270 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 54206628 34.22% 34.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 60400758 38.13% 72.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15586261 9.84% 82.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12707072 8.02% 90.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4534557 2.86% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2957745 1.87% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2082808 1.31% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1250624 0.79% 97.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4686294 2.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 54337756 34.25% 34.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 60487783 38.13% 72.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15594396 9.83% 82.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12721179 8.02% 90.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4547355 2.87% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2966330 1.87% 94.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2094139 1.32% 96.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1239343 0.78% 97.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4657700 2.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158412747 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158645981 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071227 # Number of instructions committed system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -277,70 +277,70 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4686294 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4657700 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 498391350 # The number of ROB reads -system.cpu.rob.rob_writes 706346628 # The number of ROB writes -system.cpu.timesIdled 1678 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76860 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 498924256 # The number of ROB reads +system.cpu.rob.rob_writes 706924128 # The number of ROB writes +system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 80839 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071227 # Number of Instructions Simulated system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated -system.cpu.cpi 1.328587 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.328587 # CPI: Total CPI of All Threads -system.cpu.ipc 0.752679 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.752679 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 657568441 # number of integer regfile reads -system.cpu.int_regfile_writes 365395599 # number of integer regfile writes -system.cpu.fp_regfile_reads 3514318 # number of floating regfile reads -system.cpu.fp_regfile_writes 2225520 # number of floating regfile writes -system.cpu.misc_regfile_reads 139440665 # number of misc regfile reads +system.cpu.cpi 1.330655 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.330655 # CPI: Total CPI of All Threads +system.cpu.ipc 0.751510 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.751510 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 657690172 # number of integer regfile reads +system.cpu.int_regfile_writes 365563414 # number of integer regfile writes +system.cpu.fp_regfile_reads 3506965 # number of floating regfile reads +system.cpu.fp_regfile_writes 2222676 # number of floating regfile writes +system.cpu.misc_regfile_reads 139526646 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5526 # number of replacements -system.cpu.icache.tagsinuse 1631.257386 # Cycle average of tags in use -system.cpu.icache.total_refs 25812694 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7496 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3443.529082 # Average number of references to valid blocks. +system.cpu.icache.replacements 5610 # number of replacements +system.cpu.icache.tagsinuse 1629.478377 # Cycle average of tags in use +system.cpu.icache.total_refs 25796956 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7578 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3404.190552 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1631.257386 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.796512 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.796512 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25812694 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25812694 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25812694 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25812694 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25812694 # number of overall hits -system.cpu.icache.overall_hits::total 25812694 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8998 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8998 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8998 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8998 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8998 # number of overall misses -system.cpu.icache.overall_misses::total 8998 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186818500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186818500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186818500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186818500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186818500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186818500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25821692 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25821692 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25821692 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25821692 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25821692 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25821692 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000348 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000348 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000348 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000348 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000348 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000348 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20762.224939 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20762.224939 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20762.224939 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20762.224939 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20762.224939 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20762.224939 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1629.478377 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.795644 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.795644 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25796956 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25796956 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25796956 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25796956 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25796956 # number of overall hits +system.cpu.icache.overall_hits::total 25796956 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9079 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9079 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9079 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9079 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9079 # number of overall misses +system.cpu.icache.overall_misses::total 9079 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 194493000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 194493000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 194493000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 194493000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 194493000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 194493000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25806035 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25806035 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25806035 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25806035 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25806035 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25806035 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000352 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000352 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21422.293204 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21422.293204 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21422.293204 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21422.293204 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21422.293204 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21422.293204 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,78 +349,78 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1359 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1359 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1359 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1359 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1359 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1359 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7639 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7639 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7639 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7639 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7639 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7639 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130438500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 130438500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130438500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 130438500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130438500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 130438500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000296 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000296 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000296 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000296 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000296 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000296 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17075.337086 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17075.337086 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17075.337086 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17075.337086 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17075.337086 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17075.337086 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1363 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1363 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1363 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1363 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1363 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1363 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7716 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7716 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7716 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7716 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7716 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7716 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 136466500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 136466500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 136466500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 136466500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 136466500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 136466500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17686.171591 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17686.171591 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17686.171591 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17686.171591 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17686.171591 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17686.171591 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1425.887115 # Cycle average of tags in use -system.cpu.dcache.total_refs 68669194 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1998 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34368.965966 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 1427.277065 # Cycle average of tags in use +system.cpu.dcache.total_refs 68700923 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1995 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34436.552882 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1425.887115 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.348117 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.348117 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48154983 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48154983 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514026 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514026 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68669009 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68669009 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68669009 # number of overall hits -system.cpu.dcache.overall_hits::total 68669009 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 768 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 768 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1704 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1704 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2472 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2472 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2472 # number of overall misses -system.cpu.dcache.overall_misses::total 2472 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24800000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24800000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64672500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64672500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89472500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89472500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89472500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89472500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48155751 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48155751 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1427.277065 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.348456 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.348456 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48186723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48186723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514032 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514032 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68700755 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68700755 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68700755 # number of overall hits +system.cpu.dcache.overall_hits::total 68700755 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1698 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1698 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2449 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2449 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2449 # number of overall misses +system.cpu.dcache.overall_misses::total 2449 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26925000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26925000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64818000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64818000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91743000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91743000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91743000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91743000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48187474 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48187474 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 68671481 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 68671481 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 68671481 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 68671481 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 68703204 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68703204 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68703204 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68703204 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses @@ -429,14 +429,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 system.cpu.dcache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32291.666667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32291.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37953.345070 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37953.345070 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36194.377023 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36194.377023 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36194.377023 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36194.377023 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35852.197071 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35852.197071 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38173.144876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38173.144876 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37461.412822 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37461.412822 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37461.412822 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37461.412822 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,32 +445,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 14 # number of writebacks -system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 326 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 326 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 442 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 442 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2143 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2143 # 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average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35126.057776 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34790.347293 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 35003.992572 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35126.057776 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34790.347293 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 35003.992572 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -585,58 +585,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3430 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 410 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3840 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 143 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 143 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1551 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3430 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5391 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3430 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5391 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106414500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12709500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119124000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4433000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4433000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106414500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60820000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 167234500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106414500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60820000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 167234500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929705 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.483810 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3427 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 409 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3836 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 138 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 138 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1549 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1549 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3427 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5385 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3427 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5385 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109445000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13559500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 123004500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4278000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4278000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48463000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48463000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109445000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 62022500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 171467500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109445000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 62022500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 171467500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.452230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.478424 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994869 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.567713 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.567713 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31024.635569 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30998.780488 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31021.875000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994862 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994862 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.452230 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980471 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.562402 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.452230 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980471 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.562402 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31936.095711 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33152.811736 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32065.823775 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31024.635569 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.788373 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31021.053608 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31024.635569 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.788373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31021.053608 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31286.636540 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31286.636540 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31936.095711 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31676.455567 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31841.689879 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31936.095711 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31676.455567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31841.689879 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 168d19d0f..1ebce5cb8 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -169,7 +169,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -201,7 +201,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index c17116a39..2dfefd0be 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:08:09 -gem5 started Jun 29 2012 00:23:42 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 14:50:18 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -22,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 250960631000 because target called exit() +122 123 124 Exiting @ tick 250981042000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 8e544f41c..f0166c804 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.250961 # Number of seconds simulated -sim_ticks 250960631000 # Number of ticks simulated -final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.250981 # Number of seconds simulated +sim_ticks 250981042000 # Number of ticks simulated +final_tick 250981042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1047161 # Simulator instruction rate (inst/s) -host_op_rate 1755134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1989805633 # Simulator tick rate (ticks/s) -host_mem_usage 234988 # Number of bytes of host memory used -host_seconds 126.12 # Real time elapsed on the host +host_inst_rate 522050 # Simulator instruction rate (inst/s) +host_op_rate 875003 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 992076486 # Simulator tick rate (ticks/s) +host_mem_usage 235972 # Number of bytes of host memory used +host_seconds 252.99 # Real time elapsed on the host sim_insts 132071228 # Number of instructions simulated sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 181760 # Nu system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 724257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 483263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1207520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 724257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 724257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 724257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 483263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1207520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 724198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 483224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1207422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 724198 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 724198 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 724198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 483224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1207422 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501921262 # number of cpu cycles simulated +system.cpu.numCycles 501962084 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071228 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 77165306 # nu system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_store_insts 20515716 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 501921262 # Number of busy cycles +system.cpu.num_busy_cycles 501962084 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1455.271683 # Cycle average of tags in use system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1455.289108 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.710590 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.710590 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1455.271683 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.710582 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.710582 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 173489718 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489718 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489718 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 185041500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 185041500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 185041500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 185041500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 185041500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 185041500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 185042500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 185042500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 185042500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 185042500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 185042500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 185042500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 173494412 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 173494412 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 173494412 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39420.856412 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39420.856412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39420.856412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39420.856412 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39421.069450 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39421.069450 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39421.069450 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39421.069450 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39421.069450 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39421.069450 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170928000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170928000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170928000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170928000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170928000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170928000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170929000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 170929000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170929000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 170929000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170929000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 170929000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.145718 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.145718 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.145718 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.358756 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.358756 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.358756 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.358756 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.358756 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.358756 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1363.438791 # Cycle average of tags in use system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.451495 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332874 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332874 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1363.438791 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332871 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332871 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 56681681 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681681 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits @@ -155,12 +155,12 @@ system.cpu.dcache.overall_misses::cpu.data 1905 # system.cpu.dcache.overall_misses::total 1905 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 18020000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 18020000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 88242000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 88242000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106262000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106262000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106262000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106262000 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 88243000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 88243000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106263000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106263000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106263000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106263000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 56682008 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 56682008 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) @@ -179,12 +179,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 55107.033639 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.152091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55920.152091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55780.577428 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55780.577428 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.785805 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55920.785805 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55781.102362 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55781.102362 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55781.102362 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55781.102362 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,12 +205,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1905 system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83509000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83509000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100547500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 100547500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100547500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 100547500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses @@ -221,22 +221,22 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.785805 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.785805 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.839895 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.839895 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.839895 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.839895 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2058.146079 # Cycle average of tags in use system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.021756 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1829.968899 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.177535 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 0.021788 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1829.948431 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 228.175860 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.055846 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy |