diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref')
12 files changed, 2570 insertions, 2177 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 17c346b69..bb082f445 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041684 # Number of seconds simulated -sim_ticks 41683573000 # Number of ticks simulated -final_tick 41683573000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041682 # Number of seconds simulated +sim_ticks 41681685000 # Number of ticks simulated +final_tick 41681685000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119929 # Simulator instruction rate (inst/s) -host_op_rate 119929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54395175 # Simulator tick rate (ticks/s) -host_mem_usage 269084 # Number of bytes of host memory used -host_seconds 766.31 # Real time elapsed on the host +host_inst_rate 117228 # Simulator instruction rate (inst/s) +host_op_rate 117228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53167547 # Simulator tick rate (ticks/s) +host_mem_usage 270132 # Number of bytes of host memory used +host_seconds 783.97 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4289843 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3291848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7581692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4289843 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4289843 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4289843 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3291848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7581692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4290038 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3291997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7582035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4290038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4290038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4290038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3291997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7582035 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 41683192000 # Total gap between requests +system.physmem.totGap 41681611000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 3265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 74 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,28 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 284 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 541.521127 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 335.427822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.351632 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 58 20.42% 20.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 54 19.01% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24 8.45% 47.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12 4.23% 52.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 10 3.52% 55.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9 3.17% 58.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 1.76% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 1.76% 62.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 107 37.68% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 284 # Bytes accessed per row activation -system.physmem.totQLat 37971250 # Total ticks spent queuing -system.physmem.totMemAccLat 131493750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 856 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 367.551402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 223.659981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 343.121338 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 258 30.14% 30.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 183 21.38% 51.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95 11.10% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 7.36% 69.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 46 5.37% 75.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 30 3.50% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 51 5.96% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 22 2.57% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 108 12.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 856 # Bytes accessed per row activation +system.physmem.totQLat 35422000 # Total ticks spent queuing +system.physmem.totMemAccLat 128009500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers -system.physmem.totBankLat 68832500 # Total ticks spent accessing banks -system.physmem.avgQLat 7689.60 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13939.35 # Average bank access latency per DRAM burst +system.physmem.avgQLat 7173.35 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26628.95 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25923.35 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s @@ -218,14 +216,18 @@ system.physmem.busUtilRead 0.06 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4086 # Number of row buffer hits during reads +system.physmem.readRowHits 4077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.75 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8441310.65 # Average gap between requests -system.physmem.pageHitRate 82.75 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 7581692 # Throughput (bytes/s) +system.physmem.avgGap 8440990.48 # Average gap between requests +system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 39211333500 # Time in different power states +system.physmem.memoryStateTime::REF 1391780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1076956500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 7582035 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution @@ -236,40 +238,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5782000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 45941000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 45945000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 13412627 # Number of BP lookups +system.cpu.branchPred.lookups 13412628 # Number of BP lookups system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 7424479 # Number of BTB lookups -system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits +system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3768498 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.757730 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 50.757737 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996264 # DTB read hits +system.cpu.dtb.read_hits 19996260 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996274 # DTB read accesses -system.cpu.dtb.write_hits 6501866 # DTB write hits +system.cpu.dtb.read_accesses 19996270 # DTB read accesses +system.cpu.dtb.write_hits 6501862 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501889 # DTB write accesses -system.cpu.dtb.data_hits 26498130 # DTB hits +system.cpu.dtb.write_accesses 6501885 # DTB write accesses +system.cpu.dtb.data_hits 26498122 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498163 # DTB accesses -system.cpu.itb.fetch_hits 9956950 # ITB hits +system.cpu.dtb.data_accesses 26498155 # DTB accesses +system.cpu.itb.fetch_hits 9956951 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9956999 # ITB accesses +system.cpu.itb.fetch_accesses 9957000 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -283,10 +285,10 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83367147 # number of cpu cycles simulated +system.cpu.numCycles 83363371 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 5905663 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 73570553 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File @@ -305,12 +307,12 @@ system.cpu.execution_unit.executions 57404027 # Nu system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82970332 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970271 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10410 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7759392 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607755 # Number of cycles cpu stages are processed. -system.cpu.activity 90.692506 # Percentage of cycles cpu is active +system.cpu.timesIdled 10393 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7755613 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607758 # Number of cycles cpu stages are processed. +system.cpu.activity 90.696618 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -322,36 +324,36 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.907121 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.907079 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.907121 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102389 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.907079 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102439 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.102389 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27686803 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680344 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.789312 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34115467 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251680 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.078044 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33515800 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.102439 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27683021 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680350 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.792345 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34111687 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.080725 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33512024 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 49851347 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.797353 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65340657 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026490 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.623014 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29507392 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 59.800061 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65336871 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026500 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.624006 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29503616 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 53859755 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.605491 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 64.608418 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 7635 # number of replacements -system.cpu.icache.tags.tagsinuse 1492.188372 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1492.194030 # Cycle average of tags in use system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1492.188372 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.728608 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.728608 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.194030 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728610 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728610 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1885 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id @@ -359,44 +361,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 613 system.cpu.icache.tags.age_task_id_blocks_1024::3 136 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 959 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.920410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 19923420 # Number of tag accesses -system.cpu.icache.tags.data_accesses 19923420 # Number of data accesses +system.cpu.icache.tags.tag_accesses 19923422 # Number of tag accesses +system.cpu.icache.tags.data_accesses 19923422 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits system.cpu.icache.overall_hits::total 9945551 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11399 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11399 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11399 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses -system.cpu.icache.overall_misses::total 11399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 329283500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 329283500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 329283500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 329283500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 329283500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 329283500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9956950 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9956950 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9956950 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 11400 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11400 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11400 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11400 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11400 # number of overall misses +system.cpu.icache.overall_misses::total 11400 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 327908250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 327908250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 327908250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 327908250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 327908250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 327908250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956951 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956951 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956951 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956951 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956951 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9956951 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28887.051496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28887.051496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28887.051496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28887.051496 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28763.881579 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28763.881579 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28763.881579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28763.881579 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -405,38 +407,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1880 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1880 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1880 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1880 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1880 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1880 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268822750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 268822750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268822750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 268822750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268822750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 268822750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268503000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 268503000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268503000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 268503000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268503000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 268503000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28237.683824 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28237.683824 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28204.096639 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28204.096639 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 18194218 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 18195042 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -452,21 +454,21 @@ system.cpu.toL2Bus.data_through_bus 758400 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 14800250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 14805000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3515750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3522500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2189.597840 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2189.603987 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.844631 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.766792 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.844250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.772066 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 350.987671 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055566 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.066821 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3282 # Occupied blocks per task id @@ -502,17 +504,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191765250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32319750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 224085000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125611500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 125611500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 191765250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 157931250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 349696500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 191765250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 157931250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 349696500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191445500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31242750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 222688250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 121662250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 121662250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 191445500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 152905000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 344350500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 191445500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 152905000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 344350500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -537,17 +539,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68634.663565 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76587.085308 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69678.171642 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72945.121951 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72945.121951 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70817.436209 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70817.436209 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68520.221904 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74034.952607 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69243.858831 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70651.713124 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70651.713124 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68520.221904 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71317.630597 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69734.811665 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68520.221904 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71317.630597 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69734.811665 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -567,17 +569,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156642750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27057250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 183700000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104540000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104540000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156642750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131597250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 288240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156642750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131597250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 288240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156316500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25982750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 182299250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100579250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100579250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156316500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 126562000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 282878500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156316500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 126562000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282878500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -589,25 +591,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56063.976378 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64116.706161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57120.646766 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60708.478513 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60708.478513 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55947.208304 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61570.497630 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56685.090174 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58408.391405 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58408.391405 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55947.208304 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59030.783582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57286.046983 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55947.208304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59030.783582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57286.046983 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.382253 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26488456 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1441.383569 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488452 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11915.634728 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.632928 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.382253 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.383569 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.351900 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.351900 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id @@ -619,30 +621,30 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492835 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492835 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488456 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488456 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488456 # number of overall hits -system.cpu.dcache.overall_hits::total 26488456 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8268 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8268 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8845 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8845 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8845 # number of overall misses -system.cpu.dcache.overall_misses::total 8845 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40979500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40979500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 507652000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 507652000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 548631500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 548631500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 548631500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 548631500 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 19995619 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995619 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492833 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492833 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488452 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488452 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488452 # number of overall hits +system.cpu.dcache.overall_hits::total 26488452 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 579 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 579 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8270 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8270 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8849 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8849 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8849 # number of overall misses +system.cpu.dcache.overall_misses::total 8849 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39903000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39903000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 493053000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 493053000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 532956000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 532956000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 532956000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 532956000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -659,32 +661,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71021.663778 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71021.663778 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61399.612966 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61399.612966 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62027.303561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62027.303561 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25755 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68917.098446 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68917.098446 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59619.467956 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59619.467956 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60227.822353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60227.822353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60227.822353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60227.822353 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 844 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 836 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.515403 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.770335 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6520 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6520 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6622 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6622 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6622 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6622 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6522 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6522 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6626 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6626 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6626 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6626 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -693,14 +695,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33343250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33343250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127629000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 127629000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160972250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 160972250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160972250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 160972250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32266250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32266250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 123679750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 123679750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155946000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 155946000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155946000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 155946000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -709,14 +711,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70196.315789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70196.315789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73014.302059 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73014.302059 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67928.947368 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67928.947368 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70755.005721 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70755.005721 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index c3a9e9ab9..c2ef654cc 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023455 # Number of seconds simulated -sim_ticks 23455364500 # Number of ticks simulated -final_tick 23455364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023496 # Number of seconds simulated +sim_ticks 23495860500 # Number of ticks simulated +final_tick 23495860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164985 # Simulator instruction rate (inst/s) -host_op_rate 164985 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45970553 # Simulator tick rate (ticks/s) -host_mem_usage 272156 # Number of bytes of host memory used -host_seconds 510.23 # Real time elapsed on the host +host_inst_rate 162171 # Simulator instruction rate (inst/s) +host_op_rate 162171 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45264552 # Simulator tick rate (ticks/s) +host_mem_usage 273204 # Number of bytes of host memory used +host_seconds 519.08 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory -system.physmem.bytes_read::total 334592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8354933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5910119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14265052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8354933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8354933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8354933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5910119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14265052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5228 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory +system.physmem.bytes_read::total 334528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8345981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5891761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14237742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8345981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8345981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8345981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5891761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14237742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5227 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 469 # Per bank write bursts -system.physmem.perBankRdBursts::1 290 # Per bank write bursts -system.physmem.perBankRdBursts::2 301 # Per bank write bursts -system.physmem.perBankRdBursts::3 519 # Per bank write bursts +system.physmem.perBankRdBursts::1 291 # Per bank write bursts +system.physmem.perBankRdBursts::2 302 # Per bank write bursts +system.physmem.perBankRdBursts::3 524 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 227 # Per bank write bursts +system.physmem.perBankRdBursts::5 226 # Per bank write bursts system.physmem.perBankRdBursts::6 220 # Per bank write bursts -system.physmem.perBankRdBursts::7 288 # Per bank write bursts +system.physmem.perBankRdBursts::7 285 # Per bank write bursts system.physmem.perBankRdBursts::8 236 # Per bank write bursts -system.physmem.perBankRdBursts::9 278 # Per bank write bursts +system.physmem.perBankRdBursts::9 280 # Per bank write bursts system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 255 # Per bank write bursts -system.physmem.perBankRdBursts::12 401 # Per bank write bursts -system.physmem.perBankRdBursts::13 338 # Per bank write bursts +system.physmem.perBankRdBursts::11 254 # Per bank write bursts +system.physmem.perBankRdBursts::12 398 # Per bank write bursts +system.physmem.perBankRdBursts::13 336 # Per bank write bursts system.physmem.perBankRdBursts::14 491 # Per bank write bursts system.physmem.perBankRdBursts::15 447 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23455237500 # Total gap between requests +system.physmem.totGap 23495733500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5228 # Read request sizes (log2) +system.physmem.readPktSize::6 5227 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,90 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 339 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.348083 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 311.933424 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 425.197716 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 81 23.89% 23.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 64 18.88% 42.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 21 6.19% 48.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 17 5.01% 53.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9 2.65% 56.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 2.36% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7 2.06% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 0.88% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 129 38.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 339 # Bytes accessed per row activation -system.physmem.totQLat 42838250 # Total ticks spent queuing -system.physmem.totMemAccLat 141220750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers -system.physmem.totBankLat 72242500 # Total ticks spent accessing banks -system.physmem.avgQLat 8194.00 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13818.38 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 383.188005 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 230.923786 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 354.572905 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 252 29.07% 29.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 197 22.72% 51.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 79 9.11% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.57% 67.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 42 4.84% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 41 4.73% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 51 5.88% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 24 2.77% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 124 14.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 867 # Bytes accessed per row activation +system.physmem.totQLat 41053500 # Total ticks spent queuing +system.physmem.totMemAccLat 139059750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7854.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27012.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26604.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.11 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4346 # Number of row buffer hits during reads +system.physmem.readRowHits 4351 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.13 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4486464.71 # Average gap between requests -system.physmem.pageHitRate 83.13 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.10 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 14265052 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3523 # Transaction distribution -system.membus.trans_dist::ReadResp 3523 # Transaction distribution +system.physmem.avgGap 4495070.50 # Average gap between requests +system.physmem.pageHitRate 83.24 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 21787630000 # Time in different power states +system.physmem.memoryStateTime::REF 784420000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 919340000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 14237742 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3522 # Transaction distribution +system.membus.trans_dist::ReadResp 3522 # Transaction distribution system.membus.trans_dist::ReadExReq 1705 # Transaction distribution system.membus.trans_dist::ReadExResp 1705 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334592 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6760500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6755000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48963750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 48973500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14848335 # Number of BP lookups -system.cpu.branchPred.condPredicted 10770516 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 922016 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8296689 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6955595 # Number of BTB hits +system.cpu.branchPred.lookups 14867597 # Number of BP lookups +system.cpu.branchPred.condPredicted 10786733 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 927657 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8507235 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6975722 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.835793 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1468520 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3112 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.997523 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1468896 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3134 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23116922 # DTB read hits -system.cpu.dtb.read_misses 193562 # DTB read misses -system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 23310484 # DTB read accesses -system.cpu.dtb.write_hits 7068693 # DTB write hits -system.cpu.dtb.write_misses 1118 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 7069811 # DTB write accesses -system.cpu.dtb.data_hits 30185615 # DTB hits -system.cpu.dtb.data_misses 194680 # DTB misses -system.cpu.dtb.data_acv 6 # DTB access violations -system.cpu.dtb.data_accesses 30380295 # DTB accesses -system.cpu.itb.fetch_hits 14732180 # ITB hits -system.cpu.itb.fetch_misses 100 # ITB misses +system.cpu.dtb.read_hits 23141508 # DTB read hits +system.cpu.dtb.read_misses 194908 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 23336416 # DTB read accesses +system.cpu.dtb.write_hits 7073051 # DTB write hits +system.cpu.dtb.write_misses 1111 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 7074162 # DTB write accesses +system.cpu.dtb.data_hits 30214559 # DTB hits +system.cpu.dtb.data_misses 196019 # DTB misses +system.cpu.dtb.data_acv 3 # DTB access violations +system.cpu.dtb.data_accesses 30410578 # DTB accesses +system.cpu.itb.fetch_hits 14761442 # ITB hits +system.cpu.itb.fetch_misses 106 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14732280 # ITB accesses +system.cpu.itb.fetch_accesses 14761548 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -283,238 +285,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46910730 # number of cpu cycles simulated +system.cpu.numCycles 46991722 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15458006 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126949517 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14848335 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8424115 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22129467 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4471319 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5547804 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2176 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 15493602 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127144789 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14867597 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8444618 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22164191 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4494518 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5543985 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 114 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2326 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14732180 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 325492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46652781 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.721156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376288 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 14761442 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 326314 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46736650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.720451 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.375825 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24523314 52.57% 52.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2362460 5.06% 57.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1191709 2.55% 60.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1744531 3.74% 63.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2756035 5.91% 69.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1149513 2.46% 72.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1216156 2.61% 74.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 771099 1.65% 76.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10937964 23.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24572459 52.58% 52.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2364267 5.06% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1190852 2.55% 60.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1750659 3.75% 63.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2760354 5.91% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1155374 2.47% 72.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1219764 2.61% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 773397 1.65% 76.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10949524 23.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46652781 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316523 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.706194 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17279755 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4249359 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20525557 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1094653 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3503457 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2516236 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12079 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123971467 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3503457 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18421615 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 960025 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8092 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20456033 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3303559 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121144333 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 76 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 398869 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2427038 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88958437 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157404324 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150359413 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7044910 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46736650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316388 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.705685 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17320813 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4244089 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20558459 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1092640 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3520649 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2518881 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12242 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 124135665 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32164 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3520649 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18467014 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 956444 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7682 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20482522 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3302339 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121292511 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 405307 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2418029 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89077183 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157604141 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 150534696 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7069444 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20531076 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 753 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 746 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8762869 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25364686 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8245053 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2579677 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 916866 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105436349 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1901 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96572685 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 177506 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20788885 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15603704 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1512 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46652781 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.070031 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.877189 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20649822 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 718 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 707 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8775432 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25394818 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8253633 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2570331 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 907077 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105549830 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2075 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96657653 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 179218 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20902238 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15662437 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1686 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46736650 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.068134 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876130 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12130850 26.00% 26.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9330795 20.00% 46.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8389374 17.98% 63.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6281972 13.47% 77.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4924466 10.56% 88.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2864469 6.14% 94.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1724344 3.70% 97.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 801135 1.72% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 205376 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12165151 26.03% 26.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9350062 20.01% 46.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8404811 17.98% 64.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6298333 13.48% 77.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4922419 10.53% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2869013 6.14% 94.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1725015 3.69% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 796629 1.70% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 205217 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46652781 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46736650 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 187827 11.99% 11.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 195 0.01% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7087 0.45% 12.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5615 0.36% 12.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842803 53.78% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445934 28.46% 95.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77665 4.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189767 12.10% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 186 0.01% 12.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7209 0.46% 12.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5897 0.38% 12.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843167 53.74% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445094 28.37% 95.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77619 4.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58739096 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479860 0.50% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2798014 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115391 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386555 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 310970 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759904 0.79% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23830824 24.68% 92.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7151745 7.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58783696 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479813 0.50% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2802274 2.90% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115457 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387860 2.47% 66.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311147 0.32% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760157 0.79% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23859982 24.69% 92.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7156941 7.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96572685 # Type of FU issued -system.cpu.iq.rate 2.058648 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1567126 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016227 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226432918 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117523015 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87074868 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15109865 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8738386 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7061397 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90154911 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7984893 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1517468 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96657653 # Type of FU issued +system.cpu.iq.rate 2.056908 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1568939 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226667825 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117702286 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87133167 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15132288 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8786528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7070448 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90230128 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7996457 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1520956 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5368488 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18513 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34393 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1743950 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5398620 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18484 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34785 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1752530 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10556 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2089 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10530 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2127 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3503457 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 134155 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17977 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115673905 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 371989 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25364686 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8245053 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1901 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2671 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34393 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 533358 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 495038 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1028396 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95341973 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23310954 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1230712 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3520649 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133897 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18217 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115793083 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 374761 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25394818 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8253633 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2075 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2932 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 43 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34785 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 541104 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495336 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1036440 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95417746 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23336859 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1239907 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10235655 # number of nop insts executed -system.cpu.iew.exec_refs 30380968 # number of memory reference insts executed -system.cpu.iew.exec_branches 12023807 # Number of branches executed -system.cpu.iew.exec_stores 7070014 # Number of stores executed -system.cpu.iew.exec_rate 2.032413 # Inst execution rate -system.cpu.iew.wb_sent 94656410 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94136265 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64475750 # num instructions producing a value -system.cpu.iew.wb_consumers 89852391 # num instructions consuming a value +system.cpu.iew.exec_nop 10241178 # number of nop insts executed +system.cpu.iew.exec_refs 30411225 # number of memory reference insts executed +system.cpu.iew.exec_branches 12030179 # Number of branches executed +system.cpu.iew.exec_stores 7074366 # Number of stores executed +system.cpu.iew.exec_rate 2.030522 # Inst execution rate +system.cpu.iew.wb_sent 94727613 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94203615 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64511907 # num instructions producing a value +system.cpu.iew.wb_consumers 89904657 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.006711 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717574 # average fanout of values written-back +system.cpu.iew.wb_rate 2.004685 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717559 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23771863 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23891142 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 910264 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43149324 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.129884 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.746526 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 915882 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43216001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.126598 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.743951 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16704227 38.71% 38.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9920088 22.99% 61.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4481212 10.39% 72.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2253745 5.22% 77.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1606057 3.72% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1123881 2.60% 83.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722151 1.67% 85.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 820935 1.90% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5517028 12.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16755601 38.77% 38.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9919008 22.95% 61.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4484606 10.38% 72.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2269127 5.25% 77.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1610437 3.73% 81.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1128955 2.61% 83.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722092 1.67% 85.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 821021 1.90% 87.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5505154 12.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43149324 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43216001 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -525,230 +527,264 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5517028 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 51001542 55.49% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2732464 2.97% 67.37% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 19996198 21.76% 92.93% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction +system.cpu.commit.bw_lim_events 5505154 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153306174 # The number of ROB reads -system.cpu.rob.rob_writes 234877097 # The number of ROB writes -system.cpu.timesIdled 5272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 257949 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153504004 # The number of ROB reads +system.cpu.rob.rob_writes 235133069 # The number of ROB writes +system.cpu.timesIdled 5418 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 255072 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.557269 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.557269 # CPI: Total CPI of All Threads -system.cpu.ipc 1.794466 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.794466 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129050731 # number of integer regfile reads -system.cpu.int_regfile_writes 70522819 # number of integer regfile writes -system.cpu.fp_regfile_reads 6187407 # number of floating regfile reads -system.cpu.fp_regfile_writes 6043154 # number of floating regfile writes -system.cpu.misc_regfile_reads 714454 # number of misc regfile reads +system.cpu.cpi 0.558231 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.558231 # CPI: Total CPI of All Threads +system.cpu.ipc 1.791373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.791373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129151691 # number of integer regfile reads +system.cpu.int_regfile_writes 70572840 # number of integer regfile writes +system.cpu.fp_regfile_reads 6193374 # number of floating regfile reads +system.cpu.fp_regfile_writes 6052358 # number of floating regfile writes +system.cpu.misc_regfile_reads 714605 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37351626 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 11849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 11849 # Transaction distribution +system.cpu.toL2Bus.throughput 37684936 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 11995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27269 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 876096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 876096 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22964 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4597 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27561 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 885440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 885440 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 6953500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 7026500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17562000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17802750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3539750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3545000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9398 # number of replacements -system.cpu.icache.tags.tagsinuse 1599.250917 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14718111 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11333 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1298.695050 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9548 # number of replacements +system.cpu.icache.tags.tagsinuse 1597.278061 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14747183 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11482 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1284.374064 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1599.250917 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.780884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.780884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1935 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1597.278061 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.779921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.779921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 929 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.944824 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 29475691 # Number of tag accesses -system.cpu.icache.tags.data_accesses 29475691 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14718111 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14718111 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14718111 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14718111 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14718111 # number of overall hits -system.cpu.icache.overall_hits::total 14718111 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14068 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14068 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14068 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14068 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14068 # number of overall misses -system.cpu.icache.overall_misses::total 14068 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413989500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413989500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413989500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413989500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413989500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413989500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14732179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14732179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14732179 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14732179 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14732179 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14732179 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000955 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000955 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000955 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000955 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000955 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29427.743816 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29427.743816 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29427.743816 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29427.743816 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29427.743816 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29427.743816 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 165 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 29534364 # Number of tag accesses +system.cpu.icache.tags.data_accesses 29534364 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 14747183 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14747183 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14747183 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14747183 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14747183 # number of overall hits +system.cpu.icache.overall_hits::total 14747183 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14258 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14258 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14258 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14258 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14258 # number of overall misses +system.cpu.icache.overall_misses::total 14258 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 414157250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 414157250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 414157250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 414157250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 414157250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 414157250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14761441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14761441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14761441 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14761441 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14761441 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14761441 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000966 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000966 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000966 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000966 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73264.216366 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70609.814425 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -757,187 +793,186 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3062 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3523 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3064 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3522 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1705 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1705 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3062 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2166 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5228 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 172480500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30915000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 203395500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104707750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104707750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172480500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 135622750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 308103250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172480500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 135622750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 308103250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.297325 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3064 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3064 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171789000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30123000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201912000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101752000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101752000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171789000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131875000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 303664000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171789000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131875000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 303664000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293622 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.384978 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.384978 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56329.359895 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67060.737527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.607721 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61412.170088 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61412.170088 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.380810 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.380810 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56066.906005 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65770.742358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57328.790460 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59678.592375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59678.592375 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56066.906005 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60968.562182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58095.274536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56066.906005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60968.562182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58095.274536 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1460.308394 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28078942 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12496.191366 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1456.991941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28100018 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12522.289661 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1460.308394 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.356521 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.356521 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1456.991941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355711 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355711 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1391 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 56178581 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 56178581 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21585827 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21585827 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492868 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492868 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 247 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 247 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28078695 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28078695 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28078695 # number of overall hits -system.cpu.dcache.overall_hits::total 28078695 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 989 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 989 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8235 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8235 # number of WriteReq misses +system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 56220748 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 56220748 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21606921 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21606921 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492872 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492872 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 225 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 225 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28099793 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28099793 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28099793 # number of overall hits +system.cpu.dcache.overall_hits::total 28099793 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1002 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1002 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8231 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8231 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9224 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9224 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9224 # number of overall misses -system.cpu.dcache.overall_misses::total 9224 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64012750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64012750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 517866286 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 517866286 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9233 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9233 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9233 # number of overall misses +system.cpu.dcache.overall_misses::total 9233 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 62924000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 62924000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 508720531 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 508720531 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 581879036 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 581879036 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 581879036 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 581879036 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21586816 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21586816 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 571644531 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 571644531 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 571644531 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 571644531 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21607923 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21607923 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28087919 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28087919 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28087919 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28087919 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 226 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 226 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28109026 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28109026 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28109026 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28109026 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001267 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001267 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004032 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004032 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001266 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001266 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004425 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004425 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64724.721941 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64724.721941 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62886.009229 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62886.009229 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62798.403194 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62798.403194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61805.434455 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61805.434455 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63083.156548 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63083.156548 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24818 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61913.195170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61913.195170 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23691 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 346 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.728324 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.069971 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # number of writebacks system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 474 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6504 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6504 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6978 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6978 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6978 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6978 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 490 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6500 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6500 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6990 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6990 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6990 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6990 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37612750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37612750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127737997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 127737997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36779750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36779750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124808747 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 124808747 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165350747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 165350747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 165350747 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 165350747 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161588497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161588497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161588497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161588497 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004032 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004032 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004425 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004425 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73034.466019 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73034.466019 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73794.336800 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73794.336800 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71835.449219 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71835.449219 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72102.106875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72102.106875 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 632b87104..5bf6c1d3d 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1649677 # Simulator instruction rate (inst/s) -host_op_rate 1649676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 824838449 # Simulator tick rate (ticks/s) -host_mem_usage 275016 # Number of bytes of host memory used -host_seconds 55.71 # Real time elapsed on the host +host_inst_rate 2663178 # Simulator instruction rate (inst/s) +host_op_rate 2663177 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1331588953 # Simulator tick rate (ticks/s) +host_mem_usage 260384 # Number of bytes of host memory used +host_seconds 34.51 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 91903136 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched +system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction +system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction +system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction +system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91903089 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index bb6abdd34..88e7e1e1c 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316000 # Number of ticks simulated final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1382014 # Simulator instruction rate (inst/s) -host_op_rate 1382013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1785419086 # Simulator tick rate (ticks/s) -host_mem_usage 233256 # Number of bytes of host memory used -host_seconds 66.50 # Real time elapsed on the host +host_inst_rate 1199929 # Simulator instruction rate (inst/s) +host_op_rate 1199929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1550185026 # Simulator tick rate (ticks/s) +host_mem_usage 269088 # Number of bytes of host memory used +host_seconds 76.59 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 237458632 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched +system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction +system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction +system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction +system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91903089 # Class of executed instruction system.cpu.icache.tags.replacements 6681 # number of replacements system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 975655111..d4466739f 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074212 # Number of seconds simulated -sim_ticks 74211770500 # Number of ticks simulated -final_tick 74211770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074209 # Number of seconds simulated +sim_ticks 74208571000 # Number of ticks simulated +final_tick 74208571000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109728 # Simulator instruction rate (inst/s) -host_op_rate 120142 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47260193 # Simulator tick rate (ticks/s) -host_mem_usage 316324 # Number of bytes of host memory used -host_seconds 1570.28 # Real time elapsed on the host +host_inst_rate 109569 # Simulator instruction rate (inst/s) +host_op_rate 119969 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47190079 # Simulator tick rate (ticks/s) +host_mem_usage 316768 # Number of bytes of host memory used +host_seconds 1572.55 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112000 # Number of bytes read from this memory -system.physmem.bytes_read::total 243072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1750 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3798 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1766189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1509195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3275383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1766189 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1766189 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1766189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1509195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3275383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3799 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 131456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory +system.physmem.bytes_read::total 243264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131456 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2054 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3801 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1771440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1506672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3278112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1771440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1771440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1771440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1506672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3278112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3802 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3799 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3802 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 243136 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 243328 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 243136 # Total read bytes from the system interface side +system.physmem.bytesReadSys 243328 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 306 # Per bank write bursts -system.physmem.perBankRdBursts::1 215 # Per bank write bursts -system.physmem.perBankRdBursts::2 132 # Per bank write bursts +system.physmem.perBankRdBursts::1 216 # Per bank write bursts +system.physmem.perBankRdBursts::2 134 # Per bank write bursts system.physmem.perBankRdBursts::3 308 # Per bank write bursts system.physmem.perBankRdBursts::4 298 # Per bank write bursts -system.physmem.perBankRdBursts::5 299 # Per bank write bursts +system.physmem.perBankRdBursts::5 300 # Per bank write bursts system.physmem.perBankRdBursts::6 265 # Per bank write bursts -system.physmem.perBankRdBursts::7 218 # Per bank write bursts +system.physmem.perBankRdBursts::7 217 # Per bank write bursts system.physmem.perBankRdBursts::8 246 # Per bank write bursts -system.physmem.perBankRdBursts::9 214 # Per bank write bursts +system.physmem.perBankRdBursts::9 215 # Per bank write bursts system.physmem.perBankRdBursts::10 289 # Per bank write bursts system.physmem.perBankRdBursts::11 192 # Per bank write bursts system.physmem.perBankRdBursts::12 190 # Per bank write bursts system.physmem.perBankRdBursts::13 208 # Per bank write bursts -system.physmem.perBankRdBursts::14 219 # Per bank write bursts +system.physmem.perBankRdBursts::14 218 # Per bank write bursts system.physmem.perBankRdBursts::15 200 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 74211752000 # Total gap between requests +system.physmem.totGap 74208552500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3799 # Read request sizes (log2) +system.physmem.readPktSize::6 3802 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,28 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 398.476190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 217.440190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 401.372897 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 87 34.52% 34.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 58 23.02% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17 6.75% 64.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 1.98% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7 2.78% 69.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 3.17% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 1.59% 73.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 1.19% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 63 25.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 252 # Bytes accessed per row activation -system.physmem.totQLat 23847500 # Total ticks spent queuing -system.physmem.totMemAccLat 100702500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 18995000 # Total ticks spent in databus transfers -system.physmem.totBankLat 57860000 # Total ticks spent accessing banks -system.physmem.avgQLat 6277.31 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15230.32 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 765 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 315.649673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.993895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 311.806865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 244 31.90% 31.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 208 27.19% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 73 9.54% 68.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 46 6.01% 74.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 29 3.79% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 70 9.15% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 12 1.57% 89.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 15 1.96% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 68 8.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 765 # Bytes accessed per row activation +system.physmem.totQLat 30320750 # Total ticks spent queuing +system.physmem.totMemAccLat 101608250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19010000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7974.95 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26507.63 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26724.95 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.28 # Average system read bandwidth in MiByte/s @@ -216,40 +214,44 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3018 # Number of row buffer hits during reads +system.physmem.readRowHits 3030 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19534549.09 # Average gap between requests -system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 3275383 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2728 # Transaction distribution -system.membus.trans_dist::ReadResp 2727 # Transaction distribution +system.physmem.avgGap 19518293.66 # Average gap between requests +system.physmem.pageHitRate 79.69 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 70857777500 # Time in different power states +system.physmem.memoryStateTime::REF 2477800000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 867720500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 3278112 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2731 # Transaction distribution +system.membus.trans_dist::ReadResp 2730 # Transaction distribution system.membus.trans_dist::ReadExReq 1071 # Transaction distribution system.membus.trans_dist::ReadExResp 1071 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7597 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7597 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243072 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 243072 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 243072 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7603 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7603 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243264 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 243264 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 243264 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4687500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35592500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35718000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 94795806 # Number of BP lookups -system.cpu.branchPred.condPredicted 74795654 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6279989 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44691885 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43051051 # Number of BTB hits +system.cpu.branchPred.lookups 94830067 # Number of BP lookups +system.cpu.branchPred.condPredicted 74823235 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6280063 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44671635 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43055955 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.328564 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4354918 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88426 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.383208 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4354004 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88575 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -335,135 +337,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148423542 # number of cpu cycles simulated +system.cpu.numCycles 148417143 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39654967 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380195915 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94795806 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47405969 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80368300 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27279262 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7212539 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5988 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39654365 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380231735 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94830067 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47409959 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80369944 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27285630 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7202415 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5794 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36848695 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1833193 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148225221 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802047 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153051 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36851066 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1832690 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148222429 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153204 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68026374 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5263091 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10536182 7.11% 56.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10285653 6.94% 63.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8660137 5.84% 69.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6544581 4.42% 73.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6243734 4.21% 77.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8007959 5.40% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24657510 16.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68020985 45.89% 45.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5256509 3.55% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10534999 7.11% 56.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10284828 6.94% 63.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8666572 5.85% 69.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6537070 4.41% 73.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6246175 4.21% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8016813 5.41% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24658478 16.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148225221 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638684 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.561561 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45510679 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5881311 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74801618 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1201370 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20830243 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14327753 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164034 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392767808 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 749358 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20830243 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50895494 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 723680 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 602483 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70555782 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4617539 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371309891 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 338990 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3664355 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 25 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631718613 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1588504211 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506839397 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3198087 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 148222429 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638943 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.561913 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45507597 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5871716 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74805608 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1201041 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20836467 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14340186 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164591 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392845308 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 733522 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20836467 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50894479 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 722812 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 602318 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70557272 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4609081 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371354915 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 338748 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3656059 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631764461 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1588652531 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506975247 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3198470 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333674474 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25005 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25002 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13030816 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43005440 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16429294 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5701095 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3639070 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329189812 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47090 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249460239 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 787524 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139505237 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362363758 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1874 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148225221 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.682981 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761692 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 333720322 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25119 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25116 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13019783 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43012506 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16421309 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5620383 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3639856 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329245944 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47173 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249482695 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 793526 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139565421 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362544222 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1957 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148222429 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.683164 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761970 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56054819 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22642547 15.28% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24806201 16.74% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20327492 13.71% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12550892 8.47% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6518173 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4029511 2.72% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1113373 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 182213 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56049781 37.81% 37.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22646407 15.28% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24808421 16.74% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20317592 13.71% 83.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12547069 8.47% 92.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6521251 4.40% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4032352 2.72% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1118421 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181135 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148225221 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148222429 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 964965 38.34% 38.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5593 0.22% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 99 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 49 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1170821 46.51% 85.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 375623 14.92% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 964061 38.35% 38.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5595 0.22% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 96 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1168003 46.46% 85.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 376162 14.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194894311 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979316 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194908316 78.12% 78.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 978999 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued @@ -482,93 +484,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33075 0.01% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33072 0.01% 78.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164356 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254647 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76432 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465549 0.19% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206388 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71859 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164299 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255151 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76428 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465968 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206368 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71868 0.03% 79.03% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38358541 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13955444 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38371220 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13950685 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249460239 # Type of FU issued -system.cpu.iq.rate 1.680732 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2517150 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010090 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646712991 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466571759 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237891174 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3737382 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2188885 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1841279 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250102160 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1875229 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2007089 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249482695 # Type of FU issued +system.cpu.iq.rate 1.680956 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2513965 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010077 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646755779 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466684925 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237894917 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3739531 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2191886 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1842592 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250120414 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1876246 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2009109 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13155956 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11631 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18977 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3784660 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13163022 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11141 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18733 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3776675 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20830243 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18508 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 911 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329253924 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 785902 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43005440 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16429294 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24682 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 206 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18977 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3891616 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3758665 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7650281 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242960344 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36855491 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6499895 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20836467 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18579 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 909 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329310121 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 781513 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43012506 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16421309 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24765 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 190 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 272 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18733 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3888765 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3761308 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7650073 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242977304 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36862847 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6505391 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17022 # number of nop insts executed -system.cpu.iew.exec_refs 50506525 # number of memory reference insts executed -system.cpu.iew.exec_branches 53424421 # Number of branches executed -system.cpu.iew.exec_stores 13651034 # Number of stores executed -system.cpu.iew.exec_rate 1.636939 # Inst execution rate -system.cpu.iew.wb_sent 240787816 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239732453 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148473522 # num instructions producing a value -system.cpu.iew.wb_consumers 267271209 # num instructions consuming a value +system.cpu.iew.exec_nop 17004 # number of nop insts executed +system.cpu.iew.exec_refs 50511963 # number of memory reference insts executed +system.cpu.iew.exec_branches 53432662 # Number of branches executed +system.cpu.iew.exec_stores 13649116 # Number of stores executed +system.cpu.iew.exec_rate 1.637124 # Inst execution rate +system.cpu.iew.wb_sent 240796428 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239737509 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148472463 # num instructions producing a value +system.cpu.iew.wb_consumers 267293668 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615192 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555516 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615295 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555466 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140583033 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140639228 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6126865 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127394978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.480992 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186196 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6126680 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127385962 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481096 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.186061 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57713917 45.30% 45.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31674198 24.86% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13788488 10.82% 80.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7625423 5.99% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4380329 3.44% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321262 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1701589 1.34% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1311888 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7877884 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57702305 45.30% 45.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31675528 24.87% 70.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13782422 10.82% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7634808 5.99% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4379316 3.44% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1319569 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1705598 1.34% 92.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1313930 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7872486 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127394978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127385962 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -579,230 +581,265 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7877884 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 144055022 76.35% 76.35% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 908940 0.48% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 76.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 76.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 76.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.08% 76.93% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.23% 77.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 29849484 15.82% 93.30% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 12644634 6.70% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction +system.cpu.commit.bw_lim_events 7872486 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448765817 # The number of ROB reads -system.cpu.rob.rob_writes 679447245 # The number of ROB writes -system.cpu.timesIdled 2831 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 198321 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448818394 # The number of ROB reads +system.cpu.rob.rob_writes 679565858 # The number of ROB writes +system.cpu.timesIdled 2789 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 194714 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.861410 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861410 # CPI: Total CPI of All Threads -system.cpu.ipc 1.160887 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.160887 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079439987 # number of integer regfile reads -system.cpu.int_regfile_writes 384873432 # number of integer regfile writes -system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads -system.cpu.fp_regfile_writes 2497165 # number of floating regfile writes -system.cpu.misc_regfile_reads 64868455 # number of misc regfile reads +system.cpu.cpi 0.861373 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861373 # CPI: Total CPI of All Threads +system.cpu.ipc 1.160937 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160937 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079497274 # number of integer regfile reads +system.cpu.int_regfile_writes 384888160 # number of integer regfile writes +system.cpu.fp_regfile_reads 2912753 # number of floating regfile reads +system.cpu.fp_regfile_writes 2499155 # number of floating regfile writes +system.cpu.misc_regfile_reads 64874393 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5152821 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4879 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8203 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3730 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11933 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 262464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 382400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 382400 # Total data (bytes) +system.cpu.toL2Bus.throughput 5170292 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 19 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1081 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1081 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8239 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3733 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11972 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3006000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6511747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6548996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3051239 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3099487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2374 # number of replacements -system.cpu.icache.tags.tagsinuse 1347.666302 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36843383 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4101 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8983.999756 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2388 # number of replacements +system.cpu.icache.tags.tagsinuse 1346.753946 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36845676 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4119 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8945.296431 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1347.666302 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.658040 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.658040 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1727 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1346.753946 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.657595 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.657595 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1040 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.843262 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 73701491 # Number of tag accesses -system.cpu.icache.tags.data_accesses 73701491 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 36843383 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36843383 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36843383 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36843383 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36843383 # number of overall hits -system.cpu.icache.overall_hits::total 36843383 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5312 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5312 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5312 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5312 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5312 # number of overall misses -system.cpu.icache.overall_misses::total 5312 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 224724996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 224724996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 224724996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 224724996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 224724996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 224724996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36848695 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36848695 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36848695 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36848695 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36848695 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36848695 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000144 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000144 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000144 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000144 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000144 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000144 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42305.157380 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42305.157380 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42305.157380 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42305.157380 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1646 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 73706251 # Number of tag accesses +system.cpu.icache.tags.data_accesses 73706251 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 36845676 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36845676 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36845676 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36845676 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36845676 # number of overall hits +system.cpu.icache.overall_hits::total 36845676 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5390 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5390 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5390 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5390 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5390 # number of overall misses +system.cpu.icache.overall_misses::total 5390 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 228751995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 228751995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 228751995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 228751995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 228751995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 228751995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36851066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36851066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36851066 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36851066 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36851066 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36851066 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42440.073284 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42440.073284 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42440.073284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42440.073284 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1596 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 86.631579 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69357.376284 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69357.376284 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69252.064109 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70843.750000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69985.598324 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69252.064109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70843.750000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69985.598324 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -811,178 +848,178 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2049 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 679 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2728 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2055 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 676 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2731 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1750 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3799 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1750 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3799 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117223750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41708750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 158932500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59427500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59427500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117223750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101136250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 218360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117223750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101136250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 218360000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.873874 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559131 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.637630 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.637630 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57210.224500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61426.730486 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58259.714076 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55487.861811 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.861811 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1747 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3802 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1747 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3802 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116514500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41206750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 157721250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60687250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60687250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116514500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101894000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 218408500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116514500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101894000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218408500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.557802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990749 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.990749 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940765 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.636105 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940765 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.636105 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56698.053528 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60956.730769 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57752.196997 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56664.098973 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56664.098973 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56698.053528 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58325.128792 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57445.686481 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56698.053528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58325.128792 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57445.686481 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 59 # number of replacements -system.cpu.dcache.tags.tagsinuse 1407.038554 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46795712 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1856 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25213.206897 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 60 # number of replacements +system.cpu.dcache.tags.tagsinuse 1407.063073 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46801066 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1857 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25202.512655 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1407.038554 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.343515 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.343515 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1407.063073 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.343521 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.343521 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.438721 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 93612504 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 93612504 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 34394263 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34394263 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356566 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356566 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22476 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22476 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 93623269 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 93623269 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 34399630 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34399630 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356556 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356556 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22473 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22473 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46750829 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46750829 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46750829 # number of overall hits -system.cpu.dcache.overall_hits::total 46750829 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1889 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1889 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7721 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7721 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46756186 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46756186 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46756186 # number of overall hits +system.cpu.dcache.overall_hits::total 46756186 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1907 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1907 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7731 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7731 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9610 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9610 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9610 # number of overall misses -system.cpu.dcache.overall_misses::total 9610 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 119060977 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 119060977 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 479134996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 479134996 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9638 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9638 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9638 # number of overall misses +system.cpu.dcache.overall_misses::total 9638 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 121525225 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 121525225 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 489452496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 489452496 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 598195973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 598195973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 598195973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 598195973 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34396152 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34396152 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 610977721 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 610977721 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 610977721 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 610977721 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34401537 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34401537 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22478 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22478 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46760439 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46760439 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46760439 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46760439 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46765824 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46765824 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46765824 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46765824 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.574378 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.574378 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62056.080300 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62056.080300 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63725.865233 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63725.865233 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63310.373302 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63310.373302 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62247.239646 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62247.239646 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 566 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63392.583627 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63392.583627 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 318 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.454545 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.545455 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 18 # number of writebacks -system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1111 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1111 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6643 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6643 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 19 # number of writebacks +system.cpu.dcache.writebacks::total 19 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1130 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1130 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6651 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6651 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7754 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7754 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7754 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7754 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 778 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52580511 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52580511 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73988748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73988748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126569259 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126569259 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126569259 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126569259 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7781 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7781 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7781 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7781 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1080 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1080 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52119013 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52119013 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75404498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75404498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 127523511 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 127523511 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 127523511 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 127523511 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses @@ -991,14 +1028,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67584.204370 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67584.204370 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68635.202226 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68635.202226 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67077.236808 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67077.236808 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69818.979630 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69818.979630 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 02bcdd9ff..af9e4b297 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu sim_ticks 103106766000 # Number of ticks simulated final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1878588 # Simulator instruction rate (inst/s) -host_op_rate 2056872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1124059947 # Simulator tick rate (ticks/s) -host_mem_usage 262308 # Number of bytes of host memory used -host_seconds 91.73 # Real time elapsed on the host +host_inst_rate 1728223 # Simulator instruction rate (inst/s) +host_op_rate 1892237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1034088491 # Simulator tick rate (ticks/s) +host_mem_usage 304984 # Number of bytes of host memory used +host_seconds 99.71 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 188670891 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 206213533 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 40300311 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 144055422 76.35% 76.35% # Class of executed instruction +system.cpu.op_class::IntMult 908940 0.48% 76.83% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 32754 0.02% 76.85% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 76.85% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 154829 0.08% 76.93% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.06% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 437591 0.23% 77.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.48% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.48% # Class of executed instruction +system.cpu.op_class::MemRead 29849484 15.82% 93.30% # Class of executed instruction +system.cpu.op_class::MemWrite 12644635 6.70% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 188671292 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 013c20430..7e06925a9 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu sim_ticks 232072304000 # Number of ticks simulated final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1152638 # Simulator instruction rate (inst/s) -host_op_rate 1262262 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1556630640 # Simulator tick rate (ticks/s) -host_mem_usage 271024 # Number of bytes of host memory used -host_seconds 149.09 # Real time elapsed on the host +host_inst_rate 924224 # Simulator instruction rate (inst/s) +host_op_rate 1012125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1248159761 # Simulator tick rate (ticks/s) +host_mem_usage 313696 # Number of bytes of host memory used +host_seconds 185.93 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 188185920 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -153,6 +153,41 @@ system.cpu.num_busy_cycles 464144608 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 40300311 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 144055422 76.35% 76.35% # Class of executed instruction +system.cpu.op_class::IntMult 908940 0.48% 76.83% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 76.83% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 32754 0.02% 76.85% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 76.85% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 154829 0.08% 76.93% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.06% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 437591 0.23% 77.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.48% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.48% # Class of executed instruction +system.cpu.op_class::MemRead 29849484 15.82% 93.30% # Class of executed instruction +system.cpu.op_class::MemWrite 12644635 6.70% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 188671292 # Class of executed instruction system.cpu.icache.tags.replacements 1506 # number of replacements system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 1f6381fd7..85aa0370c 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu sim_ticks 96722945000 # Number of ticks simulated final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2588672 # Simulator instruction rate (inst/s) -host_op_rate 2588674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1294344494 # Simulator tick rate (ticks/s) -host_mem_usage 233760 # Number of bytes of host memory used -host_seconds 74.73 # Real time elapsed on the host +host_inst_rate 2358558 # Simulator instruction rate (inst/s) +host_op_rate 2358560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1179286883 # Simulator tick rate (ticks/s) +host_mem_usage 269756 # Number of bytes of host memory used +host_seconds 82.02 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -65,5 +65,40 @@ system.cpu.num_busy_cycles 193445891 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 15132745 # Number of branches fetched +system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction +system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction +system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 193445773 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index dc02f2f3d..117dae8be 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu sim_ticks 270563082000 # Number of ticks simulated final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1313314 # Simulator instruction rate (inst/s) -host_op_rate 1313315 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1836878526 # Simulator tick rate (ticks/s) -host_mem_usage 242660 # Number of bytes of host memory used -host_seconds 147.30 # Real time elapsed on the host +host_inst_rate 1069922 # Simulator instruction rate (inst/s) +host_op_rate 1069924 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1496457293 # Simulator tick rate (ticks/s) +host_mem_usage 278484 # Number of bytes of host memory used +host_seconds 180.80 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -69,6 +69,41 @@ system.cpu.num_busy_cycles 541126164 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 15132745 # Number of branches fetched +system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction +system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction +system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 193445773 # Class of executed instruction system.cpu.icache.tags.replacements 10362 # number of replacements system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index cc1011ed3..b45ab6e1b 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144377 # Number of seconds simulated -sim_ticks 144377116000 # Number of ticks simulated -final_tick 144377116000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144620 # Number of seconds simulated +sim_ticks 144620050000 # Number of ticks simulated +final_tick 144620050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66784 # Simulator instruction rate (inst/s) -host_op_rate 111936 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73006862 # Simulator tick rate (ticks/s) -host_mem_usage 319660 # Number of bytes of host memory used -host_seconds 1977.58 # Real time elapsed on the host +host_inst_rate 65513 # Simulator instruction rate (inst/s) +host_op_rate 109805 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71737347 # Simulator tick rate (ticks/s) +host_mem_usage 319696 # Number of bytes of host memory used +host_seconds 2015.97 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125056 # Number of bytes read from this memory -system.physmem.bytes_read::total 343040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1954 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5360 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1509824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 866176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2376000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1509824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1509824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1509824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 866176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2376000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5361 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory +system.physmem.bytes_read::total 342656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1501977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 867376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2369353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1501977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1501977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1501977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 867376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2369353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5356 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5361 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5356 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 343104 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 342784 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 343104 # Total read bytes from the system interface side +system.physmem.bytesReadSys 342784 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 150 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 281 # Per bank write bursts -system.physmem.perBankRdBursts::1 346 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 131 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 288 # Per bank write bursts +system.physmem.perBankRdBursts::1 358 # Per bank write bursts system.physmem.perBankRdBursts::2 449 # Per bank write bursts -system.physmem.perBankRdBursts::3 351 # Per bank write bursts -system.physmem.perBankRdBursts::4 335 # Per bank write bursts +system.physmem.perBankRdBursts::3 356 # Per bank write bursts +system.physmem.perBankRdBursts::4 330 # Per bank write bursts system.physmem.perBankRdBursts::5 328 # Per bank write bursts -system.physmem.perBankRdBursts::6 398 # Per bank write bursts -system.physmem.perBankRdBursts::7 381 # Per bank write bursts -system.physmem.perBankRdBursts::8 343 # Per bank write bursts -system.physmem.perBankRdBursts::9 292 # Per bank write bursts -system.physmem.perBankRdBursts::10 228 # Per bank write bursts -system.physmem.perBankRdBursts::11 284 # Per bank write bursts +system.physmem.perBankRdBursts::6 400 # Per bank write bursts +system.physmem.perBankRdBursts::7 378 # Per bank write bursts +system.physmem.perBankRdBursts::8 340 # Per bank write bursts +system.physmem.perBankRdBursts::9 277 # Per bank write bursts +system.physmem.perBankRdBursts::10 231 # Per bank write bursts +system.physmem.perBankRdBursts::11 276 # Per bank write bursts system.physmem.perBankRdBursts::12 208 # Per bank write bursts -system.physmem.perBankRdBursts::13 469 # Per bank write bursts -system.physmem.perBankRdBursts::14 386 # Per bank write bursts -system.physmem.perBankRdBursts::15 282 # Per bank write bursts +system.physmem.perBankRdBursts::13 466 # Per bank write bursts +system.physmem.perBankRdBursts::14 385 # Per bank write bursts +system.physmem.perBankRdBursts::15 286 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 144377080000 # Total gap between requests +system.physmem.totGap 144620007000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5361 # Read request sizes (log2) +system.physmem.readPktSize::6 5356 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 161 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,305 +186,307 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 508.672783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 294.998238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 425.682375 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 88 26.91% 26.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 53 16.21% 43.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 28 8.56% 51.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 16 4.89% 56.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9 2.75% 59.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 1.83% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 0.92% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 0.92% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 121 37.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 327 # Bytes accessed per row activation -system.physmem.totQLat 28551000 # Total ticks spent queuing -system.physmem.totMemAccLat 139987250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26805000 # Total ticks spent in databus transfers -system.physmem.totBankLat 84631250 # Total ticks spent accessing banks -system.physmem.avgQLat 5325.69 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15786.47 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 1043 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.933845 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.223116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.208962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 368 35.28% 35.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 248 23.78% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 102 9.78% 68.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 58 5.56% 74.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 42 4.03% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 59 5.66% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 17 1.63% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 23 2.21% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 126 12.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1043 # Bytes accessed per row activation +system.physmem.totQLat 35519000 # Total ticks spent queuing +system.physmem.totMemAccLat 135944000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26780000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6631.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26112.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25381.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4274 # Number of row buffer hits during reads +system.physmem.readRowHits 4304 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.72 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26930997.95 # Average gap between requests -system.physmem.pageHitRate 79.72 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 2375113 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3828 # Transaction distribution -system.membus.trans_dist::ReadResp 3825 # Transaction distribution -system.membus.trans_dist::UpgradeReq 150 # Transaction distribution -system.membus.trans_dist::UpgradeResp 150 # Transaction distribution +system.physmem.avgGap 27001494.96 # Average gap between requests +system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 138334279250 # Time in different power states +system.physmem.memoryStateTime::REF 4828980000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1451861250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 2368911 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3823 # Transaction distribution +system.membus.trans_dist::ReadResp 3820 # Transaction distribution +system.membus.trans_dist::UpgradeReq 131 # Transaction distribution +system.membus.trans_dist::UpgradeResp 131 # Transaction distribution system.membus.trans_dist::ReadExReq 1533 # Transaction distribution system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11019 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11019 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11019 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 342912 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 342912 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10971 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10971 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10971 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 342592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6993500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6960500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50706850 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50659869 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 18662333 # Number of BP lookups -system.cpu.branchPred.condPredicted 18662333 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1490477 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11407057 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10802916 # Number of BTB hits +system.cpu.branchPred.lookups 18663045 # Number of BP lookups +system.cpu.branchPred.condPredicted 18663045 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1489785 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11444584 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10797822 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.703796 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1319575 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 23217 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.348750 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1319901 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22895 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 289035036 # number of cpu cycles simulated +system.cpu.numCycles 289523031 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23466628 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206674196 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18662333 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12122491 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54224578 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15529649 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 177872737 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1739 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9780 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22363082 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 227556 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269352720 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.269654 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.757498 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23473938 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206858197 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18663045 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12117723 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54247835 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15552938 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 178336695 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7706 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22368694 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 223698 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269869756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.267902 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.756065 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216567147 80.40% 80.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2849140 1.06% 81.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2312743 0.86% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2640443 0.98% 83.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3223496 1.20% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3388678 1.26% 85.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3828931 1.42% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2559342 0.95% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31982800 11.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 217061517 80.43% 80.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2847740 1.06% 81.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2315002 0.86% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2640494 0.98% 83.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3217056 1.19% 84.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3387561 1.26% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3839682 1.42% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2560696 0.95% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32000008 11.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269352720 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064568 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.715049 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36872291 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 166882879 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41583049 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10237266 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13777235 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336030589 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13777235 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44927552 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116592006 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 33482 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42725844 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51296601 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329644603 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10793 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25973281 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22738118 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382392326 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917644681 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 605892364 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4122807 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269869756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064461 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.714479 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36939117 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167279649 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41594778 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10253994 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13802218 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336245393 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13802218 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45020160 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116775107 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 31642 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42714880 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51525749 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329872428 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 11092 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26167242 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22759273 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382595093 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 918331708 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 606342575 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4133173 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122962876 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2119 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2126 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104910685 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84442386 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30099715 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58118082 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18905602 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322699954 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4280 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260615725 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 114961 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100953398 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 209924725 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3035 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269352720 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.967563 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.344835 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 123165643 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2073 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2073 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105277588 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84554246 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30134710 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58533931 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19035455 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322937953 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4364 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260608849 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 112553 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 101196304 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 210593531 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3119 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269869756 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.965684 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.342187 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143250903 53.18% 53.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55370436 20.56% 73.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34176648 12.69% 86.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19094867 7.09% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10869897 4.04% 97.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4155062 1.54% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1825131 0.68% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476500 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 133276 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143519297 53.18% 53.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55647203 20.62% 73.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34229884 12.68% 86.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19073202 7.07% 93.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10874136 4.03% 97.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4113724 1.52% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1802263 0.67% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 476846 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 133201 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269352720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269869756 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 130941 4.84% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2275620 84.10% 88.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 299199 11.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 125646 4.63% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2288183 84.39% 89.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 297636 10.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210799 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162097443 62.20% 62.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 790400 0.30% 62.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035783 2.70% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1447528 0.56% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65478586 25.12% 91.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22555186 8.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210826 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162119129 62.21% 62.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 788294 0.30% 62.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035677 2.70% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1444684 0.55% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65441941 25.11% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22568298 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260615725 # Type of FU issued -system.cpu.iq.rate 0.901675 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2705760 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010382 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788512519 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420334227 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255242293 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4892372 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3608187 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2352192 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259648600 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2462086 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18920241 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260608849 # Type of FU issued +system.cpu.iq.rate 0.900132 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2711465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010404 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 789025856 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420800342 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255248449 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4885616 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3622403 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2349194 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259650836 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2458652 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18874838 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27792799 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26588 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 290410 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9583998 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27904659 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26471 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 289699 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9618993 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49921 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13777235 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85064772 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5446513 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322704234 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 135340 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84442386 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30099715 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2049 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2678194 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12950 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 290410 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 639185 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 902051 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1541236 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258833919 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64703526 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1781806 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13802218 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85051562 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5443180 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322942317 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 133815 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84554246 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30134710 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2043 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2682047 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14716 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 289699 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 640019 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 900364 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1540383 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258834349 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64663337 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1774500 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87053484 # number of memory reference insts executed -system.cpu.iew.exec_branches 14272898 # Number of branches executed -system.cpu.iew.exec_stores 22349958 # Number of stores executed -system.cpu.iew.exec_rate 0.895511 # Inst execution rate -system.cpu.iew.wb_sent 258192676 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257594485 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206043233 # num instructions producing a value -system.cpu.iew.wb_consumers 369200904 # num instructions consuming a value +system.cpu.iew.exec_refs 87028906 # number of memory reference insts executed +system.cpu.iew.exec_branches 14271418 # Number of branches executed +system.cpu.iew.exec_stores 22365569 # Number of stores executed +system.cpu.iew.exec_rate 0.894003 # Inst execution rate +system.cpu.iew.wb_sent 258197839 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257597643 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206027195 # num instructions producing a value +system.cpu.iew.wb_consumers 369217293 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.891222 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.558079 # average fanout of values written-back +system.cpu.iew.wb_rate 0.889731 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.558011 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101415579 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101647922 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1491917 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255575485 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.866137 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.656618 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1490935 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 256067538 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.864473 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.651889 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156360594 61.18% 61.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57109316 22.35% 83.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13985683 5.47% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12037857 4.71% 93.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4182593 1.64% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2963821 1.16% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 909345 0.36% 96.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1046624 0.41% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6979652 2.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156617936 61.16% 61.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57255270 22.36% 83.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14082261 5.50% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12088609 4.72% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4189643 1.64% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2964480 1.16% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 903129 0.35% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1051661 0.41% 97.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6914549 2.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255575485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 256067538 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -495,240 +497,277 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6979652 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 133863962 60.47% 61.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.35% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 1352943 0.61% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction +system.cpu.commit.bw_lim_events 6914549 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571374796 # The number of ROB reads -system.cpu.rob.rob_writes 659361249 # The number of ROB writes -system.cpu.timesIdled 5927783 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19682316 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 572164295 # The number of ROB reads +system.cpu.rob.rob_writes 659850863 # The number of ROB writes +system.cpu.timesIdled 5930649 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19653275 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.188479 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.188479 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456938 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456938 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451403378 # number of integer regfile reads -system.cpu.int_regfile_writes 234040975 # number of integer regfile writes -system.cpu.fp_regfile_reads 3219859 # number of floating regfile reads -system.cpu.fp_regfile_writes 2011879 # number of floating regfile writes -system.cpu.cc_regfile_reads 102824885 # number of cc regfile reads -system.cpu.cc_regfile_writes 59817361 # number of cc regfile writes -system.cpu.misc_regfile_reads 133392985 # number of misc regfile reads +system.cpu.cpi 2.192174 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.192174 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456168 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456168 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 451375343 # number of integer regfile reads +system.cpu.int_regfile_writes 234032598 # number of integer regfile writes +system.cpu.fp_regfile_reads 3213912 # number of floating regfile reads +system.cpu.fp_regfile_writes 2009037 # number of floating regfile writes +system.cpu.cc_regfile_reads 102846049 # number of cc regfile reads +system.cpu.cc_regfile_writes 59805449 # number of cc regfile writes +system.cpu.misc_regfile_reads 133386978 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3846371 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7125 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 15 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 150 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 150 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13184 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4308 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17492 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 417024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 545664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 545664 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 9664 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4430500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 3852301 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7156 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7153 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13245 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4286 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17531 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 419584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 548608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 548608 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8512 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4433000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10573999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10626750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3437150 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3450631 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4547 # number of replacements -system.cpu.icache.tags.tagsinuse 1629.451963 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22354297 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6517 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3430.151450 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4592 # number of replacements +system.cpu.icache.tags.tagsinuse 1628.049417 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22359876 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6557 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3410.077169 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1629.451963 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.795631 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.795631 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1970 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 807 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.961914 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 44732829 # Number of tag accesses -system.cpu.icache.tags.data_accesses 44732829 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22354297 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22354297 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22354297 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22354297 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22354297 # number of overall hits -system.cpu.icache.overall_hits::total 22354297 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8784 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8784 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8784 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8784 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8784 # number of overall misses -system.cpu.icache.overall_misses::total 8784 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 365846249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 365846249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 365846249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 365846249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 365846249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 365846249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22363081 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22363081 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22363081 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22363081 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22363081 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22363081 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000393 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000393 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000393 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000393 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000393 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000393 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41649.163138 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41649.163138 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41649.163138 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41649.163138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41649.163138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41649.163138 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 800 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1628.049417 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.794946 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.794946 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 810 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 44744077 # Number of tag accesses +system.cpu.icache.tags.data_accesses 44744077 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22359876 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22359876 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22359876 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22359876 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22359876 # number of overall hits +system.cpu.icache.overall_hits::total 22359876 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8818 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8818 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8818 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8818 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8818 # number of overall misses +system.cpu.icache.overall_misses::total 8818 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 365022750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 365022750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 365022750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 365022750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 365022750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 365022750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22368694 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22368694 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22368694 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22368694 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22368694 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22368694 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000394 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000394 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000394 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000394 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000394 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000394 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41395.185983 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41395.185983 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41395.185983 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41395.185983 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 701 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.733333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2116 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2116 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2116 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2116 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2116 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2116 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6668 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6668 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6668 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6668 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6668 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6668 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 272166001 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 272166001 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 272166001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 272166001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 272166001 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 272166001 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000298 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000298 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000298 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40816.736803 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40816.736803 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40816.736803 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40816.736803 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40816.736803 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40816.736803 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2129 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2129 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2129 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2129 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2129 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2129 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6689 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6689 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6689 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6689 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6689 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6689 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 269490250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 269490250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 269490250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 269490250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 269490250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 269490250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40288.570788 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40288.570788 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2545.733703 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3149 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3831 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.821979 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2549.629926 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3205 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3824 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.838128 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.666971 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2237.371026 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 306.695706 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000051 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068279 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009360 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.077690 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3831 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 881 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 143 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 1.731773 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2236.346523 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 311.551630 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068248 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009508 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.077809 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3824 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 895 # 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mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.517694 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978066 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.625555 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55532.410136 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62420.745921 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56305.388438 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55488.258317 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55488.258317 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56232.315820 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57654.042989 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56750.512964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56232.315820 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57654.042989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56750.512964 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54937.051533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54937.051533 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55532.410136 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56573.394495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55532.410136 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56573.394495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1432.023881 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66143701 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33154.737343 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 59 # number of replacements +system.cpu.dcache.tags.tagsinuse 1435.036669 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66148000 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2003 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33024.463305 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1432.023881 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349615 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349615 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 427 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1393 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.473145 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 132294203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 132294203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45629460 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45629460 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514040 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514040 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66143500 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66143500 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66143500 # number of overall hits -system.cpu.dcache.overall_hits::total 66143500 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 913 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 913 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1691 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1691 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2604 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2604 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2604 # number of overall misses -system.cpu.dcache.overall_misses::total 2604 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59632801 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59632801 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 113805150 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 113805150 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 173437951 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 173437951 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 173437951 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 173437951 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45630373 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45630373 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1435.036669 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.350351 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.350351 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 430 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 132302857 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 132302857 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45633758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45633758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514059 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514059 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66147817 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66147817 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66147817 # number of overall hits +system.cpu.dcache.overall_hits::total 66147817 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1672 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1672 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses +system.cpu.dcache.overall_misses::total 2610 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59941301 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59941301 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 112492631 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 112492631 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 172433932 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 172433932 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 172433932 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 172433932 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45634696 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45634696 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66146104 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66146104 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66146104 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66146104 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 66150427 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66150427 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66150427 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66150427 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65315.225630 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65315.225630 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67300.502661 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67300.502661 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66604.435868 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66604.435868 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66604.435868 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66604.435868 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 319 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63903.305970 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63903.305970 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67280.281699 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67280.281699 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66066.640613 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66066.640613 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 322 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 15 # number of writebacks -system.cpu.dcache.writebacks::total 15 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 455 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 455 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 456 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 456 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 456 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 456 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 458 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1690 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1690 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33615250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33615250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109709600 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 109709600 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143324850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 143324850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143324850 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 143324850 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 13 # number of writebacks +system.cpu.dcache.writebacks::total 13 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 470 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 470 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 472 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 472 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 472 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 472 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 468 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 468 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1670 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1670 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32985750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32985750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108417619 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 108417619 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 141403369 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 141403369 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 141403369 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 141403369 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000081 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000081 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73395.742358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73395.742358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64916.923077 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64916.923077 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66724.790503 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66724.790503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66724.790503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66724.790503 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70482.371795 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70482.371795 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64920.729940 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64920.729940 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 5a8c9de17..5240cde6c 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1414135 # Simulator instruction rate (inst/s) -host_op_rate 2370219 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1406875667 # Simulator tick rate (ticks/s) -host_mem_usage 267896 # Number of bytes of host memory used -host_seconds 93.39 # Real time elapsed on the host +host_inst_rate 1131336 # Simulator instruction rate (inst/s) +host_op_rate 1896222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1125528252 # Simulator tick rate (ticks/s) +host_mem_usage 303676 # Number of bytes of host memory used +host_seconds 116.74 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -66,5 +66,40 @@ system.cpu.num_busy_cycles 262786559 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 12326938 # Number of branches fetched +system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction +system.cpu.op_class::IntAlu 133863963 60.47% 61.00% # Class of executed instruction +system.cpu.op_class::IntMult 772953 0.35% 61.35% # Class of executed instruction +system.cpu.op_class::IntDiv 7031501 3.18% 64.53% # Class of executed instruction +system.cpu.op_class::FloatAdd 1352943 0.61% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction +system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 221363385 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index b4342fe40..9d2ef868e 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957000 # Number of ticks simulated final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 770398 # Simulator instruction rate (inst/s) -host_op_rate 1291257 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1463865173 # Simulator tick rate (ticks/s) -host_mem_usage 276604 # Number of bytes of host memory used -host_seconds 171.43 # Real time elapsed on the host +host_inst_rate 652190 # Simulator instruction rate (inst/s) +host_op_rate 1093130 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1239252699 # Simulator tick rate (ticks/s) +host_mem_usage 313428 # Number of bytes of host memory used +host_seconds 202.50 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -74,6 +74,41 @@ system.cpu.num_busy_cycles 501907914 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 12326938 # Number of branches fetched +system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction +system.cpu.op_class::IntAlu 133863963 60.47% 61.00% # Class of executed instruction +system.cpu.op_class::IntMult 772953 0.35% 61.35% # Class of executed instruction +system.cpu.op_class::IntDiv 7031501 3.18% 64.53% # Class of executed instruction +system.cpu.op_class::FloatAdd 1352943 0.61% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction +system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 221363385 # Class of executed instruction system.cpu.icache.tags.replacements 2836 # number of replacements system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks. |