diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref')
5 files changed, 1549 insertions, 1520 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 5fb393485..11356e644 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.051911 # Nu sim_ticks 51910606500 # Number of ticks simulated final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 229005 # Simulator instruction rate (inst/s) -host_op_rate 229005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 129351336 # Simulator tick rate (ticks/s) -host_mem_usage 295204 # Number of bytes of host memory used -host_seconds 401.31 # Real time elapsed on the host +host_inst_rate 339215 # Simulator instruction rate (inst/s) +host_op_rate 339215 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191602600 # Simulator tick rate (ticks/s) +host_mem_usage 303192 # Number of bytes of host memory used +host_seconds 270.93 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -663,6 +663,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 32052 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 14007 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 13900 # Transaction distribution @@ -678,15 +684,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1161728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 32052 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32052 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 32052 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 32052 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 16133000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index f7c0c31d6..cc5b93144 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.021919 # Nu sim_ticks 21919473500 # Number of ticks simulated final_tick 21919473500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134628 # Simulator instruction rate (inst/s) -host_op_rate 134628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35055621 # Simulator tick rate (ticks/s) -host_mem_usage 296224 # Number of bytes of host memory used -host_seconds 625.28 # Real time elapsed on the host +host_inst_rate 199769 # Simulator instruction rate (inst/s) +host_op_rate 199769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52017673 # Simulator tick rate (ticks/s) +host_mem_usage 302932 # Number of bytes of host memory used +host_seconds 421.39 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -971,6 +971,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 23293 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9635 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 11922 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 9527 # Transaction distribution @@ -986,15 +992,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 881024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 23293 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 23293 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 23293 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 23293 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 11754500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 396e2f8dd..13ae4452a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.130773 # Number of seconds simulated -sim_ticks 130772636500 # Number of ticks simulated -final_tick 130772636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 130772642500 # Number of ticks simulated +final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167747 # Simulator instruction rate (inst/s) -host_op_rate 176832 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 127303889 # Simulator tick rate (ticks/s) -host_mem_usage 312696 # Number of bytes of host memory used -host_seconds 1027.25 # Real time elapsed on the host +host_inst_rate 233615 # Simulator instruction rate (inst/s) +host_op_rate 246267 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 177290947 # Simulator tick rate (ticks/s) +host_mem_usage 321196 # Number of bytes of host memory used +host_seconds 737.62 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -22,12 +22,12 @@ system.physmem.num_reads::cpu.inst 2158 # Nu system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 835894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 835894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3866 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 130772543000 # Total gap between requests +system.physmem.totGap 130772548000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # By system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation -system.physmem.totQLat 28055750 # Total ticks spent queuing -system.physmem.totMemAccLat 100543250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 27654500 # Total ticks spent queuing +system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7257.05 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26007.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s @@ -220,35 +220,35 @@ system.physmem.readRowHits 2957 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33826317.38 # Average gap between requests +system.physmem.avgGap 33826318.68 # Average gap between requests system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3568801635 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75331661250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 87462680535 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.826718 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 125318913500 # Time in different power states +system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.826558 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1084715250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3564422325 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75335511000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 87460741830 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.811822 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 125325774500 # Time in different power states +system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.811714 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1078159500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 49732170 # Number of BP lookups system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted @@ -377,7 +377,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 261545273 # number of cpu cycles simulated +system.cpu.numCycles 261545285 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed @@ -386,15 +386,15 @@ system.cpu.discardedOps 11660914 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.517808 # CPI: cycles per instruction system.cpu.ipc 0.658845 # IPC: instructions per cycle -system.cpu.tickCycles 255251954 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6293319 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.707601 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707601 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id @@ -430,14 +430,14 @@ system.cpu.dcache.demand_misses::cpu.data 2442 # n system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses system.cpu.dcache.overall_misses::total 2443 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58025500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58025500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126322500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126322500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184348000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184348000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184348000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184348000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73079.974811 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73079.974811 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76652.002427 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76652.002427 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75490.581491 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75490.581491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75459.680720 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75459.680720 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809 system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51768000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51768000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85075000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85075000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136843000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 136843000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136913000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 136913000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -518,24 +518,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72810.126582 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72810.126582 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77481.785064 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77481.785064 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75645.660586 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75645.660586 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75642.541436 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75642.541436 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2888 # number of replacements -system.cpu.icache.tags.tagsinuse 1423.991727 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991727 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id @@ -559,12 +559,12 @@ system.cpu.icache.demand_misses::cpu.inst 4685 # n system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses system.cpu.icache.overall_misses::total 4685 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 199910500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 199910500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 199910500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 199910500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 199910500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 199910500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses @@ -577,12 +577,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42670.330843 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42670.330843 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42670.330843 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42670.330843 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42671.611526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42671.611526 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4685 system.cpu.icache.demand_mshr_misses::total 4685 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4685 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4685 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195226500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 195226500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195226500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 195226500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195226500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 195226500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195232500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 195232500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195232500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 195232500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195232500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 195232500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41670.544290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41670.544290 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41671.824973 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2000.604150 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2000.604140 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5191 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2784 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.864583 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029284 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756657 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818208 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029285 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756648 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818207 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045983 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy @@ -664,18 +664,18 @@ system.cpu.l2cache.demand_misses::total 3883 # nu system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses system.cpu.l2cache.overall_misses::total 3883 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83342500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 83342500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161697500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 161697500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49918000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 49918000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 161697500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 133260500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 294958000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 161697500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 133260500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 294958000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 83327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161329500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 161329500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49900500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49900500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 161329500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 133228000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294557500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) @@ -702,18 +702,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.597844 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461259 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.597844 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76461.009174 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76461.009174 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74825.312355 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74825.312355 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78984.177215 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78984.177215 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75961.370075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75961.370075 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -744,18 +744,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3867 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139969500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139969500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42776000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42776000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139969500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115218500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 255188000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139969500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115218500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 255188000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72427500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72427500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139601500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139601500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42758500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42758500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139601500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses @@ -768,19 +768,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66461.009174 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66461.009174 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64830.708661 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64830.708661 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69216.828479 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69216.828479 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2586 # Transaction distribution @@ -796,14 +802,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 416640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 9425 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.083820 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.277132 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9425 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8635 91.62% 91.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 790 8.38% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 9425 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4728500 # Layer occupancy (ticks) @@ -831,9 +837,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3866 # Request fanout histogram -system.membus.reqLayer0.occupancy 4535000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20543000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index b0d8b3c34..7a60aaca0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085022 # Number of seconds simulated -sim_ticks 85021523000 # Number of ticks simulated -final_tick 85021523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085039 # Number of seconds simulated +sim_ticks 85038866000 # Number of ticks simulated +final_tick 85038866000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136979 # Simulator instruction rate (inst/s) -host_op_rate 144399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67591393 # Simulator tick rate (ticks/s) -host_mem_usage 315696 # Number of bytes of host memory used -host_seconds 1257.88 # Real time elapsed on the host +host_inst_rate 124768 # Simulator instruction rate (inst/s) +host_op_rate 131526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61578459 # Simulator tick rate (ticks/s) +host_mem_usage 316956 # Number of bytes of host memory used +host_seconds 1380.98 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 126976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71104 # Number of bytes read from this memory -system.physmem.bytes_read::total 245888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 126976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 126976 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1984 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1111 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3842 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1493457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 562305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 836306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2892068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1493457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1493457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1493457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 562305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 836306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2892068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3842 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71424 # Number of bytes read from this memory +system.physmem.bytes_read::total 246336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1116 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3849 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1493905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 562943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 839898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2896746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1493905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1493905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1493905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 562943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 839898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2896746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3849 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3842 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3849 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 245888 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 246336 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 245888 # Total read bytes from the system interface side +system.physmem.bytesReadSys 246336 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 309 # Per bank write bursts -system.physmem.perBankRdBursts::1 220 # Per bank write bursts +system.physmem.perBankRdBursts::1 223 # Per bank write bursts system.physmem.perBankRdBursts::2 134 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts -system.physmem.perBankRdBursts::4 307 # Per bank write bursts +system.physmem.perBankRdBursts::3 318 # Per bank write bursts +system.physmem.perBankRdBursts::4 300 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts -system.physmem.perBankRdBursts::7 232 # Per bank write bursts +system.physmem.perBankRdBursts::7 237 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts system.physmem.perBankRdBursts::9 219 # Per bank write bursts system.physmem.perBankRdBursts::10 292 # Per bank write bursts system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 193 # Per bank write bursts +system.physmem.perBankRdBursts::12 191 # Per bank write bursts system.physmem.perBankRdBursts::13 211 # Per bank write bursts system.physmem.perBankRdBursts::14 211 # Per bank write bursts system.physmem.perBankRdBursts::15 194 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85021379500 # Total gap between requests +system.physmem.totGap 85038722500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3842 # Read request sizes (log2) +system.physmem.readPktSize::6 3849 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,15 +94,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 770 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.174026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 198.484323 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.262764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 239 31.04% 31.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194 25.19% 56.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 82 10.65% 66.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 86 11.17% 78.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 28 3.64% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 38 4.94% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15 1.95% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 2.08% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 72 9.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 770 # Bytes accessed per row activation -system.physmem.totQLat 41378240 # Total ticks spent queuing -system.physmem.totMemAccLat 113415740 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19210000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10769.97 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 773 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 316.357050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 198.451466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 308.377497 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 239 30.92% 30.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 194 25.10% 56.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 10.87% 66.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 87 11.25% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 29 3.75% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 4.79% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 16 2.07% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13 1.68% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 74 9.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 773 # Bytes accessed per row activation +system.physmem.totQLat 41463141 # Total ticks spent queuing +system.physmem.totMemAccLat 113631891 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10772.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29519.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29522.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.83 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3065 # Number of row buffer hits during reads +system.physmem.readRowHits 3069 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.78 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.73 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22129458.49 # Average gap between requests -system.physmem.pageHitRate 79.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2766960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1509750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22093718.50 # Average gap between requests +system.physmem.pageHitRate 79.73 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2789640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1522125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2338310430 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48959844750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56871567930 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.933066 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81449206260 # Time in different power states -system.physmem_0.memoryStateTime::REF 2838940000 # Time in different power states +system.physmem_0.refreshEnergy 5553983760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2338576335 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48968955000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56882066460 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.934025 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81466129254 # Time in different power states +system.physmem_0.memoryStateTime::REF 2839460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 731844740 # Time in different power states +system.physmem_0.memoryStateTime::ACT 731738246 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3039120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1658250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13579800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3031560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1654125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13525200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2293221150 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48999396750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56863861710 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.842424 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81513735655 # Time in different power states -system.physmem_1.memoryStateTime::REF 2838940000 # Time in different power states +system.physmem_1.refreshEnergy 5553983760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2304071955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48999213750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56875480350 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.856680 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81513506905 # Time in different power states +system.physmem_1.memoryStateTime::REF 2839460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 665661845 # Time in different power states +system.physmem_1.memoryStateTime::ACT 681039595 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85912132 # Number of BP lookups -system.cpu.branchPred.condPredicted 68393043 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6015535 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40101121 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39014567 # Number of BTB hits +system.cpu.branchPred.lookups 85929659 # Number of BP lookups +system.cpu.branchPred.condPredicted 68408036 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6017804 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40110757 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39021888 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.290465 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3703090 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81902 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.285344 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3703815 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81895 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170043047 # number of cpu cycles simulated +system.cpu.numCycles 170077733 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5613517 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349250630 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85912132 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42717657 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158263984 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12044969 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5627528 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349301730 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85929659 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42725703 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158283885 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12049307 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2395 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78950646 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18010 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169904018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150531 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.047148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2380 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78962015 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18924 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169940212 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047263 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17361437 10.22% 10.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30204201 17.78% 28.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31835536 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90502844 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17375065 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30210489 17.78% 28.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31838895 18.74% 46.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90515763 53.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169904018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 169940212 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.505238 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.053895 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17563904 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17112948 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122657441 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6722163 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5847562 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11134700 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190128 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306600022 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27639979 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5847562 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37746058 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8470500 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 579781 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108923622 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8336495 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278650706 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13412569 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3051463 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842712 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2185705 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 36039 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26489 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483080897 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196921555 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297573893 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006747 # Number of floating rename lookups +system.cpu.fetch.rate 2.053777 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17579546 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17112098 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122676977 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6721861 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5849730 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11135516 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190121 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306633664 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27649172 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5849730 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37767470 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8469466 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579515 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108936835 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8337196 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278676031 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13415385 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3051308 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 841767 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187025 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 37328 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26465 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483141060 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1197017326 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297598208 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006154 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190103968 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23523 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23430 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13336341 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34142087 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476532 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2549378 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1793123 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264810332 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45855 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214902707 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5190620 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 83220233 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219925371 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 639 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169904018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264848 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017464 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190164131 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23534 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23437 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13334158 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34140467 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476937 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2547302 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1809047 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264833552 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45866 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214914716 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5193890 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 83243464 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219964835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169940212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017441 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52834646 31.10% 31.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36093194 21.24% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65784220 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13574325 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570253 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47194 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 186 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52857789 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36101949 21.24% 52.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65794996 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13566772 7.98% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571259 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47259 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 188 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169904018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169940212 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35605027 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152712 0.28% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35605031 66.12% 66.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152953 0.28% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available @@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1062 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35741 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35733 0.07% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 238 0.00% 66.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 1038 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34404 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1040 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34389 0.06% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14078476 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3945873 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14077055 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3945216 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167344168 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918970 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167357469 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918949 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -523,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33018 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165202 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165195 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245712 0.11% 78.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460547 0.21% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460561 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206706 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32006913 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373527 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32005826 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13373316 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214902707 # Type of FU issued -system.cpu.iq.rate 1.263814 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53854783 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250601 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654801069 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 346070765 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204597399 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3953766 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2012584 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806443 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266623022 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2134468 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1601145 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214914716 # Type of FU issued +system.cpu.iq.rate 1.263626 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53852922 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250578 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654863168 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 346117768 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204606131 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3953288 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011882 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806358 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266633604 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2134034 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600995 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6245943 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7536 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7067 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1831898 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6244323 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7621 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6899 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832303 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25713 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 795 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25728 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 844 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5847562 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5681846 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37059 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264872174 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5849730 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5682254 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37001 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264895393 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34142087 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476532 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23447 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3919 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29973 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7067 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3232804 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3246682 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6479486 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207521845 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30720947 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7380862 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34140467 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476937 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23458 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3889 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29998 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6899 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3234969 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247770 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6482739 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207531016 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30721231 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7383700 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15987 # number of nop insts executed -system.cpu.iew.exec_refs 43860767 # number of memory reference insts executed -system.cpu.iew.exec_branches 44934593 # Number of branches executed -system.cpu.iew.exec_stores 13139820 # Number of stores executed -system.cpu.iew.exec_rate 1.220408 # Inst execution rate -system.cpu.iew.wb_sent 206738836 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206403842 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129472696 # num instructions producing a value -system.cpu.iew.wb_consumers 221699614 # num instructions consuming a value +system.cpu.iew.exec_nop 15975 # number of nop insts executed +system.cpu.iew.exec_refs 43860800 # number of memory reference insts executed +system.cpu.iew.exec_branches 44937472 # Number of branches executed +system.cpu.iew.exec_stores 13139569 # Number of stores executed +system.cpu.iew.exec_rate 1.220213 # Inst execution rate +system.cpu.iew.wb_sent 206747617 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206412489 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129477272 # num instructions producing a value +system.cpu.iew.wb_consumers 221702085 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.213833 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584001 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213636 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584015 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69532937 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69549191 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5840613 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158463001 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146327 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646694 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5842881 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158496522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646497 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73683575 46.50% 46.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41276323 26.05% 72.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22553918 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9626893 6.08% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3550160 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2147765 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1281178 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 986541 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3356648 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73710350 46.51% 46.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41283484 26.05% 72.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22554549 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9626760 6.07% 92.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3551822 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2145509 1.35% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1280291 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 989155 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3354602 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158463001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158496522 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,381 +655,380 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3356648 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406284431 # The number of ROB reads -system.cpu.rob.rob_writes 513821512 # The number of ROB writes -system.cpu.timesIdled 3435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 139029 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3354602 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 406336252 # The number of ROB reads +system.cpu.rob.rob_writes 513856795 # The number of ROB writes +system.cpu.timesIdled 3529 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 137521 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986884 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986884 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013291 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013291 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218956389 # number of integer regfile reads -system.cpu.int_regfile_writes 114512069 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904391 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441624 # number of floating regfile writes -system.cpu.cc_regfile_reads 709567724 # number of cc regfile reads -system.cpu.cc_regfile_writes 229536137 # number of cc regfile writes -system.cpu.misc_regfile_reads 59314172 # number of misc regfile reads +system.cpu.cpi 0.987085 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.987085 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013084 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013084 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218963852 # number of integer regfile reads +system.cpu.int_regfile_writes 114515225 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904259 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441612 # number of floating regfile writes +system.cpu.cc_regfile_reads 709595430 # number of cc regfile reads +system.cpu.cc_regfile_writes 229551730 # number of cc regfile writes +system.cpu.misc_regfile_reads 59313283 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72862 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.418427 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41115433 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73374 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.354254 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 72876 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.418230 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41115950 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73388 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.254401 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 506092500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.418427 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.418230 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998864 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998864 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82529738 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82529738 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28729196 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28729196 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82530918 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82530918 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28729730 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28729730 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341303 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341303 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22149 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22149 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41070516 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41070516 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41070877 # number of overall hits -system.cpu.dcache.overall_hits::total 41070877 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89406 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89406 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 41071033 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41071033 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41071394 # number of overall hits +system.cpu.dcache.overall_hits::total 41071394 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89456 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89456 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22984 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22984 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112373 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112373 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112490 # number of overall misses -system.cpu.dcache.overall_misses::total 112490 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 857195000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 857195000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 240069999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 240069999 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 112440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112556 # number of overall misses +system.cpu.dcache.overall_misses::total 112556 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 857049000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 857049000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 246637999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 246637999 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 2309500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1097264999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1097264999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1097264999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1097264999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28818602 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28818602 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1103686999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1103686999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1103686999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1103686999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28819186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28819186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 478 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 478 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 477 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 477 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41182889 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41182889 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41183367 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41183367 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003102 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003102 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244770 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.244770 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41183473 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41183473 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41183950 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41183950 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001859 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001859 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.243187 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.243187 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011558 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002729 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002729 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002731 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002731 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9587.667494 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9587.667494 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10452.823573 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10452.823573 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9580.676534 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9580.676534 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10730.856204 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10730.856204 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8916.988417 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8916.988417 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9764.489682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9764.489682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9754.333710 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9754.333710 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9815.786188 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9815.786188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9805.670058 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9805.670058 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10364 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11592 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 866 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 859 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 11.967667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 13.494761 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64850 # number of writebacks -system.cpu.dcache.writebacks::total 64850 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24708 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24708 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14405 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 64866 # number of writebacks +system.cpu.dcache.writebacks::total 64866 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24759 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24759 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14406 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14406 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39113 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64698 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64698 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8562 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8562 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73260 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73260 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73374 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73374 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 560329500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 560329500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85295999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85295999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 970000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 970000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 645625499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 645625499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 646595499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 646595499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 39165 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39165 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39165 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39165 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64697 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64697 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8578 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73275 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73275 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73388 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73388 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 560382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 560382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86241499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86241499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 646623999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 646623999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 647585999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 647585999 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.238494 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.238494 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000694 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000694 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.236897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.236897 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8660.692757 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8660.692757 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9962.158257 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9962.158257 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8508.771930 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8508.771930 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8812.796874 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8812.796874 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8812.324515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8812.324515 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8661.645826 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8661.645826 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10053.800303 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10053.800303 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8824.619570 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8824.619570 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8824.140173 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8824.140173 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54433 # number of replacements -system.cpu.icache.tags.tagsinuse 510.603635 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78892635 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54945 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1435.847393 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84266921500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.603635 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 54478 # number of replacements +system.cpu.icache.tags.tagsinuse 510.603674 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78903878 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54990 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1434.876850 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84285313500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.603674 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997273 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997273 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157956195 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157956195 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78892635 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78892635 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78892635 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78892635 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78892635 # number of overall hits -system.cpu.icache.overall_hits::total 78892635 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57990 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57990 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57990 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57990 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57990 # number of overall misses -system.cpu.icache.overall_misses::total 57990 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 602731956 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 602731956 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 602731956 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 602731956 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 602731956 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 602731956 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78950625 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78950625 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78950625 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78950625 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78950625 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78950625 # 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average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62631.552419 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69799.196787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64592.090809 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62631.552419 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69799.196787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37953.552819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53914.467091 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035037 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39957.037394 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72419.831224 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72419.831224 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62471.284635 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62471.284635 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67488.258317 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67488.258317 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62471.284635 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69050.802139 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64272.045371 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62471.284635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69050.802139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54730.918408 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 119685 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64850 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2169 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54945 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 255732 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 127373 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 649 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 119730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64866 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54990 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 64740 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217447 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 373421 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8846336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12362816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2169 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 257783 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.008414 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.091342 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 156105 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217502 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 373607 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3519360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8848256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12367616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2111 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 257843 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.084059 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.277477 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 255614 99.16% 99.16% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2169 0.84% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 236169 91.59% 91.59% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 21674 8.41% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 257783 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 192657000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 257843 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 192732000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82431971 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82511447 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110065491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110086990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3609 # Transaction distribution -system.membus.trans_dist::ReadExReq 233 # Transaction distribution -system.membus.trans_dist::ReadExResp 233 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3609 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 245888 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3612 # Transaction distribution +system.membus.trans_dist::ReadExReq 237 # Transaction distribution +system.membus.trans_dist::ReadExResp 237 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3612 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7698 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7698 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 246336 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3842 # Request fanout histogram +system.membus.snoop_fanout::samples 3849 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3842 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3849 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3842 # Request fanout histogram -system.membus.reqLayer0.occupancy 4994667 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3849 # Request fanout histogram +system.membus.reqLayer0.occupancy 5019167 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20261553 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20293808 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index cd6ba3bb4..fda8a8b37 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.079147 # Number of seconds simulated -sim_ticks 79147317000 # Number of ticks simulated -final_tick 79147317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.079190 # Number of seconds simulated +sim_ticks 79190347500 # Number of ticks simulated +final_tick 79190347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70947 # Simulator instruction rate (inst/s) -host_op_rate 118914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42517019 # Simulator tick rate (ticks/s) -host_mem_usage 343896 # Number of bytes of host memory used -host_seconds 1861.54 # Real time elapsed on the host +host_inst_rate 91850 # Simulator instruction rate (inst/s) +host_op_rate 153949 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55073733 # Simulator tick rate (ticks/s) +host_mem_usage 350132 # Number of bytes of host memory used +host_seconds 1437.90 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory -system.physmem.bytes_read::total 346304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5411 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2797012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1578424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4375436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2797012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2797012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2797012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1578424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4375436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5413 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125120 # Number of bytes read from this memory +system.physmem.bytes_read::total 345920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1955 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2788219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1579991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4368209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2788219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2788219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2788219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1579991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4368209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5405 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 346304 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 345920 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side +system.physmem.bytesReadSys 345920 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 303 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 299 # Per bank write bursts -system.physmem.perBankRdBursts::1 344 # Per bank write bursts +system.physmem.perBankRdBursts::1 345 # Per bank write bursts system.physmem.perBankRdBursts::2 461 # Per bank write bursts -system.physmem.perBankRdBursts::3 354 # Per bank write bursts -system.physmem.perBankRdBursts::4 343 # Per bank write bursts -system.physmem.perBankRdBursts::5 326 # Per bank write bursts -system.physmem.perBankRdBursts::6 401 # Per bank write bursts -system.physmem.perBankRdBursts::7 385 # Per bank write bursts -system.physmem.perBankRdBursts::8 338 # Per bank write bursts +system.physmem.perBankRdBursts::3 350 # Per bank write bursts +system.physmem.perBankRdBursts::4 340 # Per bank write bursts +system.physmem.perBankRdBursts::5 325 # Per bank write bursts +system.physmem.perBankRdBursts::6 403 # Per bank write bursts +system.physmem.perBankRdBursts::7 384 # Per bank write bursts +system.physmem.perBankRdBursts::8 342 # Per bank write bursts system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 237 # Per bank write bursts -system.physmem.perBankRdBursts::11 285 # Per bank write bursts -system.physmem.perBankRdBursts::12 221 # Per bank write bursts -system.physmem.perBankRdBursts::13 466 # Per bank write bursts -system.physmem.perBankRdBursts::14 386 # Per bank write bursts -system.physmem.perBankRdBursts::15 284 # Per bank write bursts +system.physmem.perBankRdBursts::10 239 # Per bank write bursts +system.physmem.perBankRdBursts::11 284 # Per bank write bursts +system.physmem.perBankRdBursts::12 217 # Per bank write bursts +system.physmem.perBankRdBursts::13 467 # Per bank write bursts +system.physmem.perBankRdBursts::14 385 # Per bank write bursts +system.physmem.perBankRdBursts::15 283 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 79147284500 # Total gap between requests +system.physmem.totGap 79190259000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5413 # Read request sizes (log2) +system.physmem.readPktSize::6 5405 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,313 +186,313 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.266907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.102740 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.449427 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 425 38.32% 38.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 245 22.09% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 103 9.29% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 5.23% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 62 5.59% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 4.69% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.16% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.62% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 122 11.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1109 # Bytes accessed per row activation -system.physmem.totQLat 39588000 # Total ticks spent queuing -system.physmem.totMemAccLat 141044250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7313.50 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 4998.15 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26056.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.bytesPerActivate::samples 1097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 314.107566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.474477 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.278271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 419 38.20% 38.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 241 21.97% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97 8.84% 69.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 5.74% 74.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 5.74% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 54 4.92% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 22 2.01% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 1.55% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 121 11.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1097 # Bytes accessed per row activation +system.physmem.totQLat 39419500 # Total ticks spent queuing +system.physmem.totMemAccLat 140763250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7293.15 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26043.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.32 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4302 # Number of row buffer hits during reads +system.physmem.readRowHits 4299 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 14621704.14 # Average gap between requests -system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4951800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2701875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22721400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 14651296.76 # Average gap between requests +system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22565400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2476092825 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 45316483500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 52992463800 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.540663 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 75384383500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states +system.physmem_0.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2473079805 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 45342485250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 53017734165 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.530615 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 75427842500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2644200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1120221500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1114667500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3432240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1872750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19484400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3402000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1856250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19305000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2281510215 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 45487170000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 52962982005 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.168172 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 75669637750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states +system.physmem_1.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2272318965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 45518583000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 52987520415 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.149179 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 75723788000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2644200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 834967250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 820354000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20588400 # Number of BP lookups -system.cpu.branchPred.condPredicted 20588400 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1327971 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12696525 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12013993 # Number of BTB hits +system.cpu.branchPred.lookups 20589195 # Number of BP lookups +system.cpu.branchPred.condPredicted 20589195 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1327817 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12690862 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12013274 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.624261 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1440282 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 16776 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.660820 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1440361 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 16897 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 158294635 # number of cpu cycles simulated +system.cpu.numCycles 158380696 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25247816 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227405263 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20588400 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13454275 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 131222766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3194613 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 1919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 20727 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 25245702 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227408017 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20589195 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13453635 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 131309354 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3192879 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 16 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 1952 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 21042 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24255799 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 267811 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 158090598 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.379045 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324681 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 24254364 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 267325 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 158174565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.377629 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324169 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95773120 60.58% 60.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4766421 3.01% 63.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3796193 2.40% 66.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4366321 2.76% 68.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4228924 2.68% 71.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4813507 3.04% 74.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4702194 2.97% 77.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3700875 2.34% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31943043 20.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95855369 60.60% 60.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4772394 3.02% 63.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3794325 2.40% 66.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4370382 2.76% 68.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4226374 2.67% 71.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4818979 3.05% 74.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4692035 2.97% 77.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3702011 2.34% 79.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31942696 20.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 158090598 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130064 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.436595 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15405711 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96196393 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23270128 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21621060 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1597306 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336557336 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1597306 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23296942 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31816084 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 30705 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35988234 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 65361327 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328199746 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1272 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 57739687 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7687780 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 164697 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 380395487 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 909798638 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 600491080 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4191135 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 158174565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.129998 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.435832 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15399565 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96291119 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23261573 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21625869 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1596439 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336537122 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1596439 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 23302832 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31798352 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 30486 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35975056 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 65471400 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328175182 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1530 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57810134 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7763747 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 166308 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 380366291 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 909731361 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 600445935 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4186121 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 120966037 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1948 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1925 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121028118 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 82726275 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 29782185 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59498195 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20364114 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 317775977 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4062 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 259339716 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70716 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 96416655 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197093622 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2817 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 158090598 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.640450 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.524161 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 120936841 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1921 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1898 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 121141633 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 82738842 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 29779777 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59550134 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20391789 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 317761802 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 259358612 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 72184 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 96402487 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 196983368 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 158174565 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.639699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523293 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40031018 25.32% 25.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47550925 30.08% 55.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33058238 20.91% 76.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17999758 11.39% 87.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10966409 6.94% 94.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4755401 3.01% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2459487 1.56% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 881418 0.56% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 387944 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40029224 25.31% 25.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47620381 30.11% 55.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33114320 20.94% 76.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17999452 11.38% 87.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10926984 6.91% 94.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4757371 3.01% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2459469 1.55% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 879282 0.56% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 388082 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 158090598 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 158174565 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 232409 7.35% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2543467 80.43% 87.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 386453 12.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 231613 7.32% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2544922 80.40% 87.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 388680 12.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1213129 0.47% 0.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 161789317 62.39% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789379 0.30% 63.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7038032 2.71% 65.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1187047 0.46% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 64866508 25.01% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22456304 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1213055 0.47% 0.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 161788642 62.38% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789415 0.30% 63.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7038152 2.71% 65.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1187589 0.46% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64884960 25.02% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22456799 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 259339716 # Type of FU issued -system.cpu.iq.rate 1.638335 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3162329 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012194 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 675146049 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410783686 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253609186 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4857026 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3709843 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2340813 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258843472 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2445444 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18733712 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 259358612 # Type of FU issued +system.cpu.iq.rate 1.637565 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3165215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012204 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 675270057 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410763185 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 253622616 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4859131 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3700913 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2341090 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 258863930 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2446842 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18717155 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26076688 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12661 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 303068 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9266468 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26089255 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12841 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 302099 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9264060 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50753 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50731 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1597306 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12475143 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 492608 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 317780039 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 92128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 82726275 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 29782185 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1904 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 385254 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 64210 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 303068 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 551876 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 825683 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1377559 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 257278299 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64049933 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2061417 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1596439 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12482349 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 492760 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 317765871 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 91851 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 82738842 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 29779777 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1874 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 386744 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 63788 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 302099 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 551455 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 825732 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1377187 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 257295592 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64068122 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2063020 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86328991 # number of memory reference insts executed -system.cpu.iew.exec_branches 14325599 # Number of branches executed -system.cpu.iew.exec_stores 22279058 # Number of stores executed -system.cpu.iew.exec_rate 1.625313 # Inst execution rate -system.cpu.iew.wb_sent 256636877 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 255949999 # cumulative count of insts written-back -system.cpu.iew.wb_producers 204329368 # num instructions producing a value -system.cpu.iew.wb_consumers 369642243 # num instructions consuming a value +system.cpu.iew.exec_refs 86346654 # number of memory reference insts executed +system.cpu.iew.exec_branches 14327856 # Number of branches executed +system.cpu.iew.exec_stores 22278532 # Number of stores executed +system.cpu.iew.exec_rate 1.624539 # Inst execution rate +system.cpu.iew.wb_sent 256649039 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 255963706 # cumulative count of insts written-back +system.cpu.iew.wb_producers 204348842 # num instructions producing a value +system.cpu.iew.wb_consumers 369627181 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.616922 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.552776 # average fanout of values written-back +system.cpu.iew.wb_rate 1.616129 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.552851 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 96424533 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 96410316 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1329745 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 144946815 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.527204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.957309 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1329636 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 145035845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.526267 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.955883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 45502245 31.39% 31.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57364882 39.58% 70.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14168547 9.77% 80.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11990061 8.27% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4061557 2.80% 91.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2847156 1.96% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 903972 0.62% 94.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1081775 0.75% 95.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7026620 4.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 45546155 31.40% 31.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57399506 39.58% 70.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14176238 9.77% 80.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11993202 8.27% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4061532 2.80% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2861406 1.97% 93.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 912773 0.63% 94.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1078264 0.74% 95.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7006769 4.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 144946815 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 145035845 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -538,75 +538,75 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 7026620 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 455708112 # The number of ROB reads -system.cpu.rob.rob_writes 648756933 # The number of ROB writes -system.cpu.timesIdled 2654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 204037 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 7006769 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 455802776 # The number of ROB reads +system.cpu.rob.rob_writes 648723400 # The number of ROB writes +system.cpu.timesIdled 2658 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 206131 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.198555 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.198555 # CPI: Total CPI of All Threads -system.cpu.ipc 0.834338 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.834338 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 448462774 # number of integer regfile reads -system.cpu.int_regfile_writes 232558570 # number of integer regfile writes -system.cpu.fp_regfile_reads 3214394 # number of floating regfile reads -system.cpu.fp_regfile_writes 1998880 # number of floating regfile writes -system.cpu.cc_regfile_reads 102524460 # number of cc regfile reads -system.cpu.cc_regfile_writes 59518831 # number of cc regfile writes -system.cpu.misc_regfile_reads 132416718 # number of misc regfile reads +system.cpu.cpi 1.199207 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.199207 # CPI: Total CPI of All Threads +system.cpu.ipc 0.833884 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.833884 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 448507967 # number of integer regfile reads +system.cpu.int_regfile_writes 232568909 # number of integer regfile writes +system.cpu.fp_regfile_reads 3215393 # number of floating regfile reads +system.cpu.fp_regfile_writes 1999198 # number of floating regfile writes +system.cpu.cc_regfile_reads 102530516 # number of cc regfile reads +system.cpu.cc_regfile_writes 59523273 # number of cc regfile writes +system.cpu.misc_regfile_reads 132435302 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 53 # number of replacements -system.cpu.dcache.tags.tagsinuse 1431.895248 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 65702088 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1996 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32916.877756 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 52 # number of replacements +system.cpu.dcache.tags.tagsinuse 1432.092422 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 65736813 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2001 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32851.980510 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1431.895248 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349584 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349584 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1943 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1432.092422 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 500 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.474365 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 131411014 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 131411014 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45187780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45187780 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513887 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513887 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 65701667 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 65701667 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 65701667 # number of overall hits -system.cpu.dcache.overall_hits::total 65701667 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 998 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 998 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1844 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1844 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2842 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2842 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2842 # number of overall misses -system.cpu.dcache.overall_misses::total 2842 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65947500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65947500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129226000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129226000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 195173500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 195173500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 195173500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 195173500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45188778 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45188778 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 131480483 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 131480483 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45222500 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45222500 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 65736393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 65736393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 65736393 # number of overall hits +system.cpu.dcache.overall_hits::total 65736393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1010 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1010 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2848 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2848 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2848 # number of overall misses +system.cpu.dcache.overall_misses::total 2848 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65396000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65396000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129164500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129164500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 194560500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 194560500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 194560500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 194560500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45223510 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45223510 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 65704509 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 65704509 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 65704509 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 65704509 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 65739241 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 65739241 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 65739241 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 65739241 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses @@ -615,262 +615,262 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66079.659319 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66079.659319 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70079.175705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70079.175705 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68674.700915 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68674.700915 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64748.514851 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64748.514851 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70274.483134 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70274.483134 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68314.782303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68314.782303 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 697 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.125000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 12 # number of writebacks -system.cpu.dcache.writebacks::total 12 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 541 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 541 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 10 # number of writebacks +system.cpu.dcache.writebacks::total 10 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 549 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 549 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 543 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 543 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 543 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 543 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 457 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 457 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1842 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2299 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2299 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2299 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2299 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 127238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163790500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 163790500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163790500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 163790500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 551 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 551 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 551 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 551 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1836 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1836 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2297 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2297 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2297 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2297 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127182500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127182500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163319500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 163319500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163319500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 163319500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79983.588621 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79983.588621 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69076.004343 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69076.004343 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78388.286334 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78388.286334 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69271.514161 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69271.514161 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5044 # number of replacements -system.cpu.icache.tags.tagsinuse 1638.951309 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24246301 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7022 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3452.905298 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4970 # number of replacements +system.cpu.icache.tags.tagsinuse 1639.175035 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24244955 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6947 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3489.989204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1638.951309 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800269 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800269 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 874 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 48518920 # Number of tag accesses -system.cpu.icache.tags.data_accesses 48518920 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24246303 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24246303 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24246303 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24246303 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24246303 # number of overall hits -system.cpu.icache.overall_hits::total 24246303 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9495 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9495 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9495 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9495 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9495 # number of overall misses -system.cpu.icache.overall_misses::total 9495 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 408233999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 408233999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 408233999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 408233999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 408233999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 408233999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24255798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24255798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24255798 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24255798 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24255798 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24255798 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000391 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000391 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000391 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000391 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000391 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000391 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42994.628647 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42994.628647 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42994.628647 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42994.628647 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42994.628647 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42994.628647 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 791 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1639.175035 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800378 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800378 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 48515969 # Number of tag accesses +system.cpu.icache.tags.data_accesses 48515969 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24244955 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24244955 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24244955 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24244955 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24244955 # number of overall hits +system.cpu.icache.overall_hits::total 24244955 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9408 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9408 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9408 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9408 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9408 # number of overall misses +system.cpu.icache.overall_misses::total 9408 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 407324999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 407324999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 407324999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 407324999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 407324999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 407324999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24254363 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24254363 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24254363 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24254363 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24254363 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24254363 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43295.599384 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43295.599384 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43295.599384 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43295.599384 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43295.599384 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43295.599384 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 788 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60.846154 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2168 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2168 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2168 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2168 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2168 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2168 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7327 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7327 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7327 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7327 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7327 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7327 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 310311499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 310311499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 310311499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 310311499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 310311499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 310311499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000302 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000302 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000302 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42351.780947 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42351.780947 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42351.780947 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42351.780947 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42351.780947 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42351.780947 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2164 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2164 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2164 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2164 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2164 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7244 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7244 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7244 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7244 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7244 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7244 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 309481499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 309481499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 309481499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 309481499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 309481499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 309481499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42722.459829 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42722.459829 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42722.459829 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 42722.459829 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42722.459829 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 42722.459829 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2588.297524 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8549 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3882 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.202215 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2588.929088 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8413 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3873 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.172218 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 0.823385 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2282.748954 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 304.725185 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000025 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069664 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009299 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.078989 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3882 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 994 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2615 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118469 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 119661 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 119661 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 12 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 12 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3560 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3560 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 39 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 39 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3560 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 44 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3604 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3560 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 44 # number of overall hits -system.cpu.l2cache.overall_hits::total 3604 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 303 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 303 # number of UpgradeReq misses +system.cpu.l2cache.tags.occ_blocks::writebacks 1.256976 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2282.894376 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 304.777736 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000038 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069668 # 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number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 296 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 296 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1534 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1534 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3462 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3462 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 418 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 418 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3462 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1952 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5414 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1952 # 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average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73089.073634 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 7781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 4947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 303 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 303 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7327 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 457 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 449216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 577728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 305 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 14723 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 14563 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5344 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7704 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 4875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7244 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 461 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19022 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4645 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23667 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 444416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 573120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 299 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 14563 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.061251 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.239799 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 14723 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13671 93.87% 93.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 892 6.13% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 14723 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7373500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 14563 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7291500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10986000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10864500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3145500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3149999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3877 # Transaction distribution -system.membus.trans_dist::UpgradeReq 303 # Transaction distribution -system.membus.trans_dist::UpgradeResp 303 # Transaction distribution +system.membus.trans_dist::ReadResp 3871 # Transaction distribution +system.membus.trans_dist::UpgradeReq 296 # Transaction distribution +system.membus.trans_dist::UpgradeResp 296 # Transaction distribution system.membus.trans_dist::ReadExReq 1534 # Transaction distribution system.membus.trans_dist::ReadExResp 1534 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3879 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11430 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11430 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11430 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 346304 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11402 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11402 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11402 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 345920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5716 # Request fanout histogram +system.membus.snoop_fanout::samples 5701 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5716 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5701 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5716 # Request fanout histogram -system.membus.reqLayer0.occupancy 7099000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5701 # Request fanout histogram +system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 29276697 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 29231454 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |