diff options
Diffstat (limited to 'tests/long/se/70.twolf/ref')
9 files changed, 3092 insertions, 3053 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 2c6817645..478ad3d97 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.051523 # Nu sim_ticks 51522973500 # Number of ticks simulated final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192794 # Simulator instruction rate (inst/s) -host_op_rate 192794 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108084557 # Simulator tick rate (ticks/s) -host_mem_usage 244692 # Number of bytes of host memory used -host_seconds 476.69 # Real time elapsed on the host +host_inst_rate 335661 # Simulator instruction rate (inst/s) +host_op_rate 335661 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188179142 # Simulator tick rate (ticks/s) +host_mem_usage 271092 # Number of bytes of host memory used +host_seconds 273.80 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 30 3.09% 85.57% # By system.physmem.bytesPerActivate::896-1023 24 2.47% 88.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 116 11.96% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 970 # Bytes accessed per row activation -system.physmem.totQLat 35128750 # Total ticks spent queuing -system.physmem.totMemAccLat 134766250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 35079750 # Total ticks spent queuing +system.physmem.totMemAccLat 134717250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6610.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6601.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25360.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25351.38 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.60 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.60 # Average system read bandwidth in MiByte/s @@ -218,10 +218,10 @@ system.physmem.readRowHitRate 81.65 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9695689.12 # Average gap between requests system.physmem.pageHitRate 81.65 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 48460398500 # Time in different power states +system.physmem.memoryStateTime::IDLE 48460480000 # Time in different power states system.physmem.memoryStateTime::REF 1720420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1341071500 # Time in different power states +system.physmem.memoryStateTime::ACT 1340990000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.membus.throughput 6600861 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3595 # Transaction distribution @@ -234,40 +234,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 340096 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6106000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6107000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49717250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49715750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 11407310 # Number of BP lookups -system.cpu.branchPred.condPredicted 8177170 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 788660 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6672659 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5348436 # Number of BTB hits +system.cpu.branchPred.lookups 11407320 # Number of BP lookups +system.cpu.branchPred.condPredicted 8177175 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 788662 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6672694 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5348459 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.154493 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1172954 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.154417 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1172953 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20390002 # DTB read hits +system.cpu.dtb.read_hits 20390003 # DTB read hits system.cpu.dtb.read_misses 46972 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20436974 # DTB read accesses -system.cpu.dtb.write_hits 6579989 # DTB write hits +system.cpu.dtb.read_accesses 20436975 # DTB read accesses +system.cpu.dtb.write_hits 6579991 # DTB write hits system.cpu.dtb.write_misses 273 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580262 # DTB write accesses -system.cpu.dtb.data_hits 26969991 # DTB hits +system.cpu.dtb.write_accesses 6580264 # DTB write accesses +system.cpu.dtb.data_hits 26969994 # DTB hits system.cpu.dtb.data_misses 47245 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27017236 # DTB accesses -system.cpu.itb.fetch_hits 22956123 # ITB hits +system.cpu.dtb.data_accesses 27017239 # DTB accesses +system.cpu.itb.fetch_hits 22956162 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22956211 # ITB accesses +system.cpu.itb.fetch_accesses 22956250 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -286,19 +286,19 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2250201 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2250216 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.121246 # CPI: cycles per instruction system.cpu.ipc 0.891865 # IPC: instructions per cycle -system.cpu.tickCycles 100852498 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2193449 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 100852685 # Number of cycles that the object actually ticked +system.cpu.idleCycles 2193262 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 13697 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.300459 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22940462 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1640.300457 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22940501 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15661 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1464.814635 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1464.817125 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300459 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300457 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.800928 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.800928 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id @@ -308,44 +308,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 670 system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45927907 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45927907 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22940462 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22940462 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22940462 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22940462 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22940462 # number of overall hits -system.cpu.icache.overall_hits::total 22940462 # number of overall hits +system.cpu.icache.tags.tag_accesses 45927985 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45927985 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22940501 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22940501 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22940501 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22940501 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22940501 # number of overall hits +system.cpu.icache.overall_hits::total 22940501 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15661 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15661 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15661 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15661 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15661 # number of overall misses system.cpu.icache.overall_misses::total 15661 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 385817000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 385817000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 385817000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 385817000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 385817000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 385817000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22956123 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22956123 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22956123 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22956123 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22956123 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22956123 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 385791500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 385791500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 385791500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 385791500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 385791500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 385791500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22956162 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22956162 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22956162 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22956162 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22956162 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22956162 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24635.527744 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24635.527744 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24635.527744 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24635.527744 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24635.527744 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24635.527744 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24633.899496 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24633.899496 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24633.899496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24633.899496 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -360,24 +360,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15661 system.cpu.icache.demand_mshr_misses::total 15661 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15661 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15661 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353131000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 353131000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353131000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 353131000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353131000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 353131000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353105500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 353105500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353105500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 353105500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353105500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 353105500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22548.432412 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22548.432412 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22548.432412 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22548.432412 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22548.432412 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22548.432412 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22546.804163 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22546.804163 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 22356474 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 16146 # Transaction distribution @@ -400,13 +400,13 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L system.cpu.toL2Bus.respLayer1.occupancy 3734250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2477.580709 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2477.580697 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12565 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3661 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.432122 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.790278 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790431 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.790277 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790419 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075067 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.075610 # Average percentage of cache occupancy @@ -437,14 +437,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 5314 # system.cpu.l2cache.demand_misses::total 5314 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 5314 # number of overall misses system.cpu.l2cache.overall_misses::total 5314 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245039250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245039250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117228000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 117228000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 362267250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 362267250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 362267250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 362267250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245013750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 245013750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117202000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 117202000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 362215750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 362215750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 362215750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 362215750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 16146 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16146 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) @@ -463,14 +463,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.297021 system.cpu.l2cache.demand_miss_rate::total 0.297021 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.297021 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.297021 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68161.126565 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.126565 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68195.462478 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68195.462478 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68172.233722 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68172.233722 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68172.233722 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68172.233722 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68154.033380 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68154.033380 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68180.337405 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68180.337405 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68162.542341 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68162.542341 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,14 +487,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 5314 system.cpu.l2cache.demand_mshr_misses::total 5314 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 5314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5314 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199861250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199861250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95675500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95675500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295536750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 295536750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295536750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 295536750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199838750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199838750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95648000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95648000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295486750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 295486750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295486750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 295486750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222656 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222656 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses @@ -503,22 +503,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.297021 system.cpu.l2cache.demand_mshr_miss_rate::total 0.297021 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.297021 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55594.228095 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55594.228095 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55657.649796 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55657.649796 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55614.744072 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55614.744072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55614.744072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55614.744072 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55587.969402 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55587.969402 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55641.652123 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55641.652123 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.553123 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26545427 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1448.553115 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26545428 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11903.778924 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11903.779372 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553123 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553115 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.353651 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353651 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id @@ -528,16 +528,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53099944 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53099944 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20047235 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20047235 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 53099946 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53099946 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 20047236 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20047236 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.inst 6498192 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 26545427 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26545427 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 26545427 # number of overall hits -system.cpu.dcache.overall_hits::total 26545427 # number of overall hits +system.cpu.dcache.demand_hits::cpu.inst 26545428 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26545428 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 26545428 # number of overall hits +system.cpu.dcache.overall_hits::total 26545428 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.inst 2911 # number of WriteReq misses @@ -548,20 +548,20 @@ system.cpu.dcache.overall_misses::cpu.inst 3430 # system.cpu.dcache.overall_misses::total 3430 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36876750 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 36876750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 198662500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 198662500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 235539250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235539250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 235539250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235539250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 20047754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20047754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 198611000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 198611000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 235487750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235487750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 235487750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235487750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 20047755 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20047755 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 26548857 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26548857 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 26548857 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26548857 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 26548858 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26548858 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 26548858 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26548858 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses @@ -572,12 +572,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71053.468208 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 71053.468208 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68245.448300 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68245.448300 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68670.335277 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68670.335277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68670.335277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68670.335277 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68227.756785 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68227.756785 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68655.320700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68655.320700 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,12 +606,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33572250 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 33572250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 119233500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 119233500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152805750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 152805750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152805750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 152805750 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 119207500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 119207500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152779750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 152779750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152779750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 152779750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses @@ -622,12 +622,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69221.134021 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69221.134021 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68328.653295 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68328.653295 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68522.757848 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68522.757848 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68522.757848 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68522.757848 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68313.753582 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68313.753582 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 35ce90696..5c7163ec8 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023058 # Number of seconds simulated -sim_ticks 23058360500 # Number of ticks simulated -final_tick 23058360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022159 # Number of seconds simulated +sim_ticks 22159411000 # Number of ticks simulated +final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185744 # Simulator instruction rate (inst/s) -host_op_rate 185744 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50878767 # Simulator tick rate (ticks/s) -host_mem_usage 227216 # Number of bytes of host memory used -host_seconds 453.20 # Real time elapsed on the host +host_inst_rate 150496 # Simulator instruction rate (inst/s) +host_op_rate 150496 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39616568 # Simulator tick rate (ticks/s) +host_mem_usage 240828 # Number of bytes of host memory used +host_seconds 559.35 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 196160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138688 # Number of bytes read from this memory system.physmem.bytes_read::total 334848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196416 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 196160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196160 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2167 # Number of read requests responded to by this memory system.physmem.num_reads::total 5232 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8518212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6003549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14521761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8518212 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8518212 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8518212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6003549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14521761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8852221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6258650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15110871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8852221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8852221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8852221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6258650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15110871 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5232 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5232 # Number of DRAM read bursts, including those serviced by the write queue @@ -42,20 +42,20 @@ system.physmem.servicedByWrQ 0 # Nu system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 471 # Per bank write bursts -system.physmem.perBankRdBursts::1 291 # Per bank write bursts +system.physmem.perBankRdBursts::1 289 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 524 # Per bank write bursts -system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 225 # Per bank write bursts -system.physmem.perBankRdBursts::6 219 # Per bank write bursts -system.physmem.perBankRdBursts::7 286 # Per bank write bursts -system.physmem.perBankRdBursts::8 240 # Per bank write bursts -system.physmem.perBankRdBursts::9 278 # Per bank write bursts -system.physmem.perBankRdBursts::10 248 # Per bank write bursts +system.physmem.perBankRdBursts::3 527 # Per bank write bursts +system.physmem.perBankRdBursts::4 218 # Per bank write bursts +system.physmem.perBankRdBursts::5 224 # Per bank write bursts +system.physmem.perBankRdBursts::6 217 # Per bank write bursts +system.physmem.perBankRdBursts::7 287 # Per bank write bursts +system.physmem.perBankRdBursts::8 239 # Per bank write bursts +system.physmem.perBankRdBursts::9 281 # Per bank write bursts +system.physmem.perBankRdBursts::10 249 # Per bank write bursts system.physmem.perBankRdBursts::11 253 # Per bank write bursts -system.physmem.perBankRdBursts::12 398 # Per bank write bursts +system.physmem.perBankRdBursts::12 396 # Per bank write bursts system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 491 # Per bank write bursts +system.physmem.perBankRdBursts::14 493 # Per bank write bursts system.physmem.perBankRdBursts::15 448 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23058233500 # Total gap between requests +system.physmem.totGap 22159321500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 871 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 381.722158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.044875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.837953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 257 29.51% 29.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194 22.27% 51.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 84 9.64% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 7.46% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 4.02% 72.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 4.13% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 31 3.56% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 43 4.94% 85.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 126 14.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 871 # Bytes accessed per row activation -system.physmem.totQLat 38517250 # Total ticks spent queuing -system.physmem.totMemAccLat 136617250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 383.630485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.084782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.284844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 269 31.06% 31.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 171 19.75% 50.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 88 10.16% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 7.27% 68.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 4.39% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 33 3.81% 76.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 35 4.04% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation +system.physmem.totQLat 40678250 # Total ticks spent queuing +system.physmem.totMemAccLat 138778250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7361.86 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7774.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26111.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26524.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.52 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.11 # Data bus utilization in percentage -system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4353 # Number of row buffer hits during reads +system.physmem.readRowHits 4354 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4407154.72 # Average gap between requests -system.physmem.pageHitRate 83.20 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 21416461750 # Time in different power states -system.physmem.memoryStateTime::REF 769860000 # Time in different power states +system.physmem.avgGap 4235344.32 # Average gap between requests +system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 20544029500 # Time in different power states +system.physmem.memoryStateTime::REF 739700000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 869038750 # Time in different power states +system.physmem.memoryStateTime::ACT 868593500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 14521761 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3525 # Transaction distribution -system.membus.trans_dist::ReadResp 3525 # Transaction distribution -system.membus.trans_dist::ReadExReq 1707 # Transaction distribution -system.membus.trans_dist::ReadExResp 1707 # Transaction distribution +system.membus.throughput 15110871 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3523 # Transaction distribution +system.membus.trans_dist::ReadResp 3523 # Transaction distribution +system.membus.trans_dist::ReadExReq 1709 # Transaction distribution +system.membus.trans_dist::ReadExResp 1709 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 334848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6496500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6531000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48985000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 48922250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 15361032 # Number of BP lookups -system.cpu.branchPred.condPredicted 11166301 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 940671 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8650721 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7195754 # Number of BTB hits +system.cpu.branchPred.lookups 16298030 # Number of BP lookups +system.cpu.branchPred.condPredicted 11843884 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 974423 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8872850 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7618799 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.180974 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1505004 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3205 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 85.866424 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1608574 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 439 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23573955 # DTB read hits -system.cpu.dtb.read_misses 207074 # DTB read misses -system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 23781029 # DTB read accesses -system.cpu.dtb.write_hits 7120317 # DTB write hits -system.cpu.dtb.write_misses 1134 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 7121451 # DTB write accesses -system.cpu.dtb.data_hits 30694272 # DTB hits -system.cpu.dtb.data_misses 208208 # DTB misses -system.cpu.dtb.data_acv 8 # DTB access violations -system.cpu.dtb.data_accesses 30902480 # DTB accesses -system.cpu.itb.fetch_hits 15234213 # ITB hits -system.cpu.itb.fetch_misses 102 # ITB misses +system.cpu.dtb.read_hits 24142171 # DTB read hits +system.cpu.dtb.read_misses 235539 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 24377710 # DTB read accesses +system.cpu.dtb.write_hits 7161357 # DTB write hits +system.cpu.dtb.write_misses 1208 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 7162565 # DTB write accesses +system.cpu.dtb.data_hits 31303528 # DTB hits +system.cpu.dtb.data_misses 236747 # DTB misses +system.cpu.dtb.data_acv 3 # DTB access violations +system.cpu.dtb.data_accesses 31540275 # DTB accesses +system.cpu.itb.fetch_hits 16127186 # ITB hits +system.cpu.itb.fetch_misses 86 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15234315 # ITB accesses +system.cpu.itb.fetch_accesses 16127272 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,239 +285,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46116722 # number of cpu cycles simulated +system.cpu.numCycles 44318823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15940932 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 131589057 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15361032 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8700758 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22892353 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5007718 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2994752 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2134 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15234213 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 364576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 45860852 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.869311 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.407633 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16859425 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 26218432 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44094959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22968499 50.08% 50.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2435887 5.31% 55.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1214898 2.65% 58.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1783514 3.89% 61.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2844070 6.20% 68.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1193047 2.60% 70.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1264346 2.76% 73.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 807487 1.76% 75.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11349104 24.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19653194 44.57% 44.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3047157 6.91% 64.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1303414 2.96% 67.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1381873 3.13% 71.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 894467 2.03% 73.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11866174 26.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 45860852 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.333090 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.853391 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16942268 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2554020 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21969696 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 376134 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4018734 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2597948 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12434 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 128314772 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 36360 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4018734 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17696753 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 830389 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7936 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21575239 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1731801 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 125347310 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9609 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 982853 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 675750 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22720 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 92019426 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 162776933 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 155390791 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7386141 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44094959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13063421 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8246941 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2678530 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12053 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 14206611 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4728529 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8933 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3626870 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 71936 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1987853 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1348485 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 46116 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 95420653 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 168813407 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 161260201 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7553205 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 23592065 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 733 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3333773 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26203423 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8541215 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2901793 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1268500 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 108868755 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1841 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 97966771 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 305092 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24205687 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18927840 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1452 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 45860852 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.136174 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.932064 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26993292 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 764 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 773 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8204907 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 27105677 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8747640 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3541499 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1618929 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112639456 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1940 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 100102495 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 120259 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21886195 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44094959 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12004778 26.18% 26.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8735781 19.05% 45.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7795942 17.00% 62.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6187579 13.49% 75.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4939987 10.77% 86.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3238381 7.06% 93.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1831298 3.99% 97.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 880120 1.92% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 246986 0.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11535003 26.16% 26.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7754472 17.59% 43.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7555417 17.13% 60.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5737107 13.01% 73.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4489381 10.18% 84.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2977390 6.75% 90.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2013843 4.57% 95.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 45860852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44094959 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 202355 11.05% 11.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 107 0.01% 11.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 8618 0.47% 11.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 9498 0.52% 12.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 955023 52.14% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 532552 29.07% 93.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 123630 6.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 443 0.02% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 33638 1.41% 21.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 11723 0.49% 22.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1006429 42.32% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 686405 28.86% 93.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160330 6.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59518834 60.75% 60.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 484423 0.49% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2816502 2.87% 64.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115449 0.12% 64.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2407923 2.46% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 312382 0.32% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 763359 0.78% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24335343 24.84% 92.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7212230 7.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60895265 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 491428 0.49% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2836761 2.83% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115534 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2437739 2.44% 66.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 313998 0.31% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 765483 0.76% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24980976 24.96% 92.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7264985 7.26% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 97966771 # Type of FU issued -system.cpu.iq.rate 2.124322 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1831783 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018698 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 228533724 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 123769088 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 88239146 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15397545 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9344200 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7119957 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91612691 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8185856 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1667830 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 100102495 # Type of FU issued +system.cpu.iq.rate 2.258690 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 231175572 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 90008845 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9621224 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7166740 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 94135365 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8345109 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1908745 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6207225 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16318 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 37199 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2040112 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7109479 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10719 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 42241 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2246537 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 40236 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2728 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42761 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2468 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4018734 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 14986 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 580703 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119442937 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 327587 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26203423 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8541215 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 22416 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 558101 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 37199 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 549687 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 504581 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1054268 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 96742235 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23781507 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1224536 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3707628 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 461880 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 414958 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1079990 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98729732 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24378234 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1372763 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10572341 # number of nop insts executed -system.cpu.iew.exec_refs 30903185 # number of memory reference insts executed -system.cpu.iew.exec_branches 12219901 # Number of branches executed -system.cpu.iew.exec_stores 7121678 # Number of stores executed -system.cpu.iew.exec_rate 2.097769 # Inst execution rate -system.cpu.iew.wb_sent 95961828 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 95359103 # cumulative count of insts written-back -system.cpu.iew.wb_producers 65705546 # num instructions producing a value -system.cpu.iew.wb_consumers 92226364 # num instructions consuming a value +system.cpu.iew.exec_nop 10997095 # number of nop insts executed +system.cpu.iew.exec_refs 31540837 # number of memory reference insts executed +system.cpu.iew.exec_branches 12532490 # Number of branches executed +system.cpu.iew.exec_stores 7162603 # Number of stores executed +system.cpu.iew.exec_rate 2.227716 # Inst execution rate +system.cpu.iew.wb_sent 97918366 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97175585 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67088116 # num instructions producing a value +system.cpu.iew.wb_consumers 95122373 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.067777 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.712438 # average fanout of values written-back +system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 27540320 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 928822 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 41842118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.196425 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.812600 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39466883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16239554 38.81% 38.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9401519 22.47% 61.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4137637 9.89% 71.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2136234 5.11% 76.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1534088 3.67% 79.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1088589 2.60% 82.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 699410 1.67% 84.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 798893 1.91% 86.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5806194 13.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14969501 37.93% 37.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8597580 21.78% 59.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3898486 9.88% 69.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1956471 4.96% 74.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1378247 3.49% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1028776 2.61% 80.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 694004 1.76% 82.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 732346 1.86% 84.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 41842118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39466883 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -529,10 +528,10 @@ system.cpu.commit.fp_insts 6862061 # Nu system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 51001542 55.49% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 51001453 55.49% 63.90% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2732464 2.97% 67.37% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction @@ -563,229 +562,229 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 5806194 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 155478259 # The number of ROB reads -system.cpu.rob.rob_writes 242937786 # The number of ROB writes -system.cpu.timesIdled 5286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 255870 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 156894387 # The number of ROB reads +system.cpu.rob.rob_writes 251967276 # The number of ROB writes +system.cpu.timesIdled 4538 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 223864 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.547837 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.547837 # CPI: Total CPI of All Threads -system.cpu.ipc 1.825362 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.825362 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 130779466 # number of integer regfile reads -system.cpu.int_regfile_writes 71543363 # number of integer regfile writes -system.cpu.fp_regfile_reads 6233836 # number of floating regfile reads -system.cpu.fp_regfile_writes 6101151 # number of floating regfile writes -system.cpu.misc_regfile_reads 718857 # number of misc regfile reads +system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.526479 # CPI: Total CPI of All Threads +system.cpu.ipc 1.899412 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.899412 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133358099 # number of integer regfile reads +system.cpu.int_regfile_writes 73122879 # number of integer regfile writes +system.cpu.fp_regfile_reads 6250590 # number of floating regfile reads +system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes +system.cpu.misc_regfile_reads 718773 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37986395 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 11847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 11847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1732 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4591 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 875904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 875904 # Total data (bytes) +system.cpu.toL2Bus.throughput 40079044 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 888128 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17583000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17856750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3542750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9401 # number of replacements -system.cpu.icache.tags.tagsinuse 1598.407560 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15220036 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11337 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1342.510011 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9583 # number of replacements +system.cpu.icache.tags.tagsinuse 1600.631079 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1598.407560 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.780472 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.780472 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631079 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 931 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 763 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 30479761 # Number of tag accesses -system.cpu.icache.tags.data_accesses 30479761 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 15220036 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15220036 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15220036 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15220036 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15220036 # number of overall hits -system.cpu.icache.overall_hits::total 15220036 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14176 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14176 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14176 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14176 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14176 # number of overall misses -system.cpu.icache.overall_misses::total 14176 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 411369250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 411369250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 411369250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 411369250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 411369250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 411369250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15234212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15234212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15234212 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15234212 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15234212 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15234212 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000931 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000931 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000931 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000931 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000931 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000931 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29018.711202 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29018.711202 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29018.711202 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29018.711202 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 32265889 # Number of tag accesses +system.cpu.icache.tags.data_accesses 32265889 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 16112652 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 16112652 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 16112652 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 16112652 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 16112652 # number of overall hits +system.cpu.icache.overall_hits::total 16112652 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14533 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14533 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14533 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses +system.cpu.icache.overall_misses::total 14533 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 419582750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 419582750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 419582750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 419582750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 419582750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 419582750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 16127185 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 16127185 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 16127185 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000901 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000901 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000901 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28871.034886 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28871.034886 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28871.034886 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28871.034886 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28871.034886 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28871.034886 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 39.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2839 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2839 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2839 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2839 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2839 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2839 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11337 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11337 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11337 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11337 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11337 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302662500 # 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number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3065 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2167 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 5232 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3069 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3065 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5232 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 169758750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29825000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199583750 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.297544 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985566 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985566 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.270707 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.385301 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.270707 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.385301 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55314.027370 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65405.701754 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56619.503546 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59739.162273 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59739.162273 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55314.027370 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60933.772538 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57637.327982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55314.027370 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60933.772538 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57637.327982 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171659000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29432500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201091500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 102767750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 102767750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171659000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132200250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 303859250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171659000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132200250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 303859250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292803 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.380039 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.380039 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56006.199021 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64263.100437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57079.619642 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60133.265067 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60133.265067 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56006.199021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61006.114444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58077.073777 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56006.199021 # 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12758.341637 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1456.621503 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355620 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355620 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564736 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 56732342 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 56732342 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21862715 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21862715 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492763 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492763 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 246 # 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number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492734 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492734 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28680490 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28680490 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28680490 # number of overall hits +system.cpu.dcache.overall_hits::total 28680490 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1041 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1041 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8369 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8369 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9325 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9325 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9325 # number of overall misses -system.cpu.dcache.overall_misses::total 9325 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 61174750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 61174750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 507348010 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 507348010 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses +system.cpu.dcache.overall_misses::total 9410 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65428750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65428750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 523784968 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 523784968 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 568522760 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 568522760 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 568522760 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 568522760 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21863700 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21863700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 589213718 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 589213718 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 589213718 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 589213718 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22188797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22188797 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28364803 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28364803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28364803 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28364803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001283 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001283 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004049 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004049 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000329 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000329 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000329 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000329 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62106.345178 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62106.345178 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60833.094724 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60833.094724 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28689900 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28689900 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28689900 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28689900 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.825168 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.825168 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62586.326682 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62586.326682 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60967.588204 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60967.588204 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 27950 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.942857 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62615.697981 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62615.697981 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62615.697981 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62615.697981 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29209 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.672260 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 476 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 476 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6608 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6608 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7084 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7084 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7084 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7084 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 509 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 509 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 110 # number of writebacks +system.cpu.dcache.writebacks::total 110 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 528 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 528 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6635 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6635 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2241 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2241 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2241 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2241 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36463750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36463750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124994997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 124994997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36170500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36170500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125701245 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 125701245 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161458747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161458747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161458747 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161458747 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161871745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161871745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161871745 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161871745 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004049 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004049 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71638.015717 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71638.015717 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72168.012125 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72168.012125 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70507.797271 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70507.797271 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72492.067474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72492.067474 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72039.049844 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72039.049844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72039.049844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72039.049844 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 5bf6c1d3d..e6477bb91 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2663178 # Simulator instruction rate (inst/s) -host_op_rate 2663177 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1331588953 # Simulator tick rate (ticks/s) -host_mem_usage 260384 # Number of bytes of host memory used -host_seconds 34.51 # Real time elapsed on the host +host_inst_rate 3319618 # Simulator instruction rate (inst/s) +host_op_rate 3319616 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1659808736 # Simulator tick rate (ticks/s) +host_mem_usage 259284 # Number of bytes of host memory used +host_seconds 27.68 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -96,10 +96,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction -system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 88e7e1e1c..640d2653d 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316000 # Number of ticks simulated final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1199929 # Simulator instruction rate (inst/s) -host_op_rate 1199929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1550185026 # Simulator tick rate (ticks/s) -host_mem_usage 269088 # Number of bytes of host memory used -host_seconds 76.59 # Real time elapsed on the host +host_inst_rate 1742639 # Simulator instruction rate (inst/s) +host_op_rate 1742639 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2251309988 # Simulator tick rate (ticks/s) +host_mem_usage 268020 # Number of bytes of host memory used +host_seconds 52.74 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -102,10 +102,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction -system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 6b1426f89..414b5b5a9 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,560 +1,58 @@ ---------- Begin Simulation Statistics ---------- -final_tick 133576129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 174502 # Simulator instruction rate (inst/s) -host_mem_usage 298144 # Number of bytes of host memory used -host_op_rate 191062 # Simulator op (including micro ops) rate (op/s) -host_seconds 987.48 # Real time elapsed on the host -host_tick_rate 135269038 # Simulator tick rate (ticks/s) +sim_seconds 0.131652 # Number of seconds simulated +sim_ticks 131652469500 # Number of ticks simulated +final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 235317 # Simulator instruction rate (inst/s) +host_op_rate 248063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 179784828 # Simulator tick rate (ticks/s) +host_mem_usage 321352 # Number of bytes of host memory used +host_seconds 732.28 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated -sim_ops 188671292 # Number of ops (including micro ops) simulated -sim_seconds 0.133576 # Number of seconds simulated -sim_ticks 133576129500 # Number of ticks simulated +sim_ops 181650742 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.468318 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 23338838 # Number of BTB hits -system.cpu.branchPred.BTBLookups 24446684 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 1344 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 5759272 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 40186958 # Number of conditional branches predicted -system.cpu.branchPred.lookups 50197812 # Number of BP lookups -system.cpu.branchPred.usedRAS 1870133 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 172317809 # Number of instructions committed -system.cpu.committedOps 188671292 # Number of ops (including micro ops) committed -system.cpu.cpi 1.550346 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 30104490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30104490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68315.588308 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68315.588308 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66514.624478 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66514.624478 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 30103686 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30103686 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54925733 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 54925733 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 804 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 804 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47824015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47824015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 719 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 719 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70061.205847 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70061.205847 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70028.942571 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70028.942571 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 12362645 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362645 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115040500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115040500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 1642 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1642 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 545 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 545 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76821750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76821750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1097 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1097 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 42468777 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42468777 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69487.421504 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69487.421504 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68637.535793 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68637.535793 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 42466331 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42466331 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 169966233 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 169966233 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000058 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000058 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 2446 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2446 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124645765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 124645765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1816 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1816 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 42468777 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42468777 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69487.421504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69487.421504 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68637.535793 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68637.535793 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 42466331 # number of overall hits -system.cpu.dcache.overall_hits::total 42466331 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 169966233 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 169966233 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000058 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000058 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 2446 # number of overall misses -system.cpu.dcache.overall_misses::total 2446 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124645765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 124645765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1816 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1816 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 272 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1362 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 23409.220815 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 85028998 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 1381.804492 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.337355 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.337355 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1774 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.433105 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.sampled_refs 1816 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 85028998 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 1381.804492 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42511145 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.discardedOps 12279677 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 71932968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71932968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39567.186956 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39567.186956 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37371.415126 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37371.415126 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 71928261 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71928261 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186242749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186242749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 4707 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4707 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175907251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175907251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4707 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4707 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 71932968 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71932968 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39567.186956 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39567.186956 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37371.415126 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37371.415126 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 71928261 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71928261 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 186242749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186242749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 4707 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4707 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175907251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175907251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 4707 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4707 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 71932968 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71932968 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39567.186956 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39567.186956 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37371.415126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37371.415126 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 71928261 # number of overall hits -system.cpu.icache.overall_hits::total 71928261 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 186242749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186242749 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 4707 # number of overall misses -system.cpu.icache.overall_misses::total 4707 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175907251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175907251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 4707 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4707 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1065 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 15284.373353 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 143870642 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1433.013825 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.699714 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.699714 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1803 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.880371 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 2903 # number of replacements -system.cpu.icache.tags.sampled_refs 4706 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 143870642 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1433.013825 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71928261 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 6392324 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.645017 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1097 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1097 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69461.202938 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69461.202938 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56942.378329 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56942.378329 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75643250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 75643250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992707 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.992707 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 1089 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1089 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62010250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62010250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1089 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1089 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5426 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5426 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68229.765708 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68229.765708 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55711.085327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55711.085327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 2609 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2609 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 192203250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 192203250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.519167 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.519167 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 2817 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2817 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156046750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 156046750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.516218 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.516218 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2801 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2801 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 6523 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6523 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68573.092678 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68573.092678 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56055.784062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56055.784062 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 2617 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2617 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 267846500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 267846500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.598804 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.598804 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 3906 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3906 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 218057000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 218057000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596351 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.596351 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3890 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3890 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 6523 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6523 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68573.092678 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68573.092678 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56055.784062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56055.784062 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 2617 # number of overall hits -system.cpu.l2cache.overall_hits::total 2617 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 267846500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 267846500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.598804 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.598804 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 3906 # number of overall misses -system.cpu.l2cache.overall_misses::total 3906 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 218057000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 218057000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596351 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.596351 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3890 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3890 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 538 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2015 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 0.929487 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 56217 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 3.030772 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.746792 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061302 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061395 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2808 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 2808 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 56217 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 2011.777563 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2610 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 267152259 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 260759935 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 418432 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9413 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13061 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3285500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7520749 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3003735 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 3132536 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 117248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 418432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 5426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1097 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1097 # Transaction distribution -system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 248896 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7778 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 4560000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36404000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 1863327 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 248896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 248896 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 2800 # Transaction distribution -system.membus.trans_dist::ReadResp 2800 # Transaction distribution -system.membus.trans_dist::ReadExReq 1089 # Transaction distribution -system.membus.trans_dist::ReadExResp 1089 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 34347143.61 # Average gap between requests -system.physmem.avgMemAccLat 25898.62 # Average memory access latency per DRAM burst -system.physmem.avgQLat 7148.62 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 1.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.86 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 0.01 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 1042102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1042102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 1863327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1863327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1863327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1863327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 942 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 263.473461 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.306387 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.627261 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 286 30.36% 30.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 373 39.60% 69.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 81 8.60% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 48 5.10% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 26 2.76% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 28 2.97% 89.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 20 2.12% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.91% 93.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 62 6.58% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 942 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 248896 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 248896 # Total read bytes from the system interface side +system.physmem.bytes_read::cpu.inst 247616 # Number of bytes read from this memory +system.physmem.bytes_read::total 247616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3869 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1880831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1880831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1050523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1050523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1880831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1880831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3869 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 139200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 139200 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 248896 # Number of bytes read from this memory -system.physmem.bytes_read::total 248896 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 127581858000 # Time in different power states -system.physmem.memoryStateTime::REF 4460300000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1531687500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 3889 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3889 # Number of read requests responded to by this memory -system.physmem.pageHitRate 75.67 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.perBankRdBursts::0 305 # Per bank write bursts system.physmem.perBankRdBursts::1 217 # Per bank write bursts -system.physmem.perBankRdBursts::2 139 # Per bank write bursts -system.physmem.perBankRdBursts::3 312 # Per bank write bursts -system.physmem.perBankRdBursts::4 309 # Per bank write bursts +system.physmem.perBankRdBursts::2 135 # Per bank write bursts +system.physmem.perBankRdBursts::3 313 # Per bank write bursts +system.physmem.perBankRdBursts::4 308 # Per bank write bursts system.physmem.perBankRdBursts::5 306 # Per bank write bursts system.physmem.perBankRdBursts::6 273 # Per bank write bursts -system.physmem.perBankRdBursts::7 225 # Per bank write bursts +system.physmem.perBankRdBursts::7 222 # Per bank write bursts system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts -system.physmem.perBankRdBursts::10 300 # Per bank write bursts -system.physmem.perBankRdBursts::11 202 # Per bank write bursts -system.physmem.perBankRdBursts::12 183 # Per bank write bursts -system.physmem.perBankRdBursts::13 219 # Per bank write bursts -system.physmem.perBankRdBursts::14 228 # Per bank write bursts -system.physmem.perBankRdBursts::15 204 # Per bank write bursts +system.physmem.perBankRdBursts::10 295 # Per bank write bursts +system.physmem.perBankRdBursts::11 201 # Per bank write bursts +system.physmem.perBankRdBursts::12 182 # Per bank write bursts +system.physmem.perBankRdBursts::13 218 # Per bank write bursts +system.physmem.perBankRdBursts::14 224 # Per bank write bursts +system.physmem.perBankRdBursts::15 203 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -571,8 +69,25 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 3640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 131652381500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 3869 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 240 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -603,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 3889 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3889 # Read request sizes (log2) -system.physmem.readReqs 3889 # Number of read requests accepted -system.physmem.readRowHitRate 75.67 # Row buffer hit rate for reads -system.physmem.readRowHits 2943 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 19445000 # Total ticks spent in databus transfers -system.physmem.totGap 133576041500 # Total gap between requests -system.physmem.totMemAccLat 100719750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 27801000 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -683,17 +182,518 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 903 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 272.372093 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.073064 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 280.203163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 262 29.01% 29.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 352 38.98% 68.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 86 9.52% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 48 5.32% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 3.88% 86.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 23 2.55% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 17 1.88% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.77% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 64 7.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 903 # Bytes accessed per row activation +system.physmem.totQLat 27589000 # Total ticks spent queuing +system.physmem.totMemAccLat 100132750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7130.78 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25880.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.01 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 2961 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 34027495.86 # Average gap between requests +system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 125800689500 # Time in different power states +system.physmem.memoryStateTime::REF 4396080000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1453432500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1880831 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2779 # Transaction distribution +system.membus.trans_dist::ReadResp 2779 # Transaction distribution +system.membus.trans_dist::ReadExReq 1090 # Transaction distribution +system.membus.trans_dist::ReadExResp 1090 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 247616 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 4528000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 36223250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 49915423 # Number of BP lookups +system.cpu.branchPred.condPredicted 39661220 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5747038 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24423675 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23301282 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 95.404488 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1905800 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 263304939 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 172317809 # Number of instructions committed +system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed +system.cpu.discardedOps 11787313 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.528019 # CPI: cycles per instruction +system.cpu.ipc 0.654442 # IPC: instructions per cycle +system.cpu.tickCycles 255940225 # Number of cycles that the object actually ticked +system.cpu.idleCycles 7364714 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 2881 # number of replacements +system.cpu.icache.tags.tagsinuse 1424.983797 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71509873 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4678 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15286.420051 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983797 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695793 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695793 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 143033782 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143033782 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71509873 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71509873 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71509873 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71509873 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71509873 # number of overall hits +system.cpu.icache.overall_hits::total 71509873 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4679 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4679 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4679 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4679 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4679 # number of overall misses +system.cpu.icache.overall_misses::total 4679 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 184764496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 184764496 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 184764496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 184764496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 184764496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 184764496 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71514552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71514552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71514552 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71514552 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71514552 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71514552 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39488.030776 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39488.030776 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39488.030776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39488.030776 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4679 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4679 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4679 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4679 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4679 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174487504 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 174487504 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174487504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 174487504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174487504 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 174487504 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.622996 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37291.622996 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 3161293 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9357 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3634 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 12991 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 416192 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3268000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7477496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2996735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2001.642880 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2592 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.930032 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 3.028976 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060993 # 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Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810162 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1357 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.431396 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 81497573 # 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number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 40703068 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40703068 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 40703068 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40703068 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000059 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000059 # 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number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 546 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 602 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 602 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 602 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 602 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1098 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1809 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47475265 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47475265 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77144500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77144500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124619765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 124619765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124619765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 124619765 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70259.107468 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70259.107468 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index eafc895c2..790b23ee8 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074057 # Number of seconds simulated -sim_ticks 74056845500 # Number of ticks simulated -final_tick 74056845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.071387 # Number of seconds simulated +sim_ticks 71387376000 # Number of ticks simulated +final_tick 71387376000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115398 # Simulator instruction rate (inst/s) -host_op_rate 126351 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49598898 # Simulator tick rate (ticks/s) -host_mem_usage 265028 # Number of bytes of host memory used -host_seconds 1493.11 # Real time elapsed on the host +host_inst_rate 91858 # Simulator instruction rate (inst/s) +host_op_rate 96834 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38058123 # Simulator tick rate (ticks/s) +host_mem_usage 257304 # Number of bytes of host memory used +host_seconds 1875.75 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated -sim_ops 188656503 # Number of ops (including micro ops) simulated +sim_ops 181635953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory -system.physmem.bytes_read::total 244032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131840 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2060 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3813 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1780254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1514944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3295198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1780254 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1780254 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1780254 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1514944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3295198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3814 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 130496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111040 # Number of bytes read from this memory +system.physmem.bytes_read::total 241536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 130496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 130496 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2039 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1735 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3774 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1827998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1555457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3383455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1827998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1827998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1827998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1555457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3383455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3774 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3814 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3774 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 244096 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 241536 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 244096 # Total read bytes from the system interface side +system.physmem.bytesReadSys 241536 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 307 # Per bank write bursts -system.physmem.perBankRdBursts::1 215 # Per bank write bursts -system.physmem.perBankRdBursts::2 134 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts -system.physmem.perBankRdBursts::4 299 # Per bank write bursts -system.physmem.perBankRdBursts::5 300 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 60 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 313 # Per bank write bursts +system.physmem.perBankRdBursts::1 214 # Per bank write bursts +system.physmem.perBankRdBursts::2 128 # Per bank write bursts +system.physmem.perBankRdBursts::3 306 # Per bank write bursts +system.physmem.perBankRdBursts::4 297 # Per bank write bursts +system.physmem.perBankRdBursts::5 299 # Per bank write bursts system.physmem.perBankRdBursts::6 265 # Per bank write bursts -system.physmem.perBankRdBursts::7 223 # Per bank write bursts -system.physmem.perBankRdBursts::8 246 # Per bank write bursts -system.physmem.perBankRdBursts::9 213 # Per bank write bursts -system.physmem.perBankRdBursts::10 289 # Per bank write bursts -system.physmem.perBankRdBursts::11 196 # Per bank write bursts -system.physmem.perBankRdBursts::12 190 # Per bank write bursts -system.physmem.perBankRdBursts::13 207 # Per bank write bursts -system.physmem.perBankRdBursts::14 219 # Per bank write bursts -system.physmem.perBankRdBursts::15 201 # Per bank write bursts +system.physmem.perBankRdBursts::7 217 # Per bank write bursts +system.physmem.perBankRdBursts::8 243 # Per bank write bursts +system.physmem.perBankRdBursts::9 220 # Per bank write bursts +system.physmem.perBankRdBursts::10 282 # Per bank write bursts +system.physmem.perBankRdBursts::11 189 # Per bank write bursts +system.physmem.perBankRdBursts::12 184 # Per bank write bursts +system.physmem.perBankRdBursts::13 208 # Per bank write bursts +system.physmem.perBankRdBursts::14 212 # Per bank write bursts +system.physmem.perBankRdBursts::15 197 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 74056827000 # Total gap between requests +system.physmem.totGap 71387262500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3814 # Read request sizes (log2) +system.physmem.readPktSize::6 3774 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 775 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.641290 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.687696 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 311.293227 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 258 33.29% 33.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189 24.39% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 87 11.23% 68.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51 6.58% 75.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 41 5.29% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 31 4.00% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 43 5.55% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10 1.29% 91.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 65 8.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 775 # Bytes accessed per row activation -system.physmem.totQLat 30109750 # Total ticks spent queuing -system.physmem.totMemAccLat 101622250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19070000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7894.53 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 730 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 328.591781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.502533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.063907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 243 33.29% 33.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 162 22.19% 55.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95 13.01% 68.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 41 5.62% 74.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 34 4.66% 78.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 29 3.97% 82.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 4.93% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 2.88% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 69 9.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 730 # Bytes accessed per row activation +system.physmem.totQLat 27328250 # Total ticks spent queuing +system.physmem.totMemAccLat 98090750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 18870000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7241.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26644.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25991.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.30 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage @@ -216,44 +216,44 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3033 # Number of row buffer hits during reads +system.physmem.readRowHits 3037 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.52 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19417101.99 # Average gap between requests -system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 70721348250 # Time in different power states -system.physmem.memoryStateTime::REF 2472860000 # Time in different power states +system.physmem.avgGap 18915543.85 # Average gap between requests +system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 68189011250 # Time in different power states +system.physmem.memoryStateTime::REF 2383680000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 861203250 # Time in different power states +system.physmem.memoryStateTime::ACT 812104750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 3295198 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2737 # Transaction distribution -system.membus.trans_dist::ReadResp 2736 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 1077 # Transaction distribution -system.membus.trans_dist::ReadExResp 1077 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7631 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7631 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 244032 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 244032 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 244032 # Total data (bytes) +system.membus.throughput 3383455 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2699 # Transaction distribution +system.membus.trans_dist::ReadResp 2699 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60 # Transaction distribution +system.membus.trans_dist::UpgradeResp 60 # Transaction distribution +system.membus.trans_dist::ReadExReq 1075 # Transaction distribution +system.membus.trans_dist::ReadExResp 1075 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7668 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 241536 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 241536 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 241536 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4541000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4574500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35636248 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35380947 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 95688557 # Number of BP lookups -system.cpu.branchPred.condPredicted 75485372 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6295432 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 45268261 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43530249 # Number of BTB hits +system.cpu.branchPred.lookups 106458293 # Number of BP lookups +system.cpu.branchPred.condPredicted 82706448 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6339444 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 50217715 # Number of BTB lookups +system.cpu.branchPred.BTBHits 48291708 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.160639 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4420185 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 89338 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.164686 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5164625 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84625 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,517 +339,520 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148113692 # number of cpu cycles simulated +system.cpu.numCycles 142774753 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 40192835 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 385592009 # Number of instructions fetch has processed -system.cpu.fetch.Branches 95688557 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47950434 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81543775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28012255 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4465673 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5818 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 44808389 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429802861 # Number of instructions fetch has processed +system.cpu.fetch.Branches 106458293 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 53456333 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 91468493 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12731388 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5563 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37392446 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1863811 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 147907378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.849949 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.160123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41753796 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1912042 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 142648266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.160575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.133574 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66535735 44.98% 44.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5361707 3.63% 48.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10726789 7.25% 55.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10405351 7.04% 62.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8725871 5.90% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6634741 4.49% 73.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6328592 4.28% 77.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8060301 5.45% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25128291 16.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 53718645 37.66% 37.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6357410 4.46% 42.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10351894 7.26% 49.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14920250 10.46% 59.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 10655390 7.47% 67.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3891108 2.73% 70.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7883355 5.53% 75.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 9310317 6.53% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25559897 17.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 147907378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.646048 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.603352 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45234948 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3964725 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76674416 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 488435 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21544854 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14463585 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 165860 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 398867240 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 776962 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21544854 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 49978288 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 80802 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 634035 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72417632 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3251767 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 377266574 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 64 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 883323 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2242172 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 19804 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 7460 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 639899653 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1616068029 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1531504010 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3330597 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 341855514 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25341 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25337 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6011835 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 44415560 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16956234 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6645157 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4213095 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 334591306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47320 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 251099486 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1072213 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 144899766 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 380484892 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2104 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 147907378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.697681 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.790678 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 142648266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.745638 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.010356 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37233141 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 23853545 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 68602562 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6747325 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6211693 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15955000 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160395 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 420485829 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 828178 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6211693 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42171212 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 18551410 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 713419 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69222818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5777714 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 398176302 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1614739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2816561 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 62575 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 202 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 691997012 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1704697725 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 425662370 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3491733 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 399020083 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 28576 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 28600 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 15636023 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 44518617 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 18120521 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7204434 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5193927 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353303303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 50659 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249217571 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 532732 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 170449002 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 473050896 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5443 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 142648266 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.747077 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.881809 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56583019 38.26% 38.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 21897324 14.80% 53.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24121591 16.31% 69.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20330444 13.75% 83.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12466477 8.43% 91.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6673732 4.51% 96.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4321605 2.92% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1302038 0.88% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 211148 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54008982 37.86% 37.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 21782256 15.27% 53.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24530872 17.20% 70.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 16106640 11.29% 81.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11858342 8.31% 89.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6781839 4.75% 94.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5090438 3.57% 98.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1742716 1.22% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 746181 0.52% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 147907378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 142648266 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1040958 39.39% 39.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5589 0.21% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 97 0.00% 39.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 39.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 39.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 356 0.01% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 45 0.00% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1222208 46.25% 85.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 373303 14.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1599616 44.61% 44.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5629 0.16% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 43 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 26 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 2425 0.07% 44.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 44.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 44.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1462989 40.80% 85.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 515010 14.36% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 195834645 77.99% 77.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 981127 0.39% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33203 0.01% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 259909 0.10% 78.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76654 0.03% 78.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 470113 0.19% 78.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206582 0.08% 78.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71910 0.03% 78.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38922233 15.50% 94.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14078361 5.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 192832828 77.38% 77.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1041370 0.42% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33133 0.01% 77.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 77.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164691 0.07% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 264054 0.11% 77.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76936 0.03% 78.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 473853 0.19% 78.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207040 0.08% 78.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 72084 0.03% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39374798 15.80% 94.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14676461 5.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 251099486 # Type of FU issued -system.cpu.iq.rate 1.695316 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2642556 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010524 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 650051417 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 477257433 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 239511768 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3769702 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2301296 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1862518 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 251853224 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1888818 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2264941 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249217571 # Type of FU issued +system.cpu.iq.rate 1.745530 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3585738 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014388 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 641399049 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 521384383 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237201307 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3802829 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2450137 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1875104 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250898873 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1904436 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1999527 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14566076 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14946 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20827 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4311600 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16622473 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18079 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32569 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5475887 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 115 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 334532 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 126 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21544854 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1947 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2849 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334655682 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 756589 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 44415560 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16956234 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24912 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 319 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2632 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20827 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3907560 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3770350 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7677910 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 244706645 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37396904 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6392841 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6211693 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18514097 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 29892 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353371291 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 723756 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 44518617 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 18120521 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 28251 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2286 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 27735 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32569 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3999566 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3827175 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7826741 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 243157329 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37609930 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6060242 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17056 # number of nop insts executed -system.cpu.iew.exec_refs 51162912 # number of memory reference insts executed -system.cpu.iew.exec_branches 53733408 # Number of branches executed -system.cpu.iew.exec_stores 13766008 # Number of stores executed -system.cpu.iew.exec_rate 1.652154 # Inst execution rate -system.cpu.iew.wb_sent 242463171 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 241374286 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150213875 # num instructions producing a value -system.cpu.iew.wb_consumers 271770811 # num instructions consuming a value +system.cpu.iew.exec_nop 17329 # number of nop insts executed +system.cpu.iew.exec_refs 51859202 # number of memory reference insts executed +system.cpu.iew.exec_branches 55857945 # Number of branches executed +system.cpu.iew.exec_stores 14249272 # Number of stores executed +system.cpu.iew.exec_rate 1.703084 # Inst execution rate +system.cpu.iew.wb_sent 240511751 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239076411 # cumulative count of insts written-back +system.cpu.iew.wb_producers 145760285 # num instructions producing a value +system.cpu.iew.wb_consumers 269855272 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.629655 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.552723 # average fanout of values written-back +system.cpu.iew.wb_rate 1.674501 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.540142 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 145985060 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 171723245 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6141058 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126362524 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.493092 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.207919 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6185443 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117932320 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.540293 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.243745 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57333838 45.37% 45.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31277146 24.75% 70.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13531640 10.71% 80.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7550408 5.98% 86.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4276360 3.38% 90.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1325331 1.05% 91.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1692872 1.34% 92.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1209518 0.96% 93.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 8165411 6.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 51372616 43.56% 43.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31468321 26.68% 70.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11935963 10.12% 80.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 6951478 5.89% 86.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3813624 3.23% 89.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1418078 1.20% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1525333 1.29% 91.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1616480 1.37% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7830427 6.64% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126362524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117932320 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed -system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42494118 # Number of memory references committed -system.cpu.commit.loads 29849484 # Number of loads committed +system.cpu.commit.refs 40540778 # Number of memory references committed +system.cpu.commit.loads 27896144 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed system.cpu.commit.branches 40300311 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. +system.cpu.commit.int_insts 143085667 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 144055022 76.35% 76.35% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 908940 0.48% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 76.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 76.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.08% 76.93% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.23% 77.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 29849484 15.82% 93.30% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 12644634 6.70% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 138987812 76.51% 76.51% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction -system.cpu.commit.bw_lim_events 8165411 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction +system.cpu.commit.bw_lim_events 7830427 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 452847863 # The number of ROB reads -system.cpu.rob.rob_writes 690972129 # The number of ROB writes -system.cpu.timesIdled 2844 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 206314 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 463470278 # The number of ROB reads +system.cpu.rob.rob_writes 731648814 # The number of ROB writes +system.cpu.timesIdled 1645 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 126487 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated -system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.859612 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.859612 # CPI: Total CPI of All Threads -system.cpu.ipc 1.163316 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.163316 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1087499674 # number of integer regfile reads -system.cpu.int_regfile_writes 386673292 # number of integer regfile writes -system.cpu.fp_regfile_reads 2922602 # number of floating regfile reads -system.cpu.fp_regfile_writes 2532629 # number of floating regfile writes -system.cpu.misc_regfile_reads 65625361 # number of misc regfile reads +system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.828626 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.828626 # CPI: Total CPI of All Threads +system.cpu.ipc 1.206817 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.206817 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 248213314 # number of integer regfile reads +system.cpu.int_regfile_writes 133191535 # number of integer regfile writes +system.cpu.fp_regfile_reads 2934311 # number of floating regfile reads +system.cpu.fp_regfile_writes 2552498 # number of floating regfile writes +system.cpu.cc_regfile_reads 830988511 # number of cc regfile reads +system.cpu.cc_regfile_writes 255127381 # number of cc regfile writes +system.cpu.misc_regfile_reads 66039150 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5184342 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1084 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1084 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8245 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3740 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11985 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 383808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 383808 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 5345035 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 61 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 61 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1087 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1087 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8146 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3823 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11969 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 258688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 118976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 377664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 377664 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3029000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6552747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6522997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3102991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3106540 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2387 # number of replacements -system.cpu.icache.tags.tagsinuse 1349.069671 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37387126 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4121 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9072.343121 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2317 # number of replacements +system.cpu.icache.tags.tagsinuse 1337.456920 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 41747829 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4039 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10336.179500 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1349.069671 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.658725 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.658725 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1734 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 547 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1337.456920 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.653055 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.653055 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1722 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1033 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.846680 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 74789015 # Number of tag accesses -system.cpu.icache.tags.data_accesses 74789015 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 37387126 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37387126 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37387126 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37387126 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37387126 # number of overall hits -system.cpu.icache.overall_hits::total 37387126 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5320 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5320 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5320 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5320 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5320 # number of overall misses -system.cpu.icache.overall_misses::total 5320 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 224799997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 224799997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 224799997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 224799997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 224799997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 224799997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37392446 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37392446 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37392446 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37392446 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37392446 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37392446 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42255.638534 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42255.638534 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42255.638534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42255.638534 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1071 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 83511695 # Number of tag accesses +system.cpu.icache.tags.data_accesses 83511695 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 41748272 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41748272 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 41748272 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41748272 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 41748272 # number of overall hits +system.cpu.icache.overall_hits::total 41748272 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5524 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5524 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5524 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5524 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5524 # number of overall misses +system.cpu.icache.overall_misses::total 5524 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 227823494 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 227823494 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 227823494 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 227823494 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 227823494 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 227823494 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 41753796 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41753796 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 41753796 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41753796 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 41753796 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41753796 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000132 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000132 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000132 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000132 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000132 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000132 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41242.486242 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41242.486242 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41242.486242 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41242.486242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41242.486242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41242.486242 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 857 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47.611111 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1196 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1196 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1196 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1196 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1196 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1196 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4124 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4124 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4124 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4124 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4124 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4124 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168596253 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168596253 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168596253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168596253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168596253 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168596253 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000110 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000110 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000110 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40881.729631 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40881.729631 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1420 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1420 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1420 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1420 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1420 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1420 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4104 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4104 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4104 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4104 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4104 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4104 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 164891501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 164891501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 164891501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 164891501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 164891501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 164891501 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40178.240984 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40178.240984 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40178.240984 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40178.240984 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40178.240984 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40178.240984 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1967.769315 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2148 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2745 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.782514 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1935.733118 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2084 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2703 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.770995 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4.017679 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1427.875766 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 535.875870 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043575 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.016354 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.060052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2745 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 608 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1972 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083771 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51829 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51829 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2058 # 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number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 60 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 60 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2040 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1735 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3775 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2040 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1735 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3775 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 114933000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38476250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153409250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 623553 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 623553 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60696250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60696250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114933000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99172500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 214105500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114933000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99172500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 214105500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.504576 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.874172 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.562734 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983607 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983607 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.988960 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.988960 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.504576 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941911 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.641461 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.504576 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941911 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.641461 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56339.705882 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58297.348485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56818.240741 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10392.550000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10392.550000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56461.627907 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56461.627907 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56339.705882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57159.942363 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56716.688742 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56339.705882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57159.942363 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56716.688742 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 56 # number of replacements -system.cpu.dcache.tags.tagsinuse 1410.171492 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 47073011 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1860 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25308.070430 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1395.016190 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 47368346 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1842 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25715.714441 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1410.171492 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.344280 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.344280 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1804 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1395.016190 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.340580 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.340580 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1786 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.440430 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 94167216 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 94167216 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 34671591 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34671591 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356534 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356534 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22477 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22477 # number of LoadLockedReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1369 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.436035 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 94757994 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 94757994 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 34966407 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34966407 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356440 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356440 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 545 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 545 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22480 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22480 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 47028125 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47028125 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 47028125 # number of overall hits -system.cpu.dcache.overall_hits::total 47028125 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1914 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1914 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7753 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7753 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 47322847 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47322847 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 47323392 # number of overall hits +system.cpu.dcache.overall_hits::total 47323392 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1942 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1942 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7847 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7847 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9667 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9667 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9667 # number of overall misses -system.cpu.dcache.overall_misses::total 9667 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 120679977 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 120679977 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 501616998 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 501616998 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 622296975 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 622296975 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 622296975 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 622296975 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34673505 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34673505 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9789 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9789 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9795 # number of overall misses +system.cpu.dcache.overall_misses::total 9795 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 120282480 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 120282480 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 504727051 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 504727051 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 143500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 143500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 625009531 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 625009531 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 625009531 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 625009531 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34968349 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34968349 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22479 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22479 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 551 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 551 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22482 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22482 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47037792 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47037792 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47037792 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47037792 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 47332636 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47332636 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47333187 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47333187 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000635 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000635 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.010889 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.010889 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63051.189655 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63051.189655 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64699.728879 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64699.728879 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64373.329368 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64373.329368 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 99 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.428571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 99 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.425335 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.425335 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64321.020900 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64321.020900 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63848.149045 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63848.149045 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63809.038387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63809.038387 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 848 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 85 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 42.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6668 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6668 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17 # number of writebacks +system.cpu.dcache.writebacks::total 17 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1189 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1189 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6701 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6701 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7805 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7805 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7805 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7805 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1862 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1862 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1862 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1862 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51275761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51275761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75222996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75222996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126498757 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126498757 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126498757 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126498757 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7890 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7890 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7890 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7890 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 753 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 753 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1146 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1899 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1899 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1903 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1903 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48859513 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 48859513 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76658945 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 76658945 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 305000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 305000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 125518458 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 125518458 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 125823458 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 125823458 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007260 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007260 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65991.970399 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65991.970399 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69329.950230 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69329.950230 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64886.471448 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64886.471448 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66892.622164 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66892.622164 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76250 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66097.134281 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66097.134281 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66118.475039 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66118.475039 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index af9e4b297..dd6254b3c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103107 # Number of seconds simulated -sim_ticks 103106766000 # Number of ticks simulated -final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.099596 # Number of seconds simulated +sim_ticks 99596491000 # Number of ticks simulated +final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1728223 # Simulator instruction rate (inst/s) -host_op_rate 1892237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1034088491 # Simulator tick rate (ticks/s) -host_mem_usage 304984 # Number of bytes of host memory used -host_seconds 99.71 # Real time elapsed on the host +host_inst_rate 1821315 # Simulator instruction rate (inst/s) +host_op_rate 1919960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1052688537 # Simulator tick rate (ticks/s) +host_mem_usage 309564 # Number of bytes of host memory used +host_seconds 94.61 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated -sim_ops 188670891 # Number of ops (including micro ops) simulated +sim_ops 181650341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 759440204 # Nu system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 189860051 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29622453 # Number of read requests responded to by this memory -system.physmem.num_reads::total 219482504 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217637772 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7365570985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1072031112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8437602097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7365570985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7365570985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 438893991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 438893991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7365570985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1510925103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8876496088 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 8876496088 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 7625170288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1109814813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8734985101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7625170288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7625170288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 454362795 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 454362795 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9189347896 # Throughput (bytes/s) system.membus.data_through_bus 915226805 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 206213533 # number of cpu cycles simulated +system.cpu.numCycles 199192983 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317409 # Number of instructions committed -system.cpu.committedOps 188670891 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses +system.cpu.committedOps 181650341 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls -system.cpu.num_int_insts 150106218 # number of integer instructions +system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls +system.cpu.num_int_insts 143085668 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 815315678 # number of times the integer registers were read -system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written +system.cpu.num_int_register_reads 241970171 # number of times the integer registers were read +system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_mem_refs 42494119 # number of memory refs -system.cpu.num_load_insts 29849484 # Number of load instructions +system.cpu.num_cc_register_reads 543309967 # number of times the CC registers were read +system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written +system.cpu.num_mem_refs 40540779 # number of memory refs +system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 206213533 # Number of busy cycles +system.cpu.num_busy_cycles 199192983 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 40300311 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 144055422 76.35% 76.35% # Class of executed instruction -system.cpu.op_class::IntMult 908940 0.48% 76.83% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 32754 0.02% 76.85% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 76.85% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 154829 0.08% 76.93% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.06% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 437591 0.23% 77.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 200806 0.11% 77.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.48% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.48% # Class of executed instruction -system.cpu.op_class::MemRead 29849484 15.82% 93.30% # Class of executed instruction -system.cpu.op_class::MemWrite 12644635 6.70% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction +system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction +system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction +system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 188671292 # Class of executed instruction +system.cpu.op_class::total 181650742 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 7e06925a9..6f9f28d30 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232072 # Number of seconds simulated -sim_ticks 232072304000 # Number of ticks simulated -final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.230173 # Number of seconds simulated +sim_ticks 230173357000 # Number of ticks simulated +final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 924224 # Simulator instruction rate (inst/s) -host_op_rate 1012125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1248159761 # Simulator tick rate (ticks/s) -host_mem_usage 313696 # Number of bytes of host memory used -host_seconds 185.93 # Real time elapsed on the host +host_inst_rate 1246866 # Simulator instruction rate (inst/s) +host_op_rate 1314511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1670106565 # Simulator tick rate (ticks/s) +host_mem_usage 319316 # Number of bytes of host memory used +host_seconds 137.82 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated -sim_ops 188185920 # Number of ops (including micro ops) simulated +sim_ops 181165370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory @@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 110656 # Nu system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 476817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 475438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 952255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 476817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 476817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 952255 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 960111 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 2361 # Transaction distribution system.membus.trans_dist::ReadResp 2361 # Transaction distribution system.membus.trans_dist::ReadExReq 1092 # Transaction distribution @@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 220992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -130,73 +130,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 464144608 # number of cpu cycles simulated +system.cpu.numCycles 460346714 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842483 # Number of instructions committed -system.cpu.committedOps 188185920 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses +system.cpu.committedOps 181165370 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls -system.cpu.num_int_insts 150106218 # number of integer instructions +system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls +system.cpu.num_int_insts 143085668 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 904571312 # number of times the integer registers were read -system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written +system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read +system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_mem_refs 42494119 # number of memory refs -system.cpu.num_load_insts 29849484 # Number of load instructions +system.cpu.num_cc_register_reads 626384527 # number of times the CC registers were read +system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written +system.cpu.num_mem_refs 40540779 # number of memory refs +system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 464144608 # Number of busy cycles +system.cpu.num_busy_cycles 460346714 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 40300311 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 144055422 76.35% 76.35% # Class of executed instruction -system.cpu.op_class::IntMult 908940 0.48% 76.83% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 32754 0.02% 76.85% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 76.85% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 154829 0.08% 76.93% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.06% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 437591 0.23% 77.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 200806 0.11% 77.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.48% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.48% # Class of executed instruction -system.cpu.op_class::MemRead 29849484 15.82% 93.30% # Class of executed instruction -system.cpu.op_class::MemWrite 12644635 6.70% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction +system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction +system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction +system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 188671292 # Class of executed instruction +system.cpu.op_class::total 181650742 # Class of executed instruction system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992604 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -218,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112281000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112281000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112281000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112281000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112281000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112281000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112370500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112370500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112370500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112370500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112370500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112370500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses @@ -236,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36801.376598 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36801.376598 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36801.376598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36801.376598 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.711242 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36830.711242 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36830.711242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36830.711242 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -256,34 +258,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106179000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 106179000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106179000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 106179000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106268500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 106268500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106268500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 106268500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106268500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 106268500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34830.711242 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34830.711242 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.655740 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1675.663358 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036759 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588821 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy @@ -321,17 +323,17 @@ system.cpu.l2cache.demand_misses::total 3453 # nu system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses system.cpu.l2cache.overall_misses::total 3453 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89908000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32864000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 122772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56784000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56784000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 89908000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 89648000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179556000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 89908000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 89648000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179556000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89997500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32887000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 122884500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56814500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 56814500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 89997500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 89701500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 179699000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 89997500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 89701500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179699000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses) @@ -356,17 +358,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52051.764025 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.392405 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52047.649301 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52027.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52027.930403 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52041.413264 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52041.413264 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -421,14 +423,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.611259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42007358 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 23480.915595 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -436,64 +438,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84020083 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84020083 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits -system.cpu.dcache.overall_hits::total 41962544 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits +system.cpu.dcache.overall_hits::total 40117812 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -504,40 +514,48 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1339169 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1350217 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 27be407ab..7d03f3ce8 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.145755 # Number of seconds simulated -sim_ticks 145755370500 # Number of ticks simulated -final_tick 145755370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148587 # Number of seconds simulated +sim_ticks 148587085500 # Number of ticks simulated +final_tick 148587085500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67444 # Simulator instruction rate (inst/s) -host_op_rate 113042 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74431489 # Simulator tick rate (ticks/s) -host_mem_usage 330012 # Number of bytes of host memory used -host_seconds 1958.25 # Real time elapsed on the host +host_inst_rate 101386 # Simulator instruction rate (inst/s) +host_op_rate 169932 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 114064202 # Simulator tick rate (ticks/s) +host_mem_usage 285092 # Number of bytes of host memory used +host_seconds 1302.66 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 218240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125376 # Number of bytes read from this memory -system.physmem.bytes_read::total 343616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 218240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 218240 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1959 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5369 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1497303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 860181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2357484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1497303 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1497303 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1497303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 860181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2357484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5369 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 225472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory +system.physmem.bytes_read::total 350912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3523 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5483 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1517440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 844219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2361659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1517440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1517440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1517440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 844219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2361659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5483 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5369 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5483 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 343616 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 350912 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 343616 # Total read bytes from the system interface side +system.physmem.bytesReadSys 350912 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 207 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 284 # Per bank write bursts -system.physmem.perBankRdBursts::1 359 # Per bank write bursts -system.physmem.perBankRdBursts::2 451 # Per bank write bursts -system.physmem.perBankRdBursts::3 358 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 350 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 310 # Per bank write bursts +system.physmem.perBankRdBursts::1 352 # Per bank write bursts +system.physmem.perBankRdBursts::2 465 # Per bank write bursts +system.physmem.perBankRdBursts::3 360 # Per bank write bursts system.physmem.perBankRdBursts::4 334 # Per bank write bursts -system.physmem.perBankRdBursts::5 327 # Per bank write bursts -system.physmem.perBankRdBursts::6 401 # Per bank write bursts -system.physmem.perBankRdBursts::7 381 # Per bank write bursts +system.physmem.perBankRdBursts::5 328 # Per bank write bursts +system.physmem.perBankRdBursts::6 400 # Per bank write bursts +system.physmem.perBankRdBursts::7 386 # Per bank write bursts system.physmem.perBankRdBursts::8 341 # Per bank write bursts -system.physmem.perBankRdBursts::9 279 # Per bank write bursts -system.physmem.perBankRdBursts::10 232 # Per bank write bursts -system.physmem.perBankRdBursts::11 279 # Per bank write bursts -system.physmem.perBankRdBursts::12 208 # Per bank write bursts -system.physmem.perBankRdBursts::13 464 # Per bank write bursts -system.physmem.perBankRdBursts::14 389 # Per bank write bursts -system.physmem.perBankRdBursts::15 282 # Per bank write bursts +system.physmem.perBankRdBursts::9 281 # Per bank write bursts +system.physmem.perBankRdBursts::10 278 # Per bank write bursts +system.physmem.perBankRdBursts::11 258 # Per bank write bursts +system.physmem.perBankRdBursts::12 226 # Per bank write bursts +system.physmem.perBankRdBursts::13 469 # Per bank write bursts +system.physmem.perBankRdBursts::14 405 # Per bank write bursts +system.physmem.perBankRdBursts::15 290 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 145755124000 # Total gap between requests +system.physmem.totGap 148587005000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5369 # Read request sizes (log2) +system.physmem.readPktSize::6 5483 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 915 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.156134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.849707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.212521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 414 38.48% 38.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 235 21.84% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 101 9.39% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 5.39% 75.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 43 4.00% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 47 4.37% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 3.16% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 1.77% 88.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 125 11.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1076 # Bytes accessed per row activation -system.physmem.totQLat 40846250 # Total ticks spent queuing -system.physmem.totMemAccLat 141515000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26845000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7607.79 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1137 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.616535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.186204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.211340 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 456 40.11% 40.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 252 22.16% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97 8.53% 70.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 50 4.40% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 53 4.66% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 61 5.36% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21 1.85% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 1.50% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 130 11.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1137 # Bytes accessed per row activation +system.physmem.totQLat 38062500 # Total ticks spent queuing +system.physmem.totMemAccLat 140868750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6941.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26357.79 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25691.91 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s @@ -214,280 +214,281 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4285 # Number of row buffer hits during reads +system.physmem.readRowHits 4339 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.81 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27147536.60 # Average gap between requests -system.physmem.pageHitRate 79.81 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 139292792000 # Time in different power states -system.physmem.memoryStateTime::REF 4866940000 # Time in different power states +system.physmem.avgGap 27099581.43 # Average gap between requests +system.physmem.pageHitRate 79.14 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 141978840750 # Time in different power states +system.physmem.memoryStateTime::REF 4961580000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1591366500 # Time in different power states +system.physmem.memoryStateTime::ACT 1644861750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2357484 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3832 # Transaction distribution -system.membus.trans_dist::ReadResp 3832 # Transaction distribution -system.membus.trans_dist::UpgradeReq 207 # Transaction distribution -system.membus.trans_dist::UpgradeResp 207 # Transaction distribution -system.membus.trans_dist::ReadExReq 1537 # Transaction distribution -system.membus.trans_dist::ReadExResp 1537 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11152 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 343616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 343616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 343616 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 343616 # Total data (bytes) +system.membus.throughput 2361659 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3951 # Transaction distribution +system.membus.trans_dist::ReadResp 3951 # Transaction distribution +system.membus.trans_dist::UpgradeReq 350 # Transaction distribution +system.membus.trans_dist::UpgradeResp 350 # Transaction distribution +system.membus.trans_dist::ReadExReq 1532 # Transaction distribution +system.membus.trans_dist::ReadExResp 1532 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11666 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 350912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 350912 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 350912 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6685000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7101000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50563044 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 51987900 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 19312355 # Number of BP lookups -system.cpu.branchPred.condPredicted 19312355 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1526222 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12165390 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11208509 # Number of BTB hits +system.cpu.branchPred.lookups 22396239 # Number of BP lookups +system.cpu.branchPred.condPredicted 22396239 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1554538 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 14104442 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13258278 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.134399 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1374126 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 24109 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.000727 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1524438 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22257 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 291824777 # number of cpu cycles simulated +system.cpu.numCycles 297174180 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 24324759 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 214691013 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19312355 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12582635 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 56144836 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 16970936 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 176562009 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2090 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11526 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 23234678 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 287353 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 272218372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.300706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.783258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27916282 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 249227309 # Number of instructions fetch has processed +system.cpu.fetch.Branches 22396239 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14782716 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 267173177 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3706948 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 35 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5683 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 49787 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26681234 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 258392 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 296998563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.383031 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.791258 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 217566223 79.92% 79.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2932645 1.08% 81.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2385496 0.88% 81.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2737910 1.01% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3337902 1.23% 84.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3515947 1.29% 85.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4015286 1.48% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2680056 0.98% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33046907 12.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 228914394 77.08% 77.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5078121 1.71% 78.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4142401 1.39% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4790312 1.61% 81.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4897925 1.65% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5093198 1.71% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5344969 1.80% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4001055 1.35% 88.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34736188 11.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 272218372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.066178 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.735685 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35961276 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167476538 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44947862 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8659583 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15173113 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 347461862 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 15173113 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42752504 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116485143 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31994 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 45803186 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51972432 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 340800862 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21864 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 45640903 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 6024783 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 135945 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 394811664 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 947446953 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 625588632 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4495188 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 296998563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075364 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.838657 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16354452 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 230786837 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 26168548 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21835252 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1853474 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 359377278 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1853474 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24140537 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 162592213 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 34818 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 38296584 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70080937 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350637562 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 41127 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 61846506 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7943239 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 152837 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 405833434 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 972943751 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 642292546 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4668888 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 135382214 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2125 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2128 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90643821 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 87211861 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 31146341 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 61275223 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20328080 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 332778184 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4631 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 263626408 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 192005 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111021931 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 233004479 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3386 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 272218372 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.968437 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359512 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 146403984 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2369 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2300 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 128426201 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89689525 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32027647 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63947531 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21534219 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 341381240 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5216 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 266882213 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74332 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119621882 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 250682367 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3971 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 296998563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.898598 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365381 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 146051537 53.65% 53.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54756567 20.11% 73.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34141482 12.54% 86.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19064760 7.00% 93.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11177424 4.11% 97.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4331751 1.59% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1975514 0.73% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 583634 0.21% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135703 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 171353571 57.70% 57.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54179431 18.24% 75.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33564937 11.30% 87.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19156299 6.45% 93.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10836839 3.65% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4376133 1.47% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2240693 0.75% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 893448 0.30% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 397212 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 272218372 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 296998563 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 150028 5.32% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2336090 82.83% 88.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 334182 11.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 240121 7.41% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2588686 79.93% 87.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 410086 12.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210869 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 164756015 62.50% 62.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789411 0.30% 63.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7036440 2.67% 65.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1209865 0.46% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65957948 25.02% 91.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22665860 8.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211280 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167297217 62.69% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 790659 0.30% 63.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035808 2.64% 66.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1214833 0.46% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 66531787 24.93% 91.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22800629 8.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 263626408 # Type of FU issued -system.cpu.iq.rate 0.903372 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2820300 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010698 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 797512450 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 440004694 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 258018761 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4971043 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4096196 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2387913 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262734744 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2501095 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18875446 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 266882213 # Type of FU issued +system.cpu.iq.rate 0.898067 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3238893 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012136 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 829077263 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 457002634 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260953197 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4998951 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4330787 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2399211 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266394178 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2515648 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18924906 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30562274 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18312 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 301481 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10630624 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33039938 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13805 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 330906 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11511930 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50310 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 51585 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15173113 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 84276429 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5906270 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 332782815 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 102069 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 87211861 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 31146341 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2037 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2851984 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 388220 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 301481 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 659051 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 922496 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1581547 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 261729032 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65162827 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1897376 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1853474 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 126194753 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5535533 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 341386456 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110817 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89689525 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32027647 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2236 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2225894 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 376853 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 330906 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 685400 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 928719 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1614119 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264771892 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65665679 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2110321 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87627279 # number of memory reference insts executed -system.cpu.iew.exec_branches 14424837 # Number of branches executed -system.cpu.iew.exec_stores 22464452 # Number of stores executed -system.cpu.iew.exec_rate 0.896870 # Inst execution rate -system.cpu.iew.wb_sent 261068756 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 260406674 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208884231 # num instructions producing a value -system.cpu.iew.wb_consumers 374053492 # num instructions consuming a value +system.cpu.iew.exec_refs 88263450 # number of memory reference insts executed +system.cpu.iew.exec_branches 14588563 # Number of branches executed +system.cpu.iew.exec_stores 22597771 # Number of stores executed +system.cpu.iew.exec_rate 0.890965 # Inst execution rate +system.cpu.iew.wb_sent 264070010 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 263352408 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208938306 # num instructions producing a value +system.cpu.iew.wb_consumers 376948521 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.892339 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.558434 # average fanout of values written-back +system.cpu.iew.wb_rate 0.886189 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554289 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 111590930 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 120072652 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1527972 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 257045259 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.861184 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.643795 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1559859 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 280678389 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.788673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.596070 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 157102684 61.12% 61.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57671303 22.44% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14254075 5.55% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12075323 4.70% 93.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4232227 1.65% 95.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2930251 1.14% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 914346 0.36% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1028677 0.40% 97.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6836373 2.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180909203 64.45% 64.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57692004 20.55% 85.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14189338 5.06% 90.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11904368 4.24% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4187159 1.49% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2885597 1.03% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 913299 0.33% 97.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1056183 0.38% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6941238 2.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 257045259 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 280678389 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -533,241 +534,241 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6836373 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6941238 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 583163200 # The number of ROB reads -system.cpu.rob.rob_writes 681115892 # The number of ROB writes -system.cpu.timesIdled 5968247 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19606405 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 615173187 # The number of ROB reads +system.cpu.rob.rob_writes 699236981 # The number of ROB writes +system.cpu.timesIdled 3132 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 175617 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.209602 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.209602 # CPI: Total CPI of All Threads -system.cpu.ipc 0.452570 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.452570 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 453845201 # number of integer regfile reads -system.cpu.int_regfile_writes 236601026 # number of integer regfile writes -system.cpu.fp_regfile_reads 3267567 # number of floating regfile reads -system.cpu.fp_regfile_writes 2048085 # number of floating regfile writes -system.cpu.cc_regfile_reads 102937064 # number of cc regfile reads -system.cpu.cc_regfile_writes 59977801 # number of cc regfile writes -system.cpu.misc_regfile_reads 135125313 # number of misc regfile reads +system.cpu.cpi 2.250106 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.250106 # CPI: Total CPI of All Threads +system.cpu.ipc 0.444424 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.444424 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 456530694 # number of integer regfile reads +system.cpu.int_regfile_writes 239288826 # number of integer regfile writes +system.cpu.fp_regfile_reads 3276715 # number of floating regfile reads +system.cpu.fp_regfile_writes 2059644 # number of floating regfile writes +system.cpu.cc_regfile_reads 102986535 # number of cc regfile reads +system.cpu.cc_regfile_writes 60205049 # number of cc regfile writes +system.cpu.misc_regfile_reads 136896298 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4014617 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1544 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1544 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4438 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 18480 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 442624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 571776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 571776 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 13376 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4690000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4492019 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 8845 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 38 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1547 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16361 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4810 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 512128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 132544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 644672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 644672 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 22784 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 5429500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11276499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13138750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3488206 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3605850 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4946 # number of replacements -system.cpu.icache.tags.tagsinuse 1631.815497 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23225438 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6919 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3356.762249 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6027 # number of replacements +system.cpu.icache.tags.tagsinuse 1644.648933 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 26670487 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8006 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3331.312391 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1631.815497 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.796785 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.796785 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1973 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 771 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 126 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 811 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.963379 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46476479 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46476479 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23225439 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23225439 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23225439 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23225439 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23225439 # number of overall hits -system.cpu.icache.overall_hits::total 23225439 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9238 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9238 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9238 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9238 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9238 # number of overall misses -system.cpu.icache.overall_misses::total 9238 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 372844498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 372844498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 372844498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 372844498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 372844498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 372844498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23234677 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23234677 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23234677 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23234677 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40359.872050 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40359.872050 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40359.872050 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1450 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1644.648933 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.803051 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.803051 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 791 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 758 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 53370822 # Number of tag accesses +system.cpu.icache.tags.data_accesses 53370822 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 26670487 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26670487 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26670487 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26670487 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26670487 # number of overall hits +system.cpu.icache.overall_hits::total 26670487 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10745 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10745 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10745 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36959.818520 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36959.818520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36959.818520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36959.818520 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1215 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 90.625000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.896552 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7126 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 278959750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 278959750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 278959750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 278959750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 278959750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 278959750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # 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Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3836 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.925182 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2642.321417 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4553 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3966 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.148008 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2.524275 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2264.727526 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 309.415441 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000077 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56930.400372 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3524 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3952 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 350 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 350 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1532 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1532 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3524 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1960 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5484 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56252.871991 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1440.781031 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66638710 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33252.849301 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 91 # number of replacements +system.cpu.dcache.tags.tagsinuse 1449.080763 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 67091510 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2033 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33001.234629 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1440.781031 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351753 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351753 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1947 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 428 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.475342 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 133284338 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 133284338 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46124427 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46124427 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513978 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513978 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66638405 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66638405 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66638405 # number of overall hits -system.cpu.dcache.overall_hits::total 66638405 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1009 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1009 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1753 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1753 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2762 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2762 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2762 # number of overall misses -system.cpu.dcache.overall_misses::total 2762 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63292597 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63292597 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 114179456 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 114179456 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 177472053 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 177472053 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 177472053 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 177472053 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46125436 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46125436 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1449.080763 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353779 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353779 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1942 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 134190055 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 134190055 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46577118 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46577118 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513830 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513830 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67090948 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67090948 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67090948 # number of overall hits +system.cpu.dcache.overall_hits::total 67090948 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1162 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1162 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1901 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1901 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3063 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3063 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3063 # number of overall misses +system.cpu.dcache.overall_misses::total 3063 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64753959 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64753959 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 117721350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 117721350 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 182475309 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 182475309 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 182475309 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 182475309 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46578280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46578280 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66641167 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66641167 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66641167 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66641167 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62728.044599 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62728.044599 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65133.745579 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65133.745579 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64254.906951 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64254.906951 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64254.906951 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64254.906951 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 94 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 67094011 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67094011 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67094011 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67094011 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000093 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000093 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000046 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000046 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000046 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000046 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55726.298623 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55726.298623 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61926.012625 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61926.012625 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59574.047992 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59574.047992 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59574.047992 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59574.047992 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 303 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.600000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 14 # number of writebacks -system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 548 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 548 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 550 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 550 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 550 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 550 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1751 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1751 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2212 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2212 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2212 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2212 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33831000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33831000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109893794 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 109893794 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143724794 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 143724794 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143724794 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 143724794 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 38 # number of writebacks +system.cpu.dcache.writebacks::total 38 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 676 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 676 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 677 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 677 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 677 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 677 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 486 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 486 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1900 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1900 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2386 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2386 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2386 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2386 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33826250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33826250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113234400 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 113234400 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147060650 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 147060650 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147060650 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 147060650 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000085 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000085 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73386.117137 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73386.117137 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62760.590520 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62760.590520 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64975.042495 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64975.042495 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64975.042495 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64975.042495 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000036 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000036 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000036 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000036 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69601.337449 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69601.337449 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59597.052632 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59597.052632 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61634.807209 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61634.807209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61634.807209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61634.807209 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |