summaryrefslogtreecommitdiff
path: root/tests/long/se/70.twolf
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/se/70.twolf')
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini718
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr5
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout28
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt633
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini816
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr1
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout29
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt699
8 files changed, 2929 insertions, 0 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
new file mode 100644
index 000000000..4c4f72a25
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
@@ -0,0 +1,718 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=MinorCPU
+children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=system.cpu.branchPred
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+decodeCycleInput=true
+decodeInputBufferSize=3
+decodeInputWidth=2
+decodeToExecuteForwardDelay=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+enableIdling=true
+eventq_index=0
+executeAllowEarlyMemoryIssue=true
+executeBranchDelay=1
+executeCommitLimit=2
+executeCycleInput=true
+executeFuncUnits=system.cpu.executeFuncUnits
+executeInputBufferSize=7
+executeInputWidth=2
+executeIssueLimit=2
+executeLSQMaxStoreBufferStoresPerCycle=2
+executeLSQRequestsQueueSize=1
+executeLSQStoreBufferSize=5
+executeLSQTransfersQueueSize=2
+executeMaxAccessesInMemory=2
+executeMemoryCommitLimit=1
+executeMemoryIssueLimit=1
+executeMemoryWidth=0
+executeSetTraceTimeOnCommit=true
+executeSetTraceTimeOnIssue=false
+fetch1FetchLimit=1
+fetch1LineSnapWidth=0
+fetch1LineWidth=0
+fetch1ToFetch2BackwardDelay=1
+fetch1ToFetch2ForwardDelay=1
+fetch2CycleInput=true
+fetch2InputBufferSize=2
+fetch2ToDecodeForwardDelay=1
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dtb]
+type=AlphaTLB
+eventq_index=0
+size=64
+
+[system.cpu.executeFuncUnits]
+type=MinorFUPool
+children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
+eventq_index=0
+funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
+
+[system.cpu.executeFuncUnits.funcUnits0]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits0.timings
+
+[system.cpu.executeFuncUnits.funcUnits0.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntAlu
+
+[system.cpu.executeFuncUnits.funcUnits0.timings]
+type=MinorFUTiming
+children=opClasses
+description=Int
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits1]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits1.timings
+
+[system.cpu.executeFuncUnits.funcUnits1.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntAlu
+
+[system.cpu.executeFuncUnits.funcUnits1.timings]
+type=MinorFUTiming
+children=opClasses
+description=Int
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits2]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits2.timings
+
+[system.cpu.executeFuncUnits.funcUnits2.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntMult
+
+[system.cpu.executeFuncUnits.funcUnits2.timings]
+type=MinorFUTiming
+children=opClasses
+description=Mul
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
+srcRegsRelativeLats=0
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits3]
+type=MinorFU
+children=opClasses
+eventq_index=0
+issueLat=9
+opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
+opLat=9
+timings=
+
+[system.cpu.executeFuncUnits.funcUnits3.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntDiv
+
+[system.cpu.executeFuncUnits.funcUnits4]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
+opLat=6
+timings=system.cpu.executeFuncUnits.funcUnits4.timings
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses]
+type=MinorOpClassSet
+children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatAdd
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatCmp
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatCvt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatMult
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatDiv
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatSqrt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdAdd
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdAddAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdAlu
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdCmp
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdCvt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdMisc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdMult
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdMultAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdShift
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdShiftAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdSqrt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatAdd
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatAlu
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatCmp
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatCvt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatDiv
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMisc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMult
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMultAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatSqrt
+
+[system.cpu.executeFuncUnits.funcUnits4.timings]
+type=MinorFUTiming
+children=opClasses
+description=FloatSimd
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits5]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
+opLat=1
+timings=system.cpu.executeFuncUnits.funcUnits5.timings
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses]
+type=MinorOpClassSet
+children=opClasses0 opClasses1
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
+type=MinorOpClass
+eventq_index=0
+opClass=MemRead
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
+type=MinorOpClass
+eventq_index=0
+opClass=MemWrite
+
+[system.cpu.executeFuncUnits.funcUnits5.timings]
+type=MinorFUTiming
+children=opClasses
+description=Mem
+eventq_index=0
+extraAssumedLat=2
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
+srcRegsRelativeLats=1
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits6]
+type=MinorFU
+children=opClasses
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
+opLat=1
+timings=
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses]
+type=MinorOpClassSet
+children=opClasses0 opClasses1
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
+type=MinorOpClass
+eventq_index=0
+opClass=IprAccess
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
+type=MinorOpClass
+eventq_index=0
+opClass=InstPrefetch
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=AlphaISA
+eventq_index=0
+system=system
+
+[system.cpu.itb]
+type=AlphaTLB
+eventq_index=0
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/alpha/tru64/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.membus]
+type=CoherentBus
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=DRAMCtrl
+activation_limit=4
+addr_mapping=RoRaBaChCo
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=300000
+tRP=13750
+tRRD=6250
+tWTR=7500
+tXAW=40000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr
new file mode 100644
index 000000000..506aa6e28
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr
@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout
new file mode 100644
index 000000000..4d57fab87
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout
@@ -0,0 +1,28 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled May 7 2014 10:41:53
+gem5 started May 7 2014 15:05:33
+gem5 executing on cz3212c2d7
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 51810251500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
new file mode 100644
index 000000000..98d3f1024
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
@@ -0,0 +1,633 @@
+
+---------- Begin Simulation Statistics ----------
+final_tick 51810521500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+host_inst_rate 191326 # Simulator instruction rate (inst/s)
+host_mem_usage 251752 # Number of bytes of host memory used
+host_op_rate 191326 # Simulator op (including micro ops) rate (op/s)
+host_seconds 480.35 # Real time elapsed on the host
+host_tick_rate 107860315 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 91903089 # Number of instructions simulated
+sim_ops 91903089 # Number of ops (including micro ops) simulated
+sim_seconds 0.051811 # Number of seconds simulated
+sim_ticks 51810521500 # Number of ticks simulated
+system.clk_domain.clock 1000 # Clock period in ticks
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 79.960972 # BTB Hit Percentage
+system.cpu.branchPred.BTBHits 5346983 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 6686991 # Number of BTB lookups
+system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
+system.cpu.branchPred.condIncorrect 788623 # Number of conditional branches incorrect
+system.cpu.branchPred.condPredicted 8172556 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 11403069 # Number of BP lookups
+system.cpu.branchPred.usedRAS 1173096 # Number of times the RAS was used to get a target.
+system.cpu.committedInsts 91903089 # Number of instructions committed
+system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
+system.cpu.cpi 1.127503 # CPI: cycles per instruction
+system.cpu.dcache.ReadReq_accesses::cpu.inst 20044127 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 20044127 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 69928.365385 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 69928.365385 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 68014.432990 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68014.432990 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits::cpu.inst 20043607 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 20043607 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36362750 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 36362750 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::cpu.inst 520 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 520 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 35 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 35 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 32987000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 32987000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 485 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67476.975945 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 67476.975945 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68165.329513 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68165.329513 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits::cpu.inst 6498193 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 196358000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 196358000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::cpu.inst 2910 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1165 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 118948500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 118948500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1745 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses::cpu.inst 26545230 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 26545230 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67848.615160 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 67848.615160 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68132.511211 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68132.511211 # average overall mshr miss latency
+system.cpu.dcache.demand_hits::cpu.inst 26541800 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 26541800 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency::cpu.inst 232720750 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 232720750 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
+system.cpu.dcache.demand_misses::cpu.inst 3430 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits::cpu.inst 1200 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151935500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 151935500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses::cpu.inst 26545230 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 26545230 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67848.615160 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67848.615160 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68132.511211 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68132.511211 # average overall mshr miss latency
+system.cpu.dcache.overall_hits::cpu.inst 26541800 # number of overall hits
+system.cpu.dcache.overall_hits::total 26541800 # number of overall hits
+system.cpu.dcache.overall_miss_latency::cpu.inst 232720750 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 232720750 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
+system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses
+system.cpu.dcache.overall_misses::total 3430 # number of overall misses
+system.cpu.dcache.overall_mshr_hits::cpu.inst 1200 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151935500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 151935500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id
+system.cpu.dcache.tags.avg_refs 11902.152466 # Average number of references to valid blocks.
+system.cpu.dcache.tags.data_accesses 53092690 # Number of data accesses
+system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.584633 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst 0.353658 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.353658 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.replacements 157 # number of replacements
+system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.tag_accesses 53092690 # Number of tag accesses
+system.cpu.dcache.tags.tagsinuse 1448.584633 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 26541800 # Total number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
+system.cpu.dcache.writebacks::total 107 # number of writebacks
+system.cpu.discardedOps 2238069 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.dtb.data_accesses 27017530 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 26970236 # DTB hits
+system.cpu.dtb.data_misses 47294 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 20437728 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 20390711 # DTB read hits
+system.cpu.dtb.read_misses 47017 # DTB read misses
+system.cpu.dtb.write_accesses 6579802 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 6579525 # DTB write hits
+system.cpu.dtb.write_misses 277 # DTB write misses
+system.cpu.icache.ReadReq_accesses::cpu.inst 22978908 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 22978908 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24673.484027 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 24673.484027 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22586.223937 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22586.223937 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits::cpu.inst 22963225 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 22963225 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 386954250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 386954250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 15683 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 15683 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 354219750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 354219750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15683 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 15683 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses::cpu.inst 22978908 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 22978908 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24673.484027 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 24673.484027 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22586.223937 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22586.223937 # average overall mshr miss latency
+system.cpu.icache.demand_hits::cpu.inst 22963225 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 22963225 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency::cpu.inst 386954250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 386954250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses
+system.cpu.icache.demand_misses::cpu.inst 15683 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 15683 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 354219750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 354219750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses::cpu.inst 15683 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 15683 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses::cpu.inst 22978908 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 22978908 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24673.484027 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 24673.484027 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22586.223937 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22586.223937 # average overall mshr miss latency
+system.cpu.icache.overall_hits::cpu.inst 22963225 # number of overall hits
+system.cpu.icache.overall_hits::total 22963225 # number of overall hits
+system.cpu.icache.overall_miss_latency::cpu.inst 386954250 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 386954250 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses
+system.cpu.icache.overall_misses::cpu.inst 15683 # number of overall misses
+system.cpu.icache.overall_misses::total 15683 # number of overall misses
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 354219750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 354219750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses::cpu.inst 15683 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 15683 # number of overall MSHR misses
+system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 668 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id
+system.cpu.icache.tags.avg_refs 1464.211248 # Average number of references to valid blocks.
+system.cpu.icache.tags.data_accesses 45973499 # Number of data accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst 1641.514711 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.801521 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.801521 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.replacements 13718 # number of replacements
+system.cpu.icache.tags.sampled_refs 15683 # Sample count of references to valid blocks.
+system.cpu.icache.tags.tag_accesses 45973499 # Number of tag accesses
+system.cpu.icache.tags.tagsinuse 1641.514711 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 22963225 # Total number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.idleCycles 2226173 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.ipc 0.886915 # IPC: instructions per cycle
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 22978996 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 22978908 # ITB hits
+system.cpu.itb.fetch_misses 88 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1745 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68029.959279 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68029.959279 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55498.836533 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55498.836533 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits::cpu.inst 26 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 116943500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 116943500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.985100 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst 1719 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95402500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95402500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1719 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 16168 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 16168 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68200.931332 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68200.931332 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55638.518210 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55638.518210 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits::cpu.inst 12571 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 12571 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245318750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 245318750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.222476 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.222476 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 3597 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200131750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200131750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222476 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222476 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 3597 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses::cpu.inst 17913 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 17913 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68145.645222 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68145.645222 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55593.350263 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55593.350263 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits::cpu.inst 12597 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 12597 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency::cpu.inst 362262250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 362262250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.296768 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.296768 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses::cpu.inst 5316 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 5316 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295534250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 295534250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296768 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.296768 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 5316 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 5316 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses::cpu.inst 17913 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 17913 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68145.645222 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68145.645222 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55593.350263 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55593.350263 # average overall mshr miss latency
+system.cpu.l2cache.overall_hits::cpu.inst 12597 # number of overall hits
+system.cpu.l2cache.overall_hits::total 12597 # number of overall hits
+system.cpu.l2cache.overall_miss_latency::cpu.inst 362262250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 362262250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.296768 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.296768 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses::cpu.inst 5316 # number of overall misses
+system.cpu.l2cache.overall_misses::total 5316 # number of overall misses
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295534250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 295534250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296768 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.296768 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 5316 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 5316 # number of overall MSHR misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 767 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 181 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2506 # Occupied blocks per task id
+system.cpu.l2cache.tags.avg_refs 3.435708 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.data_accesses 149568 # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::writebacks 17.784221 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.008081 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075135 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.075677 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 3663 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111786 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.sampled_refs 3663 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.tag_accesses 149568 # Number of tag accesses
+system.cpu.l2cache.tags.tagsinuse 2479.792302 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 12585 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.numCycles 103621043 # number of cpu cycles simulated
+system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.tickCycles 101394870 # Number of cycles that the CPU actually ticked
+system.cpu.toL2Bus.data_through_bus 1153280 # Total data (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31366 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 35933 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 9117000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 24208750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3732500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.throughput 22259571 # Throughput (bytes/s)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1003712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 1153280 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 16168 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 16168 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution
+system.cpu.workload.num_syscalls 389 # Number of system calls
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.membus.data_through_bus 340224 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10632 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 10632 # Packet count per connected master and slave (bytes)
+system.membus.reqLayer0.occupancy 6066000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 49708250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.throughput 6566697 # Throughput (bytes/s)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340224 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 340224 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 3597 # Transaction distribution
+system.membus.trans_dist::ReadResp 3597 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1719 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1719 # Transaction distribution
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgGap 9746132.43 # Average gap between requests
+system.physmem.avgMemAccLat 25349.60 # Average memory access latency per DRAM burst
+system.physmem.avgQLat 6599.60 # Average queueing delay per DRAM burst
+system.physmem.avgRdBW 6.57 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 6.57 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.bw_inst_read::cpu.inst 3909631 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 3909631 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 6566697 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6566697 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 6566697 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6566697 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytesPerActivate::samples 980 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 346.710204 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 212.810529 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 326.902824 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 318 32.45% 32.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 196 20.00% 52.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 101 10.31% 62.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 95 9.69% 72.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 76 7.76% 80.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 37 3.78% 83.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 22 2.24% 86.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 21 2.14% 88.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 114 11.63% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 980 # Bytes accessed per row activation
+system.physmem.bytesReadDRAM 340224 # Total number of bytes read from DRAM
+system.physmem.bytesReadSys 340224 # Total read bytes from the system interface side
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.bytes_inst_read::cpu.inst 202560 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 202560 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 340224 # Number of bytes read from this memory
+system.physmem.bytes_read::total 340224 # Number of bytes read from this memory
+system.physmem.memoryStateTime::IDLE 48729835000 # Time in different power states
+system.physmem.memoryStateTime::REF 1730040000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 1350106250 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.num_reads::cpu.inst 5316 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5316 # Number of read requests responded to by this memory
+system.physmem.pageHitRate 81.55 # Row buffer hit rate, read and write combined
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.perBankRdBursts::0 469 # Per bank write bursts
+system.physmem.perBankRdBursts::1 295 # Per bank write bursts
+system.physmem.perBankRdBursts::2 307 # Per bank write bursts
+system.physmem.perBankRdBursts::3 523 # Per bank write bursts
+system.physmem.perBankRdBursts::4 224 # Per bank write bursts
+system.physmem.perBankRdBursts::5 238 # Per bank write bursts
+system.physmem.perBankRdBursts::6 222 # Per bank write bursts
+system.physmem.perBankRdBursts::7 289 # Per bank write bursts
+system.physmem.perBankRdBursts::8 251 # Per bank write bursts
+system.physmem.perBankRdBursts::9 282 # Per bank write bursts
+system.physmem.perBankRdBursts::10 255 # Per bank write bursts
+system.physmem.perBankRdBursts::11 260 # Per bank write bursts
+system.physmem.perBankRdBursts::12 409 # Per bank write bursts
+system.physmem.perBankRdBursts::13 344 # Per bank write bursts
+system.physmem.perBankRdBursts::14 500 # Per bank write bursts
+system.physmem.perBankRdBursts::15 448 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.rdQLenPdf::0 4911 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 388 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.readBursts 5316 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 5316 # Read request sizes (log2)
+system.physmem.readReqs 5316 # Number of read requests accepted
+system.physmem.readRowHitRate 81.55 # Row buffer hit rate for reads
+system.physmem.readRowHits 4335 # Number of row buffer hits during reads
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.totBusLat 26580000 # Total ticks spent in databus transfers
+system.physmem.totGap 51810440000 # Total gap between requests
+system.physmem.totMemAccLat 134758500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 35083500 # Total ticks spent queuing
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.voltage_domain.voltage 1 # Voltage in Volts
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
new file mode 100644
index 000000000..990a8e3a4
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
@@ -0,0 +1,816 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=MinorCPU
+children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
+branchPred=system.cpu.branchPred
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+decodeCycleInput=true
+decodeInputBufferSize=3
+decodeInputWidth=2
+decodeToExecuteForwardDelay=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+enableIdling=true
+eventq_index=0
+executeAllowEarlyMemoryIssue=true
+executeBranchDelay=1
+executeCommitLimit=2
+executeCycleInput=true
+executeFuncUnits=system.cpu.executeFuncUnits
+executeInputBufferSize=7
+executeInputWidth=2
+executeIssueLimit=2
+executeLSQMaxStoreBufferStoresPerCycle=2
+executeLSQRequestsQueueSize=1
+executeLSQStoreBufferSize=5
+executeLSQTransfersQueueSize=2
+executeMaxAccessesInMemory=2
+executeMemoryCommitLimit=1
+executeMemoryIssueLimit=1
+executeMemoryWidth=0
+executeSetTraceTimeOnCommit=true
+executeSetTraceTimeOnIssue=false
+fetch1FetchLimit=1
+fetch1LineSnapWidth=0
+fetch1LineWidth=0
+fetch1ToFetch2BackwardDelay=1
+fetch1ToFetch2ForwardDelay=1
+fetch2CycleInput=true
+fetch2InputBufferSize=2
+fetch2ToDecodeForwardDelay=1
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[5]
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.executeFuncUnits]
+type=MinorFUPool
+children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
+eventq_index=0
+funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
+
+[system.cpu.executeFuncUnits.funcUnits0]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits0.timings
+
+[system.cpu.executeFuncUnits.funcUnits0.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntAlu
+
+[system.cpu.executeFuncUnits.funcUnits0.timings]
+type=MinorFUTiming
+children=opClasses
+description=Int
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits1]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits1.timings
+
+[system.cpu.executeFuncUnits.funcUnits1.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntAlu
+
+[system.cpu.executeFuncUnits.funcUnits1.timings]
+type=MinorFUTiming
+children=opClasses
+description=Int
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits2]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
+opLat=3
+timings=system.cpu.executeFuncUnits.funcUnits2.timings
+
+[system.cpu.executeFuncUnits.funcUnits2.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntMult
+
+[system.cpu.executeFuncUnits.funcUnits2.timings]
+type=MinorFUTiming
+children=opClasses
+description=Mul
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
+srcRegsRelativeLats=0
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits3]
+type=MinorFU
+children=opClasses
+eventq_index=0
+issueLat=9
+opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
+opLat=9
+timings=
+
+[system.cpu.executeFuncUnits.funcUnits3.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
+
+[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntDiv
+
+[system.cpu.executeFuncUnits.funcUnits4]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
+opLat=6
+timings=system.cpu.executeFuncUnits.funcUnits4.timings
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses]
+type=MinorOpClassSet
+children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatAdd
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatCmp
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatCvt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatMult
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatDiv
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatSqrt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdAdd
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdAddAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdAlu
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdCmp
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdCvt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdMisc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdMult
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdMultAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdShift
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdShiftAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdSqrt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatAdd
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatAlu
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatCmp
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatCvt
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatDiv
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMisc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMult
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMultAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatSqrt
+
+[system.cpu.executeFuncUnits.funcUnits4.timings]
+type=MinorFUTiming
+children=opClasses
+description=FloatSimd
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits5]
+type=MinorFU
+children=opClasses timings
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
+opLat=1
+timings=system.cpu.executeFuncUnits.funcUnits5.timings
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses]
+type=MinorOpClassSet
+children=opClasses0 opClasses1
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
+type=MinorOpClass
+eventq_index=0
+opClass=MemRead
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
+type=MinorOpClass
+eventq_index=0
+opClass=MemWrite
+
+[system.cpu.executeFuncUnits.funcUnits5.timings]
+type=MinorFUTiming
+children=opClasses
+description=Mem
+eventq_index=0
+extraAssumedLat=2
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
+srcRegsRelativeLats=1
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits6]
+type=MinorFU
+children=opClasses
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
+opLat=1
+timings=
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses]
+type=MinorOpClassSet
+children=opClasses0 opClasses1
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
+type=MinorOpClass
+eventq_index=0
+opClass=IprAccess
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
+type=MinorOpClass
+eventq_index=0
+opClass=InstPrefetch
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[4]
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.membus]
+type=CoherentBus
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=DRAMCtrl
+activation_limit=4
+addr_mapping=RoRaBaChCo
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=300000
+tRP=13750
+tRRD=6250
+tWTR=7500
+tXAW=40000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr
new file mode 100644
index 000000000..1a4f96712
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr
@@ -0,0 +1 @@
+warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
new file mode 100644
index 000000000..6876fac87
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
@@ -0,0 +1,29 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled May 7 2014 10:57:46
+gem5 started May 7 2014 13:16:45
+gem5 executing on cz3211bhr8
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu.isa: ISA system set to: 0 0x1c024750
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+info: Increasing stack size by one page.
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 133578736500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
new file mode 100644
index 000000000..6b1426f89
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -0,0 +1,699 @@
+
+---------- Begin Simulation Statistics ----------
+final_tick 133576129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+host_inst_rate 174502 # Simulator instruction rate (inst/s)
+host_mem_usage 298144 # Number of bytes of host memory used
+host_op_rate 191062 # Simulator op (including micro ops) rate (op/s)
+host_seconds 987.48 # Real time elapsed on the host
+host_tick_rate 135269038 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 172317809 # Number of instructions simulated
+sim_ops 188671292 # Number of ops (including micro ops) simulated
+sim_seconds 0.133576 # Number of seconds simulated
+sim_ticks 133576129500 # Number of ticks simulated
+system.clk_domain.clock 1000 # Clock period in ticks
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 95.468318 # BTB Hit Percentage
+system.cpu.branchPred.BTBHits 23338838 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 24446684 # Number of BTB lookups
+system.cpu.branchPred.RASInCorrect 1344 # Number of incorrect RAS predictions.
+system.cpu.branchPred.condIncorrect 5759272 # Number of conditional branches incorrect
+system.cpu.branchPred.condPredicted 40186958 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 50197812 # Number of BP lookups
+system.cpu.branchPred.usedRAS 1870133 # Number of times the RAS was used to get a target.
+system.cpu.committedInsts 172317809 # Number of instructions committed
+system.cpu.committedOps 188671292 # Number of ops (including micro ops) committed
+system.cpu.cpi 1.550346 # CPI: cycles per instruction
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses::cpu.inst 30104490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 30104490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68315.588308 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68315.588308 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66514.624478 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66514.624478 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits::cpu.inst 30103686 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 30103686 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54925733 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 54925733 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::cpu.inst 804 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 804 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 85 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47824015 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 47824015 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 719 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 719 # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70061.205847 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70061.205847 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70028.942571 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70028.942571 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits::cpu.inst 12362645 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 12362645 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115040500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 115040500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::cpu.inst 1642 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1642 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 545 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 545 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76821750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 76821750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1097 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1097 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses::cpu.inst 42468777 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 42468777 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69487.421504 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 69487.421504 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68637.535793 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68637.535793 # average overall mshr miss latency
+system.cpu.dcache.demand_hits::cpu.inst 42466331 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 42466331 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency::cpu.inst 169966233 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 169966233 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::cpu.inst 0.000058 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000058 # miss rate for demand accesses
+system.cpu.dcache.demand_misses::cpu.inst 2446 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2446 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits::cpu.inst 630 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124645765 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 124645765 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses::cpu.inst 1816 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1816 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses::cpu.inst 42468777 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 42468777 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69487.421504 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69487.421504 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68637.535793 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68637.535793 # average overall mshr miss latency
+system.cpu.dcache.overall_hits::cpu.inst 42466331 # number of overall hits
+system.cpu.dcache.overall_hits::total 42466331 # number of overall hits
+system.cpu.dcache.overall_miss_latency::cpu.inst 169966233 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 169966233 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::cpu.inst 0.000058 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000058 # miss rate for overall accesses
+system.cpu.dcache.overall_misses::cpu.inst 2446 # number of overall misses
+system.cpu.dcache.overall_misses::total 2446 # number of overall misses
+system.cpu.dcache.overall_mshr_hits::cpu.inst 630 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124645765 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 124645765 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses::cpu.inst 1816 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1816 # number of overall MSHR misses
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 272 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1362 # Occupied blocks per task id
+system.cpu.dcache.tags.avg_refs 23409.220815 # Average number of references to valid blocks.
+system.cpu.dcache.tags.data_accesses 85028998 # Number of data accesses
+system.cpu.dcache.tags.occ_blocks::cpu.inst 1381.804492 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst 0.337355 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.337355 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 1774 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.433105 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.replacements 42 # number of replacements
+system.cpu.dcache.tags.sampled_refs 1816 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.tag_accesses 85028998 # Number of tag accesses
+system.cpu.dcache.tags.tagsinuse 1381.804492 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 42511145 # Total number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
+system.cpu.dcache.writebacks::total 16 # number of writebacks
+system.cpu.discardedOps 12279677 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.icache.ReadReq_accesses::cpu.inst 71932968 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 71932968 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39567.186956 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 39567.186956 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37371.415126 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37371.415126 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits::cpu.inst 71928261 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 71928261 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 186242749 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 186242749 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 4707 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 4707 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175907251 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 175907251 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4707 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 4707 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses::cpu.inst 71932968 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 71932968 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 39567.186956 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 39567.186956 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37371.415126 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 37371.415126 # average overall mshr miss latency
+system.cpu.icache.demand_hits::cpu.inst 71928261 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 71928261 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency::cpu.inst 186242749 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 186242749 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses
+system.cpu.icache.demand_misses::cpu.inst 4707 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 4707 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175907251 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 175907251 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses::cpu.inst 4707 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 4707 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses::cpu.inst 71932968 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 71932968 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 39567.186956 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 39567.186956 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37371.415126 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37371.415126 # average overall mshr miss latency
+system.cpu.icache.overall_hits::cpu.inst 71928261 # number of overall hits
+system.cpu.icache.overall_hits::total 71928261 # number of overall hits
+system.cpu.icache.overall_miss_latency::cpu.inst 186242749 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 186242749 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses
+system.cpu.icache.overall_misses::cpu.inst 4707 # number of overall misses
+system.cpu.icache.overall_misses::total 4707 # number of overall misses
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175907251 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 175907251 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses::cpu.inst 4707 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 4707 # number of overall MSHR misses
+system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 137 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1065 # Occupied blocks per task id
+system.cpu.icache.tags.avg_refs 15284.373353 # Average number of references to valid blocks.
+system.cpu.icache.tags.data_accesses 143870642 # Number of data accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst 1433.013825 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.699714 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.699714 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1803 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.880371 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.replacements 2903 # number of replacements
+system.cpu.icache.tags.sampled_refs 4706 # Sample count of references to valid blocks.
+system.cpu.icache.tags.tag_accesses 143870642 # Number of tag accesses
+system.cpu.icache.tags.tagsinuse 1433.013825 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 71928261 # Total number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.idleCycles 6392324 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.ipc 0.645017 # IPC: instructions per cycle
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1097 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1097 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69461.202938 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69461.202938 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56942.378329 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56942.378329 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75643250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 75643250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992707 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.992707 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst 1089 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 1089 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62010250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62010250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992707 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992707 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1089 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1089 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 5426 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 5426 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68229.765708 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68229.765708 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55711.085327 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55711.085327 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits::cpu.inst 2609 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2609 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 192203250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 192203250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.519167 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.519167 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 2817 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 2817 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156046750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 156046750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.516218 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.516218 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2801 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 2801 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses::cpu.inst 6523 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 6523 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68573.092678 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68573.092678 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56055.784062 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56055.784062 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits::cpu.inst 2617 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2617 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency::cpu.inst 267846500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 267846500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.598804 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.598804 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses::cpu.inst 3906 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 3906 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 218057000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 218057000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596351 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.596351 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3890 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 3890 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses::cpu.inst 6523 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 6523 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68573.092678 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68573.092678 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56055.784062 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56055.784062 # average overall mshr miss latency
+system.cpu.l2cache.overall_hits::cpu.inst 2617 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2617 # number of overall hits
+system.cpu.l2cache.overall_miss_latency::cpu.inst 267846500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 267846500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.598804 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.598804 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses::cpu.inst 3906 # number of overall misses
+system.cpu.l2cache.overall_misses::total 3906 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 218057000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 218057000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596351 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.596351 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3890 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 3890 # number of overall MSHR misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 51 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 538 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 167 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2015 # Occupied blocks per task id
+system.cpu.l2cache.tags.avg_refs 0.929487 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.data_accesses 56217 # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::writebacks 3.030772 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.746792 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061302 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.061395 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 2808 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.sampled_refs 2808 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.tag_accesses 56217 # Number of tag accesses
+system.cpu.l2cache.tags.tagsinuse 2011.777563 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 2610 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.numCycles 267152259 # number of cpu cycles simulated
+system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.tickCycles 260759935 # Number of cycles that the CPU actually ticked
+system.cpu.toL2Bus.data_through_bus 418432 # Total data (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9413 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 13061 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 3285500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 7520749 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3003735 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.throughput 3132536 # Throughput (bytes/s)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301184 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 117248 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 418432 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 5426 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 5425 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1097 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1097 # Transaction distribution
+system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.membus.data_through_bus 248896 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7778 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 7778 # Packet count per connected master and slave (bytes)
+system.membus.reqLayer0.occupancy 4560000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 36404000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.throughput 1863327 # Throughput (bytes/s)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 248896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 248896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 2800 # Transaction distribution
+system.membus.trans_dist::ReadResp 2800 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1089 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1089 # Transaction distribution
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgGap 34347143.61 # Average gap between requests
+system.physmem.avgMemAccLat 25898.62 # Average memory access latency per DRAM burst
+system.physmem.avgQLat 7148.62 # Average queueing delay per DRAM burst
+system.physmem.avgRdBW 1.86 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.86 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.busUtil 0.01 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.bw_inst_read::cpu.inst 1042102 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1042102 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1863327 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1863327 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1863327 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1863327 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytesPerActivate::samples 942 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 263.473461 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 171.306387 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 278.627261 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 286 30.36% 30.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 373 39.60% 69.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 81 8.60% 78.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 48 5.10% 83.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 26 2.76% 86.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 28 2.97% 89.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 20 2.12% 91.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 18 1.91% 93.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 62 6.58% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 942 # Bytes accessed per row activation
+system.physmem.bytesReadDRAM 248896 # Total number of bytes read from DRAM
+system.physmem.bytesReadSys 248896 # Total read bytes from the system interface side
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.bytes_inst_read::cpu.inst 139200 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 139200 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 248896 # Number of bytes read from this memory
+system.physmem.bytes_read::total 248896 # Number of bytes read from this memory
+system.physmem.memoryStateTime::IDLE 127581858000 # Time in different power states
+system.physmem.memoryStateTime::REF 4460300000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 1531687500 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.num_reads::cpu.inst 3889 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3889 # Number of read requests responded to by this memory
+system.physmem.pageHitRate 75.67 # Row buffer hit rate, read and write combined
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.perBankRdBursts::0 305 # Per bank write bursts
+system.physmem.perBankRdBursts::1 217 # Per bank write bursts
+system.physmem.perBankRdBursts::2 139 # Per bank write bursts
+system.physmem.perBankRdBursts::3 312 # Per bank write bursts
+system.physmem.perBankRdBursts::4 309 # Per bank write bursts
+system.physmem.perBankRdBursts::5 306 # Per bank write bursts
+system.physmem.perBankRdBursts::6 273 # Per bank write bursts
+system.physmem.perBankRdBursts::7 225 # Per bank write bursts
+system.physmem.perBankRdBursts::8 249 # Per bank write bursts
+system.physmem.perBankRdBursts::9 218 # Per bank write bursts
+system.physmem.perBankRdBursts::10 300 # Per bank write bursts
+system.physmem.perBankRdBursts::11 202 # Per bank write bursts
+system.physmem.perBankRdBursts::12 183 # Per bank write bursts
+system.physmem.perBankRdBursts::13 219 # Per bank write bursts
+system.physmem.perBankRdBursts::14 228 # Per bank write bursts
+system.physmem.perBankRdBursts::15 204 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.rdQLenPdf::0 3640 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.readBursts 3889 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 3889 # Read request sizes (log2)
+system.physmem.readReqs 3889 # Number of read requests accepted
+system.physmem.readRowHitRate 75.67 # Row buffer hit rate for reads
+system.physmem.readRowHits 2943 # Number of row buffer hits during reads
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.totBusLat 19445000 # Total ticks spent in databus transfers
+system.physmem.totGap 133576041500 # Total gap between requests
+system.physmem.totMemAccLat 100719750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 27801000 # Total ticks spent queuing
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.voltage_domain.voltage 1 # Voltage in Volts
+
+---------- End Simulation Statistics ----------