diff options
Diffstat (limited to 'tests/long/se/70.twolf')
35 files changed, 702 insertions, 238 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 5ef210362..0cab3c39f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index a267cf67d..c65e040d8 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:52:53 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 46f5e7fc2..a7912f8e0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.042005 # Nu sim_ticks 42005374000 # Number of ticks simulated final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62394 # Simulator instruction rate (inst/s) -host_op_rate 62394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28517940 # Simulator tick rate (ticks/s) -host_mem_usage 218584 # Number of bytes of host memory used -host_seconds 1472.95 # Real time elapsed on the host +host_inst_rate 106867 # Simulator instruction rate (inst/s) +host_op_rate 106867 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48844875 # Simulator tick rate (ticks/s) +host_mem_usage 218932 # Number of bytes of host memory used +host_seconds 859.98 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 316032 # Number of bytes read from this memory -system.physmem.bytes_inst_read 178816 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 4938 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7523609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 4256979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 7523609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory +system.physmem.bytes_read::total 316032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 178816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 178816 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 4256979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3266630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7523609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4256979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4256979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4256979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3266630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7523609 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -155,11 +162,17 @@ system.cpu.icache.demand_accesses::total 10037346 # nu system.cpu.icache.overall_accesses::cpu.inst 10037346 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 10037346 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001168 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001168 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001168 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001168 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001168 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001168 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25187.031037 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25187.031037 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25187.031037 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25187.031037 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 97000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,11 +200,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 228898000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228898000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 228898000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000996 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000996 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000996 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22898.959584 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22898.959584 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22898.959584 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22898.959584 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.tagsinuse 1441.511431 # Cycle average of tags in use @@ -235,13 +254,21 @@ system.cpu.dcache.demand_accesses::total 26497301 # nu system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000852 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000230 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000230 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51433.876812 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51433.876812 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54825.933947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54825.933947 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54518.627934 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54518.627934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 41043500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -277,13 +304,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 116211500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116211500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 116211500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48875.789474 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48875.789474 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53201.086957 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53201.086957 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52276.878093 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52276.878093 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use @@ -348,18 +383,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2223 system.cpu.l2cache.overall_accesses::total 12219 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279512 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.307134 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279512 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.404125 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279512 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.404125 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.181818 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52462.085308 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52337.064677 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52593.495935 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52593.495935 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52426.488457 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52426.488457 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,18 +435,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86326500 system.cpu.l2cache.overall_mshr_miss_latency::total 198396500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307134 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.404125 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.404125 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.952040 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40239.336493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40127.798507 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40270.325203 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40270.325203 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40177.501013 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40177.501013 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index ab521397c..f02146b21 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index ec78af77e..11770df5a 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:19 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:06:35 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 9debfab2e..5f8b8cbb4 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.023638 # Nu sim_ticks 23638033500 # Number of ticks simulated final_tick 23638033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91328 # Simulator instruction rate (inst/s) -host_op_rate 91328 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25645337 # Simulator tick rate (ticks/s) -host_mem_usage 219700 # Number of bytes of host memory used -host_seconds 921.73 # Real time elapsed on the host +host_inst_rate 160213 # Simulator instruction rate (inst/s) +host_op_rate 160213 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44988546 # Simulator tick rate (ticks/s) +host_mem_usage 220112 # Number of bytes of host memory used +host_seconds 525.42 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 336064 # Number of bytes read from this memory -system.physmem.bytes_inst_read 197952 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5251 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 14217088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 8374301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 14217088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 197952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138112 # Number of bytes read from this memory +system.physmem.bytes_read::total 336064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 197952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 197952 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3093 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5251 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8374301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5842787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14217088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8374301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8374301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8374301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5842787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14217088 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -357,11 +364,17 @@ system.cpu.icache.demand_accesses::total 14943347 # nu system.cpu.icache.overall_accesses::cpu.inst 14943347 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 14943347 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000915 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000915 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000915 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14911.104613 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14911.104613 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14911.104613 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14911.104613 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,11 +402,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 130905500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130905500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 130905500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000823 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000823 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000823 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10645.319997 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10645.319997 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10645.319997 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10645.319997 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158 # number of replacements system.cpu.dcache.tagsinuse 1455.343539 # Cycle average of tags in use @@ -445,15 +464,25 @@ system.cpu.dcache.demand_accesses::total 28193388 # nu system.cpu.dcache.overall_accesses::cpu.data 28193388 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 28193388 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001239 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001239 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001825 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001825 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000319 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000319 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000319 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000319 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30077.695560 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30077.695560 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35913.531968 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35913.531968 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35300.188868 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35300.188868 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 6500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -493,15 +522,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 77918500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 77918500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 77918500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000265 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001825 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001825 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32181.017613 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32181.017613 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35616.454229 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35616.454229 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35000 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34831.694233 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34831.694233 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2429.489974 # Cycle average of tags in use @@ -566,18 +605,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2238 system.cpu.l2cache.overall_accesses::total 14535 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.251525 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.277227 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984936 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984936 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.251525 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964254 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.361266 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.251525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964254 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.361266 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.562561 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34414.847162 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34332.723177 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34718.823529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34718.823529 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34457.722339 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34457.722339 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -610,18 +657,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67947000 system.cpu.l2cache.overall_mshr_miss_latency::total 164057500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.277227 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984936 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.361266 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.361266 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.553185 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31251.091703 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31096.451704 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31549.411765 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31549.411765 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31243.096553 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31243.096553 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index d2933f641..418ddecee 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr index 1b49765a7..1ed796979 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout index 0cde8149d..fbcfa0aae 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:43 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:46:55 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 47fe26ecb..4c4ae20f6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2042062 # Simulator instruction rate (inst/s) -host_op_rate 2042061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1021030561 # Simulator tick rate (ticks/s) -host_mem_usage 209388 # Number of bytes of host memory used -host_seconds 45.01 # Real time elapsed on the host +host_inst_rate 3561938 # Simulator instruction rate (inst/s) +host_op_rate 3561935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1780967913 # Simulator tick rate (ticks/s) +host_mem_usage 209744 # Number of bytes of host memory used +host_seconds 25.80 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 475949877 # Number of bytes read from this memory -system.physmem.bytes_inst_read 367612356 # Number of instructions bytes read from this memory -system.physmem.bytes_written 30920974 # Number of bytes written to this memory -system.physmem.num_reads 111899287 # Number of read requests responded to by this memory -system.physmem.num_writes 6501103 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10357641815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999995996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 672903574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11030545389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory +system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory +system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory +system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory +system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index f8f410537..39023eb08 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout index de47399fe..3fe1e7489 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:39:37 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:18:52 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 180c17bb1..5d71f2054 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.118740 # Nu sim_ticks 118740049000 # Number of ticks simulated final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 796943 # Simulator instruction rate (inst/s) -host_op_rate 796942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1029660597 # Simulator tick rate (ticks/s) -host_mem_usage 218284 # Number of bytes of host memory used -host_seconds 115.32 # Real time elapsed on the host +host_inst_rate 1590844 # Simulator instruction rate (inst/s) +host_op_rate 1590843 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2055391195 # Simulator tick rate (ticks/s) +host_mem_usage 218628 # Number of bytes of host memory used +host_seconds 57.77 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 304960 # Number of bytes read from this memory -system.physmem.bytes_inst_read 167744 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 4765 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2568299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1412699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2568299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory +system.physmem.bytes_read::total 304960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1412699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2568299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412699 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412699 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2568299 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total 91903090 # nu system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26935.605170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26935.605170 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26935.605170 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26935.605170 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 203692000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use @@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total 26497301 # nu system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51313.684211 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55375.286041 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54507.422402 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54507.422402 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,13 +244,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 114501000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use @@ -288,18 +323,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2223 system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.338676 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -332,18 +375,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 0883e5a4a..292cbefed 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 2311bc195..f8119727b 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:50:10 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:52:11 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a127da205..15323b4b4 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.076323 # Nu sim_ticks 76322764500 # Number of ticks simulated final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57710 # Simulator instruction rate (inst/s) -host_op_rate 63186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25558377 # Simulator tick rate (ticks/s) -host_mem_usage 235176 # Number of bytes of host memory used -host_seconds 2986.21 # Real time elapsed on the host +host_inst_rate 95790 # Simulator instruction rate (inst/s) +host_op_rate 104880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42423254 # Simulator tick rate (ticks/s) +host_mem_usage 235620 # Number of bytes of host memory used +host_seconds 1799.08 # Real time elapsed on the host sim_insts 172333279 # Number of instructions simulated sim_ops 188686762 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 246592 # Number of bytes read from this memory -system.physmem.bytes_inst_read 133376 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 3853 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3230910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1747526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3230910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 133376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 113216 # Number of bytes read from this memory +system.physmem.bytes_read::total 246592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 133376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 133376 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2084 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1769 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3853 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1747526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1483384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3230910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1747526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1747526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1747526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1483384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3230910 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -368,11 +375,17 @@ system.cpu.icache.demand_accesses::total 37841460 # nu system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000137 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000137 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000137 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21688.113099 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21688.113099 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21688.113099 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,11 +413,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 78893000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17950.625711 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17950.625711 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 59 # number of replacements system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use @@ -460,15 +479,25 @@ system.cpu.dcache.demand_accesses::total 47285356 # nu system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000615 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000200 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32575.806452 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31186.530880 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31459.398099 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31459.398099 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -506,13 +535,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 63473000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63473000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 63473000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31853.855721 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31853.855721 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35155.524605 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35155.524605 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2017.739485 # Cycle average of tags in use @@ -577,18 +614,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1881 system.cpu.l2cache.overall_accesses::total 6276 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.474858 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890547 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.539142 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991643 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.991643 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.474858 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.948432 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.616794 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.474858 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.948432 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.616794 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.109248 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.229050 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34272.743489 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.913858 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34368.913858 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34299.276673 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34299.276673 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -630,18 +675,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.535680 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991643 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.613926 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.613926 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31076.840215 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31044.943820 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index bd55e37b1..b72ac514a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index 1a4090c67..18d32cd6b 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 17:02:03 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:53:41 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 11a4c0835..bbd6c00f1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.103107 # Nu sim_ticks 103106771000 # Number of ticks simulated final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1081638 # Simulator instruction rate (inst/s) -host_op_rate 1184289 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 647201988 # Simulator tick rate (ticks/s) -host_mem_usage 224040 # Number of bytes of host memory used -host_seconds 159.31 # Real time elapsed on the host +host_inst_rate 2060024 # Simulator instruction rate (inst/s) +host_op_rate 2255526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1232622542 # Simulator tick rate (ticks/s) +host_mem_usage 224496 # Number of bytes of host memory used +host_seconds 83.65 # Real time elapsed on the host sim_insts 172317417 # Number of instructions simulated sim_ops 188670900 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 869973902 # Number of bytes read from this memory -system.physmem.bytes_inst_read 759440240 # Number of instructions bytes read from this memory -system.physmem.bytes_written 45252940 # Number of bytes written to this memory -system.physmem.num_reads 219482514 # Number of read requests responded to by this memory -system.physmem.num_writes 12386694 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 8437602047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7365570977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 438893969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 8876496016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 759440240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110533662 # Number of bytes read from this memory +system.physmem.bytes_read::total 869973902 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 759440240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 759440240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory +system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 189860060 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29622454 # Number of read requests responded to by this memory +system.physmem.num_reads::total 219482514 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory +system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7365570977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1072031070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8437602047 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7365570977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7365570977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 438893969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 438893969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7365570977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1510925039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8876496016 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index 98e25ecfe..3e3d3dcbe 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index 97209751d..08e4c719e 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 17:04:54 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:54:15 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 5b0760555..1e695b431 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.232077 # Nu sim_ticks 232077154000 # Number of ticks simulated final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 578450 # Simulator instruction rate (inst/s) -host_op_rate 633465 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 781209577 # Simulator tick rate (ticks/s) -host_mem_usage 233216 # Number of bytes of host memory used -host_seconds 297.07 # Real time elapsed on the host +host_inst_rate 665536 # Simulator instruction rate (inst/s) +host_op_rate 728833 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 898821179 # Simulator tick rate (ticks/s) +host_mem_usage 233632 # Number of bytes of host memory used +host_seconds 258.20 # Real time elapsed on the host sim_insts 171842491 # Number of instructions simulated sim_ops 188185929 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 220992 # Number of bytes read from this memory -system.physmem.bytes_inst_read 110656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 3453 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 952235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 476807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 952235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory +system.physmem.bytes_read::total 220992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 476807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 475428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 952235 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 476807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 476807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 476807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 475428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 952235 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -119,11 +126,17 @@ system.cpu.icache.demand_accesses::total 189860061 # nu system.cpu.icache.overall_accesses::cpu.inst 189860061 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 189860061 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37801.376598 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37801.376598 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37801.376598 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -145,11 +158,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 106179000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 40 # number of replacements system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use @@ -201,13 +220,21 @@ system.cpu.dcache.demand_accesses::total 41964334 # nu system.cpu.dcache.overall_accesses::cpu.data 41964334 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 41964334 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52525.399129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52525.399129 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55694.545455 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54474.007826 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54474.007826 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,13 +262,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 92087000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use @@ -306,18 +341,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1789 system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.631283 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,18 +393,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index b2ac1c016..505ad335a 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout index fe38fbd1a..435dd5018 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:47:40 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 15:01:23 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 417f58ce8..7fc4c3f51 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.096723 # Nu sim_ticks 96722951500 # Number of ticks simulated final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1581365 # Simulator instruction rate (inst/s) -host_op_rate 1581366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 790687708 # Simulator tick rate (ticks/s) -host_mem_usage 217932 # Number of bytes of host memory used -host_seconds 122.33 # Real time elapsed on the host +host_inst_rate 2785942 # Simulator instruction rate (inst/s) +host_op_rate 2785945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1392980356 # Simulator tick rate (ticks/s) +host_mem_usage 218424 # Number of bytes of host memory used +host_seconds 69.44 # Real time elapsed on the host sim_insts 193444531 # Number of instructions simulated sim_ops 193444769 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 997245606 # Number of bytes read from this memory -system.physmem.bytes_inst_read 773782192 # Number of instructions bytes read from this memory -system.physmem.bytes_written 72065412 # Number of bytes written to this memory -system.physmem.num_reads 251180617 # Number of read requests responded to by this memory -system.physmem.num_writes 18976439 # Number of write requests responded to by this memory -system.physmem.num_other 22406 # Number of other requests responded to by this memory -system.physmem.bw_read 10310330594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999985319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 745070440 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11055401034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 773782192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 223463414 # Number of bytes read from this memory +system.physmem.bytes_read::total 997245606 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 773782192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 773782192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory +system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 193445548 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 57735069 # Number of read requests responded to by this memory +system.physmem.num_reads::total 251180617 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory +system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory +system.physmem.num_other::total 22406 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2310345275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10310330594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 745070440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 745070440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3055415715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11055401034 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 193445904 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index af9f6c271..35d8a380c 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout index f7fdf9677..8467606a8 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:49:18 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 15:02:43 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 415ede7b3..170992582 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.270577 # Nu sim_ticks 270576960000 # Number of ticks simulated final_tick 270576960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 668557 # Simulator instruction rate (inst/s) -host_op_rate 668558 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 935131366 # Simulator tick rate (ticks/s) -host_mem_usage 226812 # Number of bytes of host memory used -host_seconds 289.35 # Real time elapsed on the host +host_inst_rate 1394951 # Simulator instruction rate (inst/s) +host_op_rate 1394952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1951161352 # Simulator tick rate (ticks/s) +host_mem_usage 227304 # Number of bytes of host memory used +host_seconds 138.67 # Real time elapsed on the host sim_insts 193444531 # Number of instructions simulated sim_ops 193444769 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 331072 # Number of bytes read from this memory -system.physmem.bytes_inst_read 230208 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5173 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1223578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 850804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1223578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory +system.physmem.bytes_read::total 331072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 850804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850804 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850804 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223578 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 541153920 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 193445549 # nu system.cpu.icache.overall_accesses::cpu.inst 193445549 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 193445549 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26294.433594 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26294.433594 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26294.433594 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 286242000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2 # number of replacements system.cpu.dcache.tagsinuse 1237.197455 # Cycle average of tags in use @@ -159,15 +178,25 @@ system.cpu.dcache.demand_accesses::total 76711508 # nu system.cpu.dcache.overall_accesses::cpu.data 76711508 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 76711508 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -199,15 +228,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 83475000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use @@ -267,18 +306,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1576 system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -311,18 +358,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 59b747474..e9982c78d 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 16:25:20 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 1d5121a0a..9505812e4 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.087752 # Nu sim_ticks 87751730000 # Number of ticks simulated final_tick 87751730000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56809 # Simulator instruction rate (inst/s) -host_op_rate 95217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37745520 # Simulator tick rate (ticks/s) -host_mem_usage 259224 # Number of bytes of host memory used -host_seconds 2324.83 # Real time elapsed on the host +host_inst_rate 66952 # Simulator instruction rate (inst/s) +host_op_rate 112217 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44484510 # Simulator tick rate (ticks/s) +host_mem_usage 236376 # Number of bytes of host memory used +host_seconds 1972.64 # Real time elapsed on the host sim_insts 132071227 # Number of instructions simulated sim_ops 221363017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 345024 # Number of bytes read from this memory -system.physmem.bytes_inst_read 219584 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5391 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3931820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2502332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3931820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 219584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory +system.physmem.bytes_read::total 345024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219584 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3431 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5391 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2502332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1429487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3931820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2502332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2502332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2502332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1429487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3931820 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 175503461 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -323,11 +330,17 @@ system.cpu.icache.demand_accesses::total 25822554 # nu system.cpu.icache.overall_accesses::cpu.inst 25822554 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 25822554 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000352 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000352 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20598.922248 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20598.922248 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20598.922248 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,11 +368,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 130634500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130634500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 130634500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16908.426094 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16908.426094 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 56 # number of replacements system.cpu.dcache.tagsinuse 1426.584624 # Cycle average of tags in use @@ -403,13 +422,21 @@ system.cpu.dcache.demand_accesses::total 68644382 # nu system.cpu.dcache.overall_accesses::cpu.data 68644382 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 68644382 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000036 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32154.792746 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32154.792746 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37945.804196 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37945.804196 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36148.914791 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36148.914791 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,13 +472,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 74414500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74414500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 74414500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32985.260771 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32985.260771 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34949.211909 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34949.211909 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2579.336511 # Cycle average of tags in use @@ -520,19 +555,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 1999 system.cpu.l2cache.overall_accesses::total 9570 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.453177 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929545 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.479341 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994869 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.453177 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.980490 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.563323 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.453177 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.980490 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.563323 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.967356 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34172.371638 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34243.489583 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34168.923275 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34168.923275 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34222.036728 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34222.036728 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -569,20 +613,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60787000 system.cpu.l2cache.overall_mshr_miss_latency::total 167227500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.479341 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994869 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.563323 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.563323 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31020.052083 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index c6c7c62e1..f20b23119 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 16:58:23 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 98c43bfba..52d17f26b 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.131393 # Nu sim_ticks 131393100000 # Number of ticks simulated final_tick 131393100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 560372 # Simulator instruction rate (inst/s) -host_op_rate 939232 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 557494351 # Simulator tick rate (ticks/s) -host_mem_usage 246748 # Number of bytes of host memory used -host_seconds 235.69 # Real time elapsed on the host +host_inst_rate 1290267 # Simulator instruction rate (inst/s) +host_op_rate 2162601 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1283641901 # Simulator tick rate (ticks/s) +host_mem_usage 223844 # Number of bytes of host memory used +host_seconds 102.36 # Real time elapsed on the host sim_insts 132071228 # Number of instructions simulated sim_ops 221363018 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1698379042 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1387955288 # Number of instructions bytes read from this memory -system.physmem.bytes_written 99822189 # Number of bytes written to this memory -system.physmem.num_reads 230176419 # Number of read requests responded to by this memory -system.physmem.num_writes 20515730 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 12925937831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 10563380330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 759721698 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 13685659529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 1387955288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 310423754 # Number of bytes read from this memory +system.physmem.bytes_read::total 1698379042 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1387955288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1387955288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 99822189 # Number of bytes written to this memory +system.physmem.bytes_written::total 99822189 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 173494411 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 56682008 # Number of read requests responded to by this memory +system.physmem.num_reads::total 230176419 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 20515730 # Number of write requests responded to by this memory +system.physmem.num_writes::total 20515730 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10563380330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2362557501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12925937831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10563380330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10563380330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 759721698 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 759721698 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10563380330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3122279199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13685659529 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 262786201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index a97127599..3bc28071d 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 17:00:16 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 1165c8c9e..8ebc5f697 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.250961 # Nu sim_ticks 250960631000 # Number of ticks simulated final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 361817 # Simulator instruction rate (inst/s) -host_op_rate 606437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 687521912 # Simulator tick rate (ticks/s) -host_mem_usage 255672 # Number of bytes of host memory used -host_seconds 365.02 # Real time elapsed on the host +host_inst_rate 653434 # Simulator instruction rate (inst/s) +host_op_rate 1095213 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1241649233 # Simulator tick rate (ticks/s) +host_mem_usage 232776 # Number of bytes of host memory used +host_seconds 202.12 # Real time elapsed on the host sim_insts 132071228 # Number of instructions simulated sim_ops 221363018 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 303040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 181760 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 4735 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1207520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 724257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1207520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory +system.physmem.bytes_read::total 303040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 724257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 483263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1207520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 724257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 724257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 724257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 483263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1207520 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 501921262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 173494412 # nu system.cpu.icache.overall_accesses::cpu.inst 173494412 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 173494412 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39420.856412 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39420.856412 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39420.856412 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39420.856412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 170928000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170928000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 170928000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.145718 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.145718 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.145718 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.145718 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use @@ -151,13 +170,21 @@ system.cpu.dcache.demand_accesses::total 77197738 # nu system.cpu.dcache.overall_accesses::cpu.data 77197738 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 77197738 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55107.033639 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.152091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55920.152091 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55780.577428 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55780.577428 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -185,13 +212,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 100546500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use @@ -256,18 +291,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1905 system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.629357 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52004.905063 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52003.273495 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52003.273495 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,18 +343,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |