diff options
Diffstat (limited to 'tests/long/se/70.twolf')
5 files changed, 4861 insertions, 0 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index e69de29bb..05e39f173 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,764 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.051906 # Number of seconds simulated +sim_ticks 51905634500 # Number of ticks simulated +final_tick 51905634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 261291 # Simulator instruction rate (inst/s) +host_op_rate 261291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 147573427 # Simulator tick rate (ticks/s) +host_mem_usage 252408 # Number of bytes of host memory used +host_seconds 351.73 # Real time elapsed on the host +sim_insts 91903089 # Number of instructions simulated +sim_ops 91903089 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory +system.physmem.bytes_read::total 340480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5320 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3907399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2652198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6559596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3907399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3907399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3907399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2652198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6559596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5320 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5320 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 340480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 340480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 469 # Per bank write bursts +system.physmem.perBankRdBursts::1 295 # Per bank write bursts +system.physmem.perBankRdBursts::2 308 # Per bank write bursts +system.physmem.perBankRdBursts::3 524 # Per bank write bursts +system.physmem.perBankRdBursts::4 224 # Per bank write bursts +system.physmem.perBankRdBursts::5 238 # Per bank write bursts +system.physmem.perBankRdBursts::6 222 # Per bank write bursts +system.physmem.perBankRdBursts::7 289 # Per bank write bursts +system.physmem.perBankRdBursts::8 252 # Per bank write bursts +system.physmem.perBankRdBursts::9 282 # Per bank write bursts +system.physmem.perBankRdBursts::10 254 # Per bank write bursts +system.physmem.perBankRdBursts::11 261 # Per bank write bursts +system.physmem.perBankRdBursts::12 410 # Per bank write bursts +system.physmem.perBankRdBursts::13 344 # Per bank write bursts +system.physmem.perBankRdBursts::14 500 # Per bank write bursts +system.physmem.perBankRdBursts::15 448 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 51905547000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5320 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 346.395112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 212.989816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.326928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 308 31.36% 31.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 213 21.69% 53.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 101 10.29% 63.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 90 9.16% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 7.23% 79.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 3.77% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21 2.14% 85.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 2.95% 88.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 112 11.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation +system.physmem.totQLat 32661000 # Total ticks spent queuing +system.physmem.totMemAccLat 132411000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26600000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6139.29 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 24889.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4334 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 9756681.77 # Average gap between requests +system.physmem.pageHitRate 81.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3515400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1918125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19983600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1736098875 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29619147750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34770724710 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.912241 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49270880000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 899376250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3885840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2120250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21309600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1812535875 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29552097750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34782010275 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.129676 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49159142250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1011440250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 11440185 # Number of BP lookups +system.cpu.branchPred.condPredicted 8207191 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765027 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6076858 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5316207 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 87.482824 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1173724 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26312 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 24255 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2057 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 20416195 # DTB read hits +system.cpu.dtb.read_misses 43360 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 20459555 # DTB read accesses +system.cpu.dtb.write_hits 6579893 # DTB write hits +system.cpu.dtb.write_misses 278 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 6580171 # DTB write accesses +system.cpu.dtb.data_hits 26996088 # DTB hits +system.cpu.dtb.data_misses 43638 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 27039726 # DTB accesses +system.cpu.itb.fetch_hits 22951506 # ITB hits +system.cpu.itb.fetch_misses 90 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 22951596 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 103811269 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 91903089 # Number of instructions committed +system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2181586 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.129573 # CPI: cycles per instruction +system.cpu.ipc 0.885290 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction +system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction +system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction +system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::MemRead 19996208 21.76% 92.93% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 91903089 # Class of committed instruction +system.cpu.tickCycles 102098443 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1712826 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1447.414267 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26572424 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.885202 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.414267 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353373 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353373 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 53153936 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53153936 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20074229 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20074229 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498195 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26572424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26572424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26572424 # number of overall hits +system.cpu.dcache.overall_hits::total 26572424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 521 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 521 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2908 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2908 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3429 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3429 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3429 # number of overall misses +system.cpu.dcache.overall_misses::total 3429 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40464500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40464500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 214055500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 214055500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 254520000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 254520000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 254520000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 254520000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20074750 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20074750 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26575853 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26575853 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26575853 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26575853 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77666.986564 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77666.986564 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73609.181568 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73609.181568 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74225.721785 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74225.721785 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1163 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1163 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1199 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1199 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1199 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1199 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36953000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36953000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131397000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131397000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168350000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 168350000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168350000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 168350000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76191.752577 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76191.752577 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75299.140401 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75299.140401 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency +system.cpu.icache.tags.replacements 13853 # number of replacements +system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15818 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1449.973891 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1642.330146 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801919 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801919 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 672 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 946 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45918830 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45918830 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22935687 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22935687 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22935687 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22935687 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22935687 # number of overall hits +system.cpu.icache.overall_hits::total 22935687 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15819 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15819 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15819 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15819 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15819 # number of overall misses +system.cpu.icache.overall_misses::total 15819 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 406827000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 406827000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 406827000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 406827000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 406827000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 406827000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22951506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22951506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22951506 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22951506 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22951506 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22951506 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25717.618054 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25717.618054 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25717.618054 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25717.618054 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 13853 # number of writebacks +system.cpu.icache.writebacks::total 13853 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15819 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15819 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15819 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15819 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15819 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15819 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 391009000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 391009000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 391009000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 391009000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 391009000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 391009000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24717.681269 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24717.681269 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2479.710860 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 26619 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3667 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.259067 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.780381 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.965355 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 359.965124 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064147 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010985 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.075675 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3667 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2507 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111908 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 261876 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 261876 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 13853 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 13853 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12649 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 12649 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12649 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 12728 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12649 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits +system.cpu.l2cache.overall_hits::total 12728 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1719 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3169 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3169 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 432 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 432 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3169 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2151 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5320 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3169 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses +system.cpu.l2cache.overall_misses::total 5320 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128506000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 128506000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 234465500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 234465500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35663000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 35663000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234465500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164169000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 398634500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234465500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164169000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 398634500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 13853 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13853 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15818 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15818 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 485 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 485 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15818 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2230 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 18048 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15818 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2230 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 18048 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985100 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200341 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200341 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.890722 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.890722 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200341 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964574 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.294770 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200341 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.294770 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74756.253636 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74756.253636 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73987.219943 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73987.219943 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82553.240741 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82553.240741 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74931.296992 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74931.296992 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3169 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3169 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 432 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 432 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111316000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111316000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202775500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202775500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31343000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31343000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202775500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 142659000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 345434500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202775500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 142659000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 345434500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200341 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294770 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294770 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64756.253636 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64756.253636 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63987.219943 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63987.219943 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72553.240741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72553.240741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 32058 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 14010 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 16303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13853 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15818 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45489 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50106 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2048512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18048 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18048 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18048 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 29989000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 23727000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 3601 # Transaction distribution +system.membus.trans_dist::ReadExReq 1719 # Transaction distribution +system.membus.trans_dist::ReadExResp 1719 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3601 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10640 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10640 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 340480 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5320 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5320 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5320 # Request fanout histogram +system.membus.reqLayer0.occupancy 6419000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 28167750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index e69de29bb..685087aff 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,1035 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.021909 # Number of seconds simulated +sim_ticks 21909208500 # Number of ticks simulated +final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 161119 # Simulator instruction rate (inst/s) +host_op_rate 161119 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41933875 # Simulator tick rate (ticks/s) +host_mem_usage 253948 # Number of bytes of host memory used +host_seconds 522.47 # Real time elapsed on the host +sim_insts 84179709 # Number of instructions simulated +sim_ops 84179709 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 334528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8944550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6324281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15268831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8944550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8944550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8944550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6324281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15268831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5227 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 470 # Per bank write bursts +system.physmem.perBankRdBursts::1 291 # Per bank write bursts +system.physmem.perBankRdBursts::2 302 # Per bank write bursts +system.physmem.perBankRdBursts::3 523 # Per bank write bursts +system.physmem.perBankRdBursts::4 220 # Per bank write bursts +system.physmem.perBankRdBursts::5 223 # Per bank write bursts +system.physmem.perBankRdBursts::6 218 # Per bank write bursts +system.physmem.perBankRdBursts::7 288 # Per bank write bursts +system.physmem.perBankRdBursts::8 239 # Per bank write bursts +system.physmem.perBankRdBursts::9 278 # Per bank write bursts +system.physmem.perBankRdBursts::10 249 # Per bank write bursts +system.physmem.perBankRdBursts::11 251 # Per bank write bursts +system.physmem.perBankRdBursts::12 395 # Per bank write bursts +system.physmem.perBankRdBursts::13 339 # Per bank write bursts +system.physmem.perBankRdBursts::14 492 # Per bank write bursts +system.physmem.perBankRdBursts::15 449 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 21909113500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5227 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.435239 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 233.348968 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.138574 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 246 28.70% 28.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186 21.70% 50.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 85 9.92% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 7.58% 67.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37 4.32% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 35 4.08% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 34 3.97% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 49 5.72% 86.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 120 14.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 857 # Bytes accessed per row activation +system.physmem.totQLat 42496500 # Total ticks spent queuing +system.physmem.totMemAccLat 140502750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8130.19 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26880.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4359 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 4191527.36 # Average gap between requests +system.physmem.pageHitRate 83.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3076920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1678875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19468800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 930163050 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12325856250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14710823175 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.635656 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20502630500 # Time in different power states +system.physmem_0.memoryStateTime::REF 731380000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 668984500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20771400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 904676355 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12348213000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14709404805 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.570899 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20540502500 # Time in different power states +system.physmem_1.memoryStateTime::REF 731380000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 632027000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 16102191 # Number of BP lookups +system.cpu.branchPred.condPredicted 11688099 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 930994 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8963309 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7508263 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 83.766642 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1594548 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 465 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 29370 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3646 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 24064579 # DTB read hits +system.cpu.dtb.read_misses 206327 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 24270906 # DTB read accesses +system.cpu.dtb.write_hits 7168860 # DTB write hits +system.cpu.dtb.write_misses 1193 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7170053 # DTB write accesses +system.cpu.dtb.data_hits 31233439 # DTB hits +system.cpu.dtb.data_misses 207520 # DTB misses +system.cpu.dtb.data_acv 4 # DTB access violations +system.cpu.dtb.data_accesses 31440959 # DTB accesses +system.cpu.itb.fetch_hits 15932703 # ITB hits +system.cpu.itb.fetch_misses 79 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 15932782 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 43818418 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 16643559 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137979359 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16102191 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9128535 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25956071 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1939868 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2614 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15932703 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367699 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43572351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.166672 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433625 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19392056 44.51% 44.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2618542 6.01% 50.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1330036 3.05% 53.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1934112 4.44% 58.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3001913 6.89% 64.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1292242 2.97% 67.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1355704 3.11% 70.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 886645 2.03% 73.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11761101 26.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 43572351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367475 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.148890 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12867028 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8206518 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19434084 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2106116 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 958605 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2654233 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11853 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132149690 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49712 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 958605 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13986113 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4641138 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10397 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20305818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3670280 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128777120 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70822 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2026790 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1359443 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 54939 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94599417 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167333836 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159779688 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7554147 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 26172056 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 950 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8271760 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26904379 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8704430 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3459754 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1614105 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111855372 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1919 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99762873 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119457 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27677581 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21095041 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1530 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43572351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.289591 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11226739 25.77% 25.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7658694 17.58% 43.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7470474 17.14% 60.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5702469 13.09% 73.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4463101 10.24% 83.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2983064 6.85% 90.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2041659 4.69% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1171062 2.69% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 855089 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43572351 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 483998 20.16% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34928 1.45% 21.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12187 0.51% 22.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1012495 42.17% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 694978 28.95% 93.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 161680 6.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60663003 60.81% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2847512 2.85% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2443315 2.45% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314199 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24854808 24.91% 92.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7268585 7.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 99762873 # Type of FU issued +system.cpu.iq.rate 2.276734 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2400804 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024065 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229929463 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129921880 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89757813 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15688895 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9653551 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7189472 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93781732 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8381938 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1923340 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 6908181 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11335 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40937 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2203327 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 42874 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1494 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 958605 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3611196 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 465334 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122779718 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241439 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26904379 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8704430 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1919 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38387 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 421097 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40937 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502390 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034339 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98437326 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24271451 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1325547 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 10922427 # number of nop insts executed +system.cpu.iew.exec_refs 31441543 # number of memory reference insts executed +system.cpu.iew.exec_branches 12471856 # Number of branches executed +system.cpu.iew.exec_stores 7170092 # Number of stores executed +system.cpu.iew.exec_rate 2.246483 # Inst execution rate +system.cpu.iew.wb_sent 97646069 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96947285 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66976790 # num instructions producing a value +system.cpu.iew.wb_consumers 94960923 # num instructions consuming a value +system.cpu.iew.wb_rate 2.212478 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705309 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 30878414 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 919665 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39078577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.351750 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.919984 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14680368 37.57% 37.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8532696 21.83% 59.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3879932 9.93% 69.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1909819 4.89% 74.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1376650 3.52% 77.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1035169 2.65% 80.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692226 1.77% 82.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 728499 1.86% 84.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6243218 15.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39078577 # Number of insts commited each cycle +system.cpu.commit.committedInsts 91903055 # Number of instructions committed +system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 26497301 # Number of memory references committed +system.cpu.commit.loads 19996198 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 10240685 # Number of branches committed +system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. +system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. +system.cpu.commit.function_calls 1029620 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 51001453 55.49% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 19996198 21.76% 92.93% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction +system.cpu.commit.bw_lim_events 6243218 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155615788 # The number of ROB reads +system.cpu.rob.rob_writes 250112160 # The number of ROB writes +system.cpu.timesIdled 4756 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 246067 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 84179709 # Number of Instructions Simulated +system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.520534 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520534 # CPI: Total CPI of All Threads +system.cpu.ipc 1.921103 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.921103 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133011224 # number of integer regfile reads +system.cpu.int_regfile_writes 72905073 # number of integer regfile writes +system.cpu.fp_regfile_reads 6263399 # number of floating regfile reads +system.cpu.fp_regfile_writes 6178143 # number of floating regfile writes +system.cpu.misc_regfile_reads 719113 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.replacements 158 # number of replacements +system.cpu.dcache.tags.tagsinuse 1457.375474 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28588753 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12734.411136 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.375474 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355805 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355805 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 536 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57198843 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57198843 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22095651 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22095651 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492632 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492632 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28588283 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28588283 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28588283 # number of overall hits +system.cpu.dcache.overall_hits::total 28588283 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1074 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1074 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8471 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8471 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9545 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9545 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9545 # number of overall misses +system.cpu.dcache.overall_misses::total 9545 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 71413000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 71413000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 546757246 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 546757246 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 618170246 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 618170246 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 618170246 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 618170246 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22096725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22096725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28597828 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28597828 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28597828 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28597828 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001303 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001303 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66492.551210 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66492.551210 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64544.592846 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64544.592846 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64763.776427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64763.776427 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32543 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 392 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.017857 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 559 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 559 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6742 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6742 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1729 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1729 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39779500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39779500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135885995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 135885995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 175665495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 175665495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 175665495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 175665495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002123 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002123 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77241.747573 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77241.747573 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78592.246964 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78592.246964 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency +system.cpu.icache.tags.replacements 9515 # number of replacements +system.cpu.icache.tags.tagsinuse 1600.928709 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15918297 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11453 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1389.880119 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.928709 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781703 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781703 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 31876857 # Number of tag accesses +system.cpu.icache.tags.data_accesses 31876857 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15918297 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15918297 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15918297 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15918297 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15918297 # number of overall hits +system.cpu.icache.overall_hits::total 15918297 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14405 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14405 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14405 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14405 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14405 # number of overall misses +system.cpu.icache.overall_misses::total 14405 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 446574000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 446574000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 446574000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 446574000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 446574000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 446574000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15932702 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15932702 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15932702 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15932702 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15932702 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15932702 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000904 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000904 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000904 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000904 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000904 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000904 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31001.318986 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31001.318986 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31001.318986 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31001.318986 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31001.318986 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31001.318986 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 9515 # number of writebacks +system.cpu.icache.writebacks::total 9515 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2951 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2951 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2951 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2951 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2951 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2951 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11454 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11454 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11454 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11454 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11454 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11454 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 336702000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 336702000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 336702000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 336702000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 336702000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 336702000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000719 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000719 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29396.018858 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29396.018858 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2407.364249 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 18027 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3589 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 5.022848 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.652891 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.506649 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 381.204708 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061295 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011633 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073467 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3589 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 192294 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 192294 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 9515 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 9515 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8392 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 8392 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 54 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 54 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8392 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8472 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8392 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits +system.cpu.l2cache.overall_hits::total 8472 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1703 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1703 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3062 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3062 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 462 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 462 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3062 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5227 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses +system.cpu.l2cache.overall_misses::total 5227 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 132876500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 132876500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 231097000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 231097000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38506000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 38506000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 231097000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 171382500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 402479500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 231097000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 171382500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 402479500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 108 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 108 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 9515 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 9515 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1729 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1729 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11454 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 11454 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 516 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 516 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 11454 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13699 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11454 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 13699 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984962 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984962 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.267330 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.267330 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.895349 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.895349 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267330 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964365 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.381561 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267330 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.381561 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78024.955960 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78024.955960 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75472.566950 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75472.566950 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83346.320346 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83346.320346 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77000.095657 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77000.095657 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1703 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1703 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3062 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3062 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 462 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 462 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3062 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115846500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115846500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200477000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200477000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33886000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33886000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200477000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149732500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 350209500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200477000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149732500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 350209500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984962 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984962 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267330 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.895349 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.895349 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.381561 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.381561 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68024.955960 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68024.955960 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65472.566950 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65472.566950 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73346.320346 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73346.320346 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 23372 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9673 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1729 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1729 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 516 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32422 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4648 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 37070 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1492544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 13699 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13699 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 13699 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21309000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 17179500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 3524 # Transaction distribution +system.membus.trans_dist::ReadExReq 1703 # Transaction distribution +system.membus.trans_dist::ReadExResp 1703 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3524 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5227 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5227 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5227 # Request fanout histogram +system.membus.reqLayer0.occupancy 6276500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 27456000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index e69de29bb..28e1374ff 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,882 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.130383 # Number of seconds simulated +sim_ticks 130382890500 # Number of ticks simulated +final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 181123 # Simulator instruction rate (inst/s) +host_op_rate 190933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137045131 # Simulator tick rate (ticks/s) +host_mem_usage 270196 # Number of bytes of host memory used +host_seconds 951.39 # Real time elapsed on the host +sim_insts 172317810 # Number of instructions simulated +sim_ops 181650743 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory +system.physmem.bytes_read::total 247424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1059280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 838392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1897672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1059280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1059280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1059280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 838392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1897672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3866 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 247424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 247424 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 305 # Per bank write bursts +system.physmem.perBankRdBursts::1 217 # Per bank write bursts +system.physmem.perBankRdBursts::2 135 # Per bank write bursts +system.physmem.perBankRdBursts::3 313 # Per bank write bursts +system.physmem.perBankRdBursts::4 306 # Per bank write bursts +system.physmem.perBankRdBursts::5 305 # Per bank write bursts +system.physmem.perBankRdBursts::6 273 # Per bank write bursts +system.physmem.perBankRdBursts::7 222 # Per bank write bursts +system.physmem.perBankRdBursts::8 248 # Per bank write bursts +system.physmem.perBankRdBursts::9 218 # Per bank write bursts +system.physmem.perBankRdBursts::10 295 # Per bank write bursts +system.physmem.perBankRdBursts::11 200 # Per bank write bursts +system.physmem.perBankRdBursts::12 183 # Per bank write bursts +system.physmem.perBankRdBursts::13 218 # Per bank write bursts +system.physmem.perBankRdBursts::14 224 # Per bank write bursts +system.physmem.perBankRdBursts::15 204 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 130382796000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 3866 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 268.939891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.781102 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 276.529935 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 273 29.84% 29.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 347 37.92% 67.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 83 9.07% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 59 6.45% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 3.83% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 24 2.62% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 16 1.75% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20 2.19% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 58 6.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 915 # Bytes accessed per row activation +system.physmem.totQLat 27071500 # Total ticks spent queuing +system.physmem.totMemAccLat 99559000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7002.46 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25752.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.01 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 2948 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 33725503.36 # Average gap between requests +system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3144960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1716000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3562127505 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75103936500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 87202954965 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.831686 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 124939990750 # Time in different power states +system.physmem_0.memoryStateTime::REF 4353700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1087339250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3764880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2054250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3544157970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.803682 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states +system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 49622074 # Number of BP lookups +system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 260765781 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 172317810 # Number of instructions committed +system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed +system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.513284 # CPI: cycles per instruction +system.cpu.ipc 0.660815 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction +system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction +system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction +system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 181650743 # Class of committed instruction +system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 42 # number of replacements +system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40709197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40709197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40709659 # number of overall hits +system.cpu.dcache.overall_hits::total 40709659 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses +system.cpu.dcache.overall_misses::total 2441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59629000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59629000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126003000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126003000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 185632000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 185632000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 185632000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 185632000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28347350 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28347350 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 40711637 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40711637 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712100 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712100 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76078.688525 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52555500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52555500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85213000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85213000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137768500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137768500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137838500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 137838500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency +system.cpu.icache.tags.replacements 2881 # number of replacements +system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses +system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits +system.cpu.icache.overall_hits::total 70779397 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4678 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4678 # number of overall misses +system.cpu.icache.overall_misses::total 4678 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 198432500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 198432500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 198432500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 198432500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 198432500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 198432500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 70784075 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 70784075 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 70784075 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 70784075 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 70784075 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 70784075 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42418.234288 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42418.234288 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42418.234288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 2881 # number of writebacks +system.cpu.icache.writebacks::total 2881 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4678 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4678 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4678 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4678 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4678 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4678 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193755500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 193755500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 193755500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 193755500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 193755500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 193755500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 489.811820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061021 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2783 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2559 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2517 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2517 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 81 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 81 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2517 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 89 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2606 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2517 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 89 # number of overall hits +system.cpu.l2cache.overall_hits::total 2606 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2161 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2161 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 631 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 631 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2161 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3883 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses +system.cpu.l2cache.overall_misses::total 3883 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83479000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 83479000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 159937500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 159937500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50622000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 50622000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 159937500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 134101000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294038500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 159937500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 134101000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294038500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2559 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2559 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4678 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4678 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4678 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6489 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4678 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6489 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461950 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461950 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886236 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886236 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461950 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.950856 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.598397 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461950 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.950856 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.598397 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75724.568633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2159 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2159 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72569000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72569000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 138134000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 138134000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43490000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43490000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138134000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116059000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 254193000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138134000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116059000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 254193000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461522 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595932 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595932 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15900 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 600640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6489 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.071197 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.257174 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6027 92.88% 92.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 462 7.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 2775 # Transaction distribution +system.membus.trans_dist::ReadExReq 1091 # Transaction distribution +system.membus.trans_dist::ReadExResp 1091 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247424 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3866 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3866 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3866 # Request fanout histogram +system.membus.reqLayer0.occupancy 4516500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 20548250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index e69de29bb..5e6d9ee12 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -0,0 +1,1172 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.084938 # Number of seconds simulated +sim_ticks 84937723500 # Number of ticks simulated +final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 96546 # Simulator instruction rate (inst/s) +host_op_rate 101775 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47592642 # Simulator tick rate (ticks/s) +host_mem_usage 268276 # Number of bytes of host memory used +host_seconds 1784.68 # Real time elapsed on the host +sim_insts 172303022 # Number of instructions simulated +sim_ops 181635954 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory +system.physmem.bytes_read::total 790400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 587328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 587328 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 9177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1109 # Number of read requests responded to by this memory +system.physmem.num_reads::total 12350 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 6914807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1555210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9305641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6914807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6914807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6914807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1555210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9305641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12351 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 12351 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 790464 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 790464 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1113 # Per bank write bursts +system.physmem.perBankRdBursts::1 381 # Per bank write bursts +system.physmem.perBankRdBursts::2 5089 # Per bank write bursts +system.physmem.perBankRdBursts::3 423 # Per bank write bursts +system.physmem.perBankRdBursts::4 1959 # Per bank write bursts +system.physmem.perBankRdBursts::5 424 # Per bank write bursts +system.physmem.perBankRdBursts::6 265 # Per bank write bursts +system.physmem.perBankRdBursts::7 373 # Per bank write bursts +system.physmem.perBankRdBursts::8 266 # Per bank write bursts +system.physmem.perBankRdBursts::9 219 # Per bank write bursts +system.physmem.perBankRdBursts::10 295 # Per bank write bursts +system.physmem.perBankRdBursts::11 324 # Per bank write bursts +system.physmem.perBankRdBursts::12 199 # Per bank write bursts +system.physmem.perBankRdBursts::13 249 # Per bank write bursts +system.physmem.perBankRdBursts::14 229 # Per bank write bursts +system.physmem.perBankRdBursts::15 543 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 84937714500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 12351 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 7250 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 108.738207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 85.269087 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 131.624325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5249 72.40% 72.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1564 21.57% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 167 2.30% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 93 1.28% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 42 0.58% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 24 0.33% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 0.25% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 0.29% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 72 0.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 7250 # Bytes accessed per row activation +system.physmem.totQLat 171430514 # Total ticks spent queuing +system.physmem.totMemAccLat 403011764 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 61755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13879.89 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32629.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 9.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 9.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 5094 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 6876990.89 # Average gap between requests +system.physmem.pageHitRate 41.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 48452040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 26437125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 78179400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16645874445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36357960750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 58704276240 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.186004 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 60381088491 # Time in different power states +system.physmem_0.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21718991509 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6335280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3456750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 17877600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3295031490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48069226500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56939300100 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.405119 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 79958437412 # Time in different power states +system.physmem_1.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 85626366 # Number of BP lookups +system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39946926 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38187698 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 95.596087 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683716 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81912 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681689 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 653746 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 169875448 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 5671940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347162762 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85626366 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42525160 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 157499775 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11884731 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 3808 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78326624 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18246 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169120520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.147875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.049260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17456404 10.32% 10.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30071791 17.78% 28.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31598997 18.68% 46.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89993328 53.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 169120520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.504054 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.043631 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17509987 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17244874 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121866560 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6731455 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5767644 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11064434 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189777 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304997911 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27240618 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5767644 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37477523 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8502539 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 578983 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108355768 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8438063 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277420851 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13180734 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3058487 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 843003 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2280960 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 36243 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27083 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481449871 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1191735135 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296461789 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3004325 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 188472942 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23603 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23603 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13353784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33915046 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14407100 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2540378 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1803003 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263798584 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45955 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214411803 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5187874 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82208585 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 217092419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169120520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.267805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017994 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52408217 30.99% 30.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35940187 21.25% 52.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65510990 38.74% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13642635 8.07% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570936 0.93% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47343 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 212 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169120520 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35659439 66.16% 66.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153265 0.28% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35730 0.07% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34286 0.06% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14056522 26.08% 92.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3955910 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166992897 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919175 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165179 0.08% 78.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245702 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460499 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206683 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31868874 14.86% 93.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13371819 6.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 214411803 # Type of FU issued +system.cpu.iq.rate 1.262171 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53897621 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251374 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653076785 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344050437 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204251594 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952836 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2009578 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806333 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266175663 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133761 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1598827 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 6018902 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7034 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1762466 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 25527 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 769 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 5767644 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5618767 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 62916 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263864756 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 33915046 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14407100 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23547 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3855 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 55872 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7034 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3149041 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246654 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6395695 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207125960 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30633355 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7285843 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 20217 # number of nop insts executed +system.cpu.iew.exec_refs 43771495 # number of memory reference insts executed +system.cpu.iew.exec_branches 44852998 # Number of branches executed +system.cpu.iew.exec_stores 13138140 # Number of stores executed +system.cpu.iew.exec_rate 1.219281 # Inst execution rate +system.cpu.iew.wb_sent 206368045 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206057927 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129397136 # num instructions producing a value +system.cpu.iew.wb_consumers 221651580 # num instructions consuming a value +system.cpu.iew.wb_rate 1.212994 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583786 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68672645 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 5760731 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157823719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.150970 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.652577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73232232 46.40% 46.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41142749 26.07% 72.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22534270 14.28% 86.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9514853 6.03% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3552076 2.25% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2143258 1.36% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1327703 0.84% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1008942 0.64% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3367636 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157823719 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172317410 # Number of instructions committed +system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 40540778 # Number of memory references committed +system.cpu.commit.loads 27896144 # Number of loads committed +system.cpu.commit.membars 22408 # Number of memory barriers committed +system.cpu.commit.branches 40300312 # Number of branches committed +system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. +system.cpu.commit.int_insts 143085667 # Number of committed integer instructions. +system.cpu.commit.function_calls 1848934 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 138987813 76.51% 76.51% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction +system.cpu.commit.bw_lim_events 3367636 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 404773869 # The number of ROB reads +system.cpu.rob.rob_writes 511956769 # The number of ROB writes +system.cpu.timesIdled 9030 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 754928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172303022 # Number of Instructions Simulated +system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.985911 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.985911 # CPI: Total CPI of All Threads +system.cpu.ipc 1.014290 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.014290 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218725741 # number of integer regfile reads +system.cpu.int_regfile_writes 114168991 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904222 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441435 # number of floating regfile writes +system.cpu.cc_regfile_reads 708194084 # number of cc regfile reads +system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes +system.cpu.misc_regfile_reads 59249203 # number of misc regfile reads +system.cpu.misc_regfile_writes 820036 # number of misc regfile writes +system.cpu.dcache.tags.replacements 72581 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.355766 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 508221500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.413915 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998855 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998855 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341311 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40986258 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40986258 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40986622 # number of overall hits +system.cpu.dcache.overall_hits::total 40986622 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89227 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89227 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22976 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22976 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112203 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112203 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112319 # number of overall misses +system.cpu.dcache.overall_misses::total 112319 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1066843000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1066843000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 241030499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 241030499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2297500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2297500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1307873499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1307873499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1307873499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1307873499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28734174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28734174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 41098461 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41098461 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41098941 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41098941 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8870.656371 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8870.656371 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11656.314885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11644.276561 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10738 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72581 # number of writebacks +system.cpu.dcache.writebacks::total 72581 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24802 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14421 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14421 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39223 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39223 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39223 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39223 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64425 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64425 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8555 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8555 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 72980 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72980 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73093 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73093 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 653903000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 653903000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85317499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85317499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 739220499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 739220499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 740182499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 740182499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10149.833139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10149.833139 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9972.822794 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9972.822794 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency +system.cpu.icache.tags.replacements 53623 # number of replacements +system.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54135 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1445.812413 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84183071500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.594536 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 51 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78269055 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78269055 # number of overall hits +system.cpu.icache.overall_hits::total 78269055 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57535 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57535 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57535 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57535 # number of overall misses +system.cpu.icache.overall_misses::total 57535 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1155198430 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1155198430 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1155198430 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1155198430 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1155198430 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1155198430 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78326590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78326590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78326590 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78326590 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78326590 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78326590 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20078.185974 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20078.185974 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20078.185974 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20078.185974 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 73195 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3246 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.549291 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 53623 # number of writebacks +system.cpu.icache.writebacks::total 53623 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3399 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3399 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3399 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3399 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3399 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3399 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54136 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54136 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54136 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54136 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54136 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54136 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1039886452 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1039886452 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1039886452 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1039886452 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1039886452 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1039886452 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19208.778853 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19208.778853 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2141.370901 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 157591 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3198 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 49.277986 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 1986.257511 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 155.113391 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.121232 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009467 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.130699 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 254 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2944 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 24 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 87 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 856 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1653 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.179688 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3955418 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3955418 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 64698 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 64698 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 51033 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 51033 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8387 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8387 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 44953 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 44953 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 62632 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 62632 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 44953 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 71019 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 115972 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 44953 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 71019 # number of overall hits +system.cpu.l2cache.overall_hits::total 115972 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 235 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 235 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9183 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 9183 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1839 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1839 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 9183 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2074 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 11257 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 9183 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2074 # number of overall misses +system.cpu.l2cache.overall_misses::total 11257 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18101500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 18101500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 689865000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 689865000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 142794500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 142794500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 689865000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 160896000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 850761000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 689865000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 160896000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 850761000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 64698 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 64698 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 51033 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 51033 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 8622 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 8622 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54136 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 54136 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64471 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 64471 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 54136 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 73093 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 127229 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 54136 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 73093 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 127229 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027256 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.027256 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.169628 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.169628 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.028524 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.028524 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.169628 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.028375 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.088478 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.169628 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.028375 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.088478 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77027.659574 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77027.659574 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75124.142437 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75124.142437 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77647.906471 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77647.906471 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75124.142437 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77577.627772 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75576.174825 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75124.142437 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77577.627772 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75576.174825 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 9 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2007 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 2007 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 234 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 234 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9178 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9178 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1830 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1830 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9178 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2064 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 11242 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9178 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2064 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2007 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 13249 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 68828649 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 68828649 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16491500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16491500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 634496500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 634496500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 131272000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 131272000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 634496500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147763500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 782260000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 634496500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147763500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68828649 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 851088649 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027140 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027140 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.169536 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028385 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028385 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.088360 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.104135 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 11007 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54136 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64471 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380661 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6896512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16219648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 13357 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 140586 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.219979 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.541213 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118188 84.07% 84.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13870 9.87% 93.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 8528 6.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 140586 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252920500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 81207989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 12116 # Transaction distribution +system.membus.trans_dist::ReadExReq 234 # Transaction distribution +system.membus.trans_dist::ReadExResp 234 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 12117 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24701 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 24701 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 790400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 790400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 12351 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 12351 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 12351 # Request fanout histogram +system.membus.reqLayer0.occupancy 15618188 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 66520835 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index e69de29bb..87cd506ee 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -0,0 +1,1008 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.103324 # Number of seconds simulated +sim_ticks 103324153500 # Number of ticks simulated +final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 48808 # Simulator instruction rate (inst/s) +host_op_rate 81806 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38183996 # Simulator tick rate (ticks/s) +host_mem_usage 302208 # Number of bytes of host memory used +host_seconds 2705.95 # Real time elapsed on the host +sim_insts 132071192 # Number of instructions simulated +sim_ops 221363384 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory +system.physmem.bytes_read::total 361984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 231488 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5656 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2240405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1262977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3503382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2240405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2240405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2240405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1262977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3503382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5656 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5656 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 361984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 361984 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 310 # Per bank write bursts +system.physmem.perBankRdBursts::1 382 # Per bank write bursts +system.physmem.perBankRdBursts::2 476 # Per bank write bursts +system.physmem.perBankRdBursts::3 358 # Per bank write bursts +system.physmem.perBankRdBursts::4 362 # Per bank write bursts +system.physmem.perBankRdBursts::5 335 # Per bank write bursts +system.physmem.perBankRdBursts::6 419 # Per bank write bursts +system.physmem.perBankRdBursts::7 385 # Per bank write bursts +system.physmem.perBankRdBursts::8 389 # Per bank write bursts +system.physmem.perBankRdBursts::9 295 # Per bank write bursts +system.physmem.perBankRdBursts::10 260 # Per bank write bursts +system.physmem.perBankRdBursts::11 270 # Per bank write bursts +system.physmem.perBankRdBursts::12 228 # Per bank write bursts +system.physmem.perBankRdBursts::13 484 # Per bank write bursts +system.physmem.perBankRdBursts::14 420 # Per bank write bursts +system.physmem.perBankRdBursts::15 283 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 103323899000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5656 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 286.278481 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.439317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.670037 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 554 43.83% 43.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 264 20.89% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 105 8.31% 73.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 69 5.46% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 45 3.56% 82.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 4.51% 86.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 28 2.22% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 1.34% 90.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 125 9.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1264 # Bytes accessed per row activation +system.physmem.totQLat 43672750 # Total ticks spent queuing +system.physmem.totMemAccLat 149722750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7721.49 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26471.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4391 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 18268016.09 # Average gap between requests +system.physmem.pageHitRate 77.63 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5624640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3069000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 23610600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3147948405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 59232949500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 69161793345 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.369133 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 98535205500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3450200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1338454000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3931200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2145000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20490600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2964574845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 59393774250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 69133507095 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.095685 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 98803806250 # Time in different power states +system.physmem_1.memoryStateTime::REF 3450200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 40908032 # Number of BP lookups +system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 35316490 # Number of BTB lookups +system.cpu.branchPred.BTBHits 0 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3206071 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 604531 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 35316490 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9869044 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 206648308 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 46351281 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 420030465 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40908032 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13075115 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 152558958 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14935189 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 126 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 68758 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 764 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41261989 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1525874 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 206453541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.416062 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.660543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 99211398 48.06% 48.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5135847 2.49% 50.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5374620 2.60% 53.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5328555 2.58% 55.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6013612 2.91% 58.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5856529 2.84% 61.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5733209 2.78% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4747222 2.30% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 69052549 33.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 206453541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.197960 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.032586 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32305475 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86547165 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 62440790 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17692517 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7467594 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 591140753 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7467594 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42099614 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46622929 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29580 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68917298 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41316526 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 552365156 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1615 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36415427 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4818042 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 146051 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 629691896 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1486514399 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 974943820 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 15152274 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 370262446 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2381 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2386 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89347483 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128815998 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45923960 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 77358410 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25275137 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 490566423 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 62065 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 338414549 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1099553 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 269265104 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 527048763 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 60820 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 206453541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.639180 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.804126 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 73345677 35.53% 35.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46646037 22.59% 58.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32854801 15.91% 74.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20905072 10.13% 84.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15063521 7.30% 91.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8409386 4.07% 95.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5213188 2.53% 98.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2363320 1.14% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1652539 0.80% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 206453541 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 758238 19.31% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2733075 69.60% 88.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 435620 11.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 1211810 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 216608884 64.01% 64.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 799973 0.24% 64.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7048329 2.08% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1813849 0.54% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 84312637 24.91% 92.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26619067 7.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 338414549 # Type of FU issued +system.cpu.iq.rate 1.637635 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3926933 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011604 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 880106724 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 745207821 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 316030450 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8202401 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15512263 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3567674 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 337013730 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4115942 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18154732 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 72166411 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54986 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 863760 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25408243 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 50543 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 7467594 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35770303 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 592137 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 490628488 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1259959 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128815998 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45923960 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22654 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 545800 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38626 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 863760 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1294864 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6880130 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8174994 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 326485130 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80685795 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11929419 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 106318426 # number of memory reference insts executed +system.cpu.iew.exec_branches 18939296 # Number of branches executed +system.cpu.iew.exec_stores 25632631 # Number of stores executed +system.cpu.iew.exec_rate 1.579907 # Inst execution rate +system.cpu.iew.wb_sent 322610085 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 319598124 # cumulative count of insts written-back +system.cpu.iew.wb_producers 256503247 # num instructions producing a value +system.cpu.iew.wb_consumers 435667509 # num instructions consuming a value +system.cpu.iew.wb_rate 1.546580 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588759 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 269290512 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6746174 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163890954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.350675 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.933271 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67206524 41.01% 41.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54940140 33.52% 74.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13261155 8.09% 82.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10687834 6.52% 89.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5446779 3.32% 92.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3132108 1.91% 94.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1092307 0.67% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1156922 0.71% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6967185 4.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163890954 # Number of insts commited each cycle +system.cpu.commit.committedInsts 132071192 # Number of instructions committed +system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 77165304 # Number of memory references committed +system.cpu.commit.loads 56649587 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 12326938 # Number of branches committed +system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. +system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. +system.cpu.commit.function_calls 797818 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction +system.cpu.commit.bw_lim_events 6967185 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 647577665 # The number of ROB reads +system.cpu.rob.rob_writes 1024269930 # The number of ROB writes +system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 194767 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 132071192 # Number of Instructions Simulated +system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.564674 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.564674 # CPI: Total CPI of All Threads +system.cpu.ipc 0.639111 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.639111 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 524516370 # number of integer regfile reads +system.cpu.int_regfile_writes 289029189 # number of integer regfile writes +system.cpu.fp_regfile_reads 4536413 # number of floating regfile reads +system.cpu.fp_regfile_writes 3331836 # number of floating regfile writes +system.cpu.cc_regfile_reads 107017358 # number of cc regfile reads +system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes +system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads +system.cpu.misc_regfile_writes 1689 # number of misc regfile writes +system.cpu.dcache.tags.replacements 72 # number of replacements +system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2113 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39170.050166 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1525.498489 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.372436 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.372436 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2041 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 409 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513707 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82765643 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82765643 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82765643 # number of overall hits +system.cpu.dcache.overall_hits::total 82765643 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1262 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1262 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2024 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2024 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3286 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3286 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3286 # number of overall misses +system.cpu.dcache.overall_misses::total 3286 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84231000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84231000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 131983500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 131983500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 216214500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 216214500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 216214500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 216214500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 62253198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 62253198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 82768929 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82768929 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82768929 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82768929 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000099 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000099 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66744.057052 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66744.057052 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65209.239130 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65209.239130 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65798.691418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65798.691418 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 369 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 18 # number of writebacks +system.cpu.dcache.writebacks::total 18 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 661 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 7 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 7 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2017 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2017 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2618 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2618 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2618 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2618 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47710000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47710000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129636500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 129636500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177346500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 177346500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177346500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 177346500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency +system.cpu.icache.tags.replacements 6515 # number of replacements +system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.812154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1984 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 845 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 736 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses +system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41248897 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 41248897 # number of overall hits +system.cpu.icache.overall_hits::total 41248897 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13089 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13089 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13089 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13089 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13089 # number of overall misses +system.cpu.icache.overall_misses::total 13089 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 485791000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 485791000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 485791000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 485791000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 485791000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 485791000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 41261986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41261986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 41261986 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41261986 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 41261986 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41261986 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000317 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000317 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000317 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000317 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000317 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000317 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37114.447246 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37114.447246 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37114.447246 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37114.447246 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2090 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 305 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 6515 # number of writebacks +system.cpu.icache.writebacks::total 6515 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4088 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4088 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4088 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4088 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4088 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4088 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9001 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9001 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9001 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9001 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9001 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9001 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340708000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 340708000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340708000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 340708000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340708000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 340708000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000218 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000218 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 389.769746 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073306 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011895 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.085353 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 992 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6469 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4877 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 4877 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 68 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 68 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 4877 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 74 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 4951 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4877 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 74 # number of overall hits +system.cpu.l2cache.overall_hits::total 4951 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 500 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 500 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1507 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1507 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3617 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3617 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 532 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 532 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3617 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2039 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5656 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3617 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2039 # number of overall misses +system.cpu.l2cache.overall_misses::total 5656 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 112056000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 112056000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 275028000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 275028000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 45953000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 45953000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 275028000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 158009000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 433037000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 275028000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 158009000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 433037000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 18 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 18 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6469 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6469 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 505 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 505 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1513 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1513 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8494 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 8494 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 600 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 600 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8494 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2113 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 10607 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8494 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2113 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 10607 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990099 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990099 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996034 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.996034 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.425830 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.425830 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886667 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886667 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.425830 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964979 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.533233 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.425830 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964979 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.533233 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74357.000664 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74357.000664 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76037.600221 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76037.600221 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86377.819549 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86377.819549 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76037.600221 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76562.411598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76037.600221 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76562.411598 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 500 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 500 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3617 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3617 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3617 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2039 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5656 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3617 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2039 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5656 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 9503500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 9503500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 96986000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 96986000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 238858000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 238858000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40633000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40633000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238858000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137619000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 376477000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238858000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137619000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 376477000 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990099 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990099 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996034 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996034 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.425830 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.886667 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.886667 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.533233 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.533233 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19007 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19007 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64357.000664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64357.000664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66037.600221 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66037.600221 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 54 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 505 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 505 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 9001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 600 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24009 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29317 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1096896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 507 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11619 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.094328 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.292297 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10523 90.57% 90.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1096 9.43% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 11619 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15636499 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 13500000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 4149 # Transaction distribution +system.membus.trans_dist::UpgradeReq 500 # Transaction distribution +system.membus.trans_dist::ReadExReq 1507 # Transaction distribution +system.membus.trans_dist::ReadExResp 1507 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4149 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11812 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 361984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 361984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 361984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6156 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6156 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6156 # Request fanout histogram +system.membus.reqLayer0.occupancy 7649501 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 30011250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |