diff options
Diffstat (limited to 'tests/long/se/70.twolf')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 684 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 1591 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt | 1496 |
3 files changed, 1894 insertions, 1877 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index f4cf26547..aa0694fe0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132539 # Number of seconds simulated -sim_ticks 132538562500 # Number of ticks simulated -final_tick 132538562500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132570 # Number of seconds simulated +sim_ticks 132570000500 # Number of ticks simulated +final_tick 132570000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 360845 # Simulator instruction rate (inst/s) -host_op_rate 380389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 277544932 # Simulator tick rate (ticks/s) -host_mem_usage 274852 # Number of bytes of host memory used -host_seconds 477.54 # Real time elapsed on the host +host_inst_rate 373440 # Simulator instruction rate (inst/s) +host_op_rate 393666 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 287300012 # Simulator tick rate (ticks/s) +host_mem_usage 274936 # Number of bytes of host memory used +host_seconds 461.43 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247552 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 824756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1867773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 824756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1867773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1042770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 824561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1867330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1042770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1042770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1042770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 824561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1867330 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3868 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 132538461500 # Total gap between requests +system.physmem.totGap 132569899500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 239 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 928 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 265.103448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.439776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 277.287318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 274 29.53% 29.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 366 39.44% 68.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 89 9.59% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.14% 84.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24 2.59% 87.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 19 2.05% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 1.94% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.94% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 63 6.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.513478 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.064139 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 273 29.42% 29.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 364 39.22% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95 10.24% 78.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 53 5.71% 84.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24 2.59% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 21 2.26% 89.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.94% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.94% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 62 6.68% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 928 # Bytes accessed per row activation -system.physmem.totQLat 84421250 # Total ticks spent queuing -system.physmem.totMemAccLat 156946250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 82551750 # Total ticks spent queuing +system.physmem.totMemAccLat 155076750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 21825.56 # Average queueing delay per DRAM burst +system.physmem.avgQLat 21342.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40575.56 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 40092.23 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s @@ -221,62 +221,62 @@ system.physmem.readRowHits 2935 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34265372.67 # Average gap between requests +system.physmem.avgGap 34273500.39 # Average gap between requests system.physmem.pageHitRate 75.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2977380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1582515 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 2963100 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1574925 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 14822640 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 159806400.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 56564520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6779040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 507399750 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 193240800 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 31407910590 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 32351114145 # Total energy per rank (pJ) -system.physmem_0.averagePower 244.088313 # Core power per rank (mW) -system.physmem_0.totalIdleTime 132395468250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 11004000 # Time in different power states -system.physmem_0.memoryStateTime::REF 67828000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 130780838250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 503202000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 62983500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1112706750 # Time in different power states -system.physmem_1.actEnergy 3684240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1939245 # Energy for precharge commands per rank (pJ) +system.physmem_0.refreshEnergy 157347840.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56147850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6612480 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 497768460 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 192585120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 31420705950 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 32350562865 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.026270 # Core power per rank (mW) +system.physmem_0.totalIdleTime 132428576750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 10716000 # Time in different power states +system.physmem_0.memoryStateTime::REF 66782000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 130836450000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 501553500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 62926000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1091573000 # Time in different power states +system.physmem_1.actEnergy 3698520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1946835 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 12794880 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 142596480.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 50045430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 5323200 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 514216380 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 148467840 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 31429438665 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 32308536150 # Total energy per rank (pJ) -system.physmem_1.averagePower 243.767063 # Core power per rank (mW) -system.physmem_1.totalIdleTime 132414854750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 7934000 # Time in different power states -system.physmem_1.memoryStateTime::REF 60464000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 130900584250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 386668500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 55249000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1127662750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 49693791 # Number of BP lookups -system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups -system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits +system.physmem_1.refreshEnergy 143211120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 50027190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 5428800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 512852940 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 149734560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 31437405705 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 32317131480 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.774090 # Core power per rank (mW) +system.physmem_1.totalIdleTime 132446049750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8198000 # Time in different power states +system.physmem_1.memoryStateTime::REF 60730000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 130931475750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 389968500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 54962000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1124666250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 49693872 # Number of BP lookups +system.cpu.branchPred.condPredicted 39498414 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5520434 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24194736 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22923274 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.744882 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1894785 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 213909 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 208025 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5884 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40447 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 265077125 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 265140001 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11517797 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.538304 # CPI: cycles per instruction -system.cpu.ipc 0.650067 # IPC: instructions per cycle +system.cpu.cpi 1.538669 # CPI: cycles per instruction +system.cpu.ipc 0.649913 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction @@ -446,18 +446,18 @@ system.cpu.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction -system.cpu.tickCycles 256741537 # Number of cycles that the object actually ticked -system.cpu.idleCycles 8335588 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 256807085 # Number of cycles that the object actually ticked +system.cpu.idleCycles 8332916 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1378.587934 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40755397 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.592517 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40754461 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22504.360574 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22503.843733 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1378.587934 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336569 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336569 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.592517 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336570 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336570 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id @@ -465,73 +465,73 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362633 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362633 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 81515543 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81515543 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28346550 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28346550 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362634 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362634 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 463 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 463 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40710121 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40710121 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40710583 # number of overall hits -system.cpu.dcache.overall_hits::total 40710583 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40709184 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40709184 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40709647 # number of overall hits +system.cpu.dcache.overall_hits::total 40709647 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1654 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1654 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1653 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1653 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2405 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2405 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2406 # number of overall misses -system.cpu.dcache.overall_misses::total 2406 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64864500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64864500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 147460000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 147460000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 212324500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 212324500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 212324500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 212324500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2404 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2404 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2405 # number of overall misses +system.cpu.dcache.overall_misses::total 2405 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64086500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64086500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 146233500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 146233500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 210320000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 210320000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 210320000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 210320000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28347301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28347301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 464 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 464 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40711588 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40711588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712052 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712052 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000134 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002155 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002155 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86370.838881 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 86370.838881 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89153.567110 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89153.567110 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 88284.615385 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 88284.615385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 88247.921862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 88247.921862 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 85334.886818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 85334.886818 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88465.517241 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 88465.517241 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 87487.520799 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 87487.520799 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 87451.143451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 87451.143451 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -542,12 +542,12 @@ system.cpu.dcache.writebacks::writebacks 16 # nu system.cpu.dcache.writebacks::total 16 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 555 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 555 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 595 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 595 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 595 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 595 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 554 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 554 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 594 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 594 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses @@ -558,162 +558,162 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61185500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 61185500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 100181500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 100181500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 60392000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 60392000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 99618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 99618500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 77000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 77000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161444000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161444000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 160010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160087500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 160087500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002155 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002155 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86055.555556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86055.555556 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91156.960874 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91156.960874 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84939.521800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84939.521800 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 90644.676979 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 90644.676979 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 77000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 77000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89153.038674 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 89153.038674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89146.327996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 89146.327996 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2864 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.889067 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 70941363 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15213.674244 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88403.591160 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 88403.591160 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88397.294313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 88397.294313 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2861 # number of replacements +system.cpu.icache.tags.tagsinuse 1424.892665 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 70991309 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4660 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15234.186481 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.889067 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695747 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695747 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.892665 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695748 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695748 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 491 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 131 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 141896717 # Number of tag accesses -system.cpu.icache.tags.data_accesses 141896717 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 70941363 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 70941363 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 70941363 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 70941363 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 70941363 # number of overall hits -system.cpu.icache.overall_hits::total 70941363 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4664 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4664 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4664 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses -system.cpu.icache.overall_misses::total 4664 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 236552500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 236552500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 236552500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 236552500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 236552500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 236552500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 70946027 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 70946027 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 70946027 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 70946027 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 70946027 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 70946027 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 141996600 # Number of tag accesses +system.cpu.icache.tags.data_accesses 141996600 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 70991309 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 70991309 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 70991309 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 70991309 # 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miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.600278 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463849 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90236.021998 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90236.021998 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91692.645698 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91692.645698 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93781.645570 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93781.645570 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 91623.423423 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 91623.423423 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.600278 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89719.981668 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89719.981668 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91456.290472 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91456.290472 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92526.107595 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92526.107595 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 91142.728443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 91142.728443 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,79 +806,79 @@ system.cpu.l2cache.demand_mshr_misses::total 3869 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87537500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87537500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 51432500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 51432500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176566000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138970000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 315536000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176566000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138970000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 315536000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86974500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86974500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176055000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176055000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 50639500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 50639500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176055000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137614000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 313669000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176055000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137614000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 313669000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463336 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463634 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.597806 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80236.021998 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80236.021998 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81705.691809 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81705.691809 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83358.995138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83358.995138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.597806 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79719.981668 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79719.981668 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81469.227210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81469.227210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82073.743922 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82073.743922 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9375 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3038 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5372 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2861 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4664 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4661 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12191 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12182 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 15855 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15846 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481344 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 598656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 598272 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6475 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.072896 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.259985 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6472 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.072775 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.259787 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6003 92.71% 92.71% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 472 7.29% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6001 92.72% 92.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 471 7.28% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6475 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7570500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6472 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7564500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6994999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6990499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) @@ -888,7 +888,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2777 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution @@ -909,9 +909,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3868 # Request fanout histogram -system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4525000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20568250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20564500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 5040af9e4..8786b6479 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.086149 # Number of seconds simulated -sim_ticks 86149358000 # Number of ticks simulated -final_tick 86149358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085986 # Number of seconds simulated +sim_ticks 85986203000 # Number of ticks simulated +final_tick 85986203000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240669 # Simulator instruction rate (inst/s) -host_op_rate 253706 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120331720 # Simulator tick rate (ticks/s) -host_mem_usage 272336 # Number of bytes of host memory used -host_seconds 715.93 # Real time elapsed on the host +host_inst_rate 210936 # Simulator instruction rate (inst/s) +host_op_rate 222361 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 105265513 # Simulator tick rate (ticks/s) +host_mem_usage 272504 # Number of bytes of host memory used +host_seconds 816.85 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 652096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 192896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71744 # Number of bytes read from this memory -system.physmem.bytes_read::total 916736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 652096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 652096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 10189 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3014 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14324 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 7569366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2239088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 832786 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10641240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7569366 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7569366 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7569366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2239088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 832786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10641240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 14324 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 651776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 193408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71680 # Number of bytes read from this memory +system.physmem.bytes_read::total 916864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 651776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 651776 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3022 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14326 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7580007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2249291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 833622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10662920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7580007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7580007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7580007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2249291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 833622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10662920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14327 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 14324 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14327 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 916736 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 916928 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 916736 # Total read bytes from the system interface side +system.physmem.bytesReadSys 916928 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1375 # Per bank write bursts -system.physmem.perBankRdBursts::1 498 # Per bank write bursts -system.physmem.perBankRdBursts::2 5101 # Per bank write bursts -system.physmem.perBankRdBursts::3 808 # Per bank write bursts -system.physmem.perBankRdBursts::4 2279 # Per bank write bursts -system.physmem.perBankRdBursts::5 424 # Per bank write bursts -system.physmem.perBankRdBursts::6 384 # Per bank write bursts -system.physmem.perBankRdBursts::7 628 # Per bank write bursts +system.physmem.perBankRdBursts::0 1379 # Per bank write bursts +system.physmem.perBankRdBursts::1 501 # Per bank write bursts +system.physmem.perBankRdBursts::2 5100 # Per bank write bursts +system.physmem.perBankRdBursts::3 815 # Per bank write bursts +system.physmem.perBankRdBursts::4 2265 # Per bank write bursts +system.physmem.perBankRdBursts::5 427 # Per bank write bursts +system.physmem.perBankRdBursts::6 394 # Per bank write bursts +system.physmem.perBankRdBursts::7 623 # Per bank write bursts system.physmem.perBankRdBursts::8 270 # Per bank write bursts -system.physmem.perBankRdBursts::9 231 # Per bank write bursts +system.physmem.perBankRdBursts::9 230 # Per bank write bursts system.physmem.perBankRdBursts::10 354 # Per bank write bursts -system.physmem.perBankRdBursts::11 348 # Per bank write bursts -system.physmem.perBankRdBursts::12 320 # Per bank write bursts -system.physmem.perBankRdBursts::13 267 # Per bank write bursts -system.physmem.perBankRdBursts::14 240 # Per bank write bursts -system.physmem.perBankRdBursts::15 797 # Per bank write bursts +system.physmem.perBankRdBursts::11 345 # Per bank write bursts +system.physmem.perBankRdBursts::12 321 # Per bank write bursts +system.physmem.perBankRdBursts::13 266 # Per bank write bursts +system.physmem.perBankRdBursts::14 239 # Per bank write bursts +system.physmem.perBankRdBursts::15 798 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 86149299500 # Total gap between requests +system.physmem.totGap 85986194000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 14324 # Read request sizes (log2) +system.physmem.readPktSize::6 14327 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,15 +95,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see @@ -191,29 +191,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.956168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 86.535791 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 122.736079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5894 69.45% 69.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 2098 24.72% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 256 3.02% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 0.74% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 36 0.42% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 32 0.38% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 19 0.22% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 8483 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.969350 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.508882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 122.734500 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5897 69.52% 69.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2092 24.66% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 251 2.96% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 0.77% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 0.45% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 0.42% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 15 0.18% 98.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 10 0.12% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 79 0.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8487 # Bytes accessed per row activation -system.physmem.totQLat 1500750524 # Total ticks spent queuing -system.physmem.totMemAccLat 1769325524 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 71620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 104771.75 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::total 8483 # Bytes accessed per row activation +system.physmem.totQLat 1497477800 # Total ticks spent queuing +system.physmem.totMemAccLat 1766109050 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 104521.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 123521.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 10.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 123271.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 10.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 10.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 10.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.08 # Data bus utilization in percentage @@ -221,66 +221,66 @@ system.physmem.busUtilRead 0.08 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5833 # Number of row buffer hits during reads +system.physmem.readRowHits 5838 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.72 # Row buffer hit rate for reads +system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6014332.55 # Average gap between requests -system.physmem.pageHitRate 40.72 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 51543660 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 27384720 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 82088580 # Energy for read commands per rank (pJ) +system.physmem.avgGap 6001688.70 # Average gap between requests +system.physmem.pageHitRate 40.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 51557940 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 27392310 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 82138560 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5186946960.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1121176890 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 276161760 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12273342600 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8346662400 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 9294814230 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 36662152740 # Total energy per rank (pJ) -system.physmem_0.averagePower 425.565010 # Core power per rank (mW) -system.physmem_0.totalIdleTime 82965211526 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 532687000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2205840000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34315599752 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21736059604 # Time in different power states -system.physmem_0.memoryStateTime::ACT 443979474 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 26915192170 # Time in different power states -system.physmem_1.actEnergy 9082080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4823445 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20184780 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 5188176240.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1121049780 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 275286240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12230933460 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8389841280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9251896980 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 36621408690 # Total energy per rank (pJ) +system.physmem_0.averagePower 425.898657 # Core power per rank (mW) +system.physmem_0.totalIdleTime 82802255264 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 532741000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2206324000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34133171250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21848572364 # Time in different power states +system.physmem_0.memoryStateTime::ACT 443169236 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 26822225150 # Time in different power states +system.physmem_1.actEnergy 9046380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4800675 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20149080 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 883852320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 198703710 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 50905920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1989700140 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1383894720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18830063895 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23371485780 # Total energy per rank (pJ) -system.physmem_1.averagePower 271.290305 # Core power per rank (mW) -system.physmem_1.totalIdleTime 85580460271 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 101384000 # Time in different power states -system.physmem_1.memoryStateTime::REF 376118000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 77613150500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3603890386 # Time in different power states -system.physmem_1.memoryStateTime::ACT 91368979 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 4363446135 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85639426 # Number of BP lookups -system.cpu.branchPred.condPredicted 68185953 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5937258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39949340 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38185565 # Number of BTB hits +system.physmem_1.refreshEnergy 880164480.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 198118890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 50592480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1982659500 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1381296480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18795083175 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23322152130 # Total energy per rank (pJ) +system.physmem_1.averagePower 271.231327 # Core power per rank (mW) +system.physmem_1.totalIdleTime 85419499755 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 100592000 # Time in different power states +system.physmem_1.memoryStateTime::REF 374546000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 77474388250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3597111150 # Time in different power states +system.physmem_1.memoryStateTime::ACT 91565245 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 4348000355 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85644201 # Number of BP lookups +system.cpu.branchPred.condPredicted 68263451 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5948841 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39900262 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38156956 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.584971 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3683095 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81909 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681696 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 653573 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 28123 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40352 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.630841 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3658994 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81907 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 654149 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 629298 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 24851 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40566 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,242 +401,242 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 172298717 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 171972407 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5689617 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347266831 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85639426 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42522233 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158380748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11888463 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5684699 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 346733793 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85644201 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42445248 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158074641 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11911485 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4331 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 80 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 4281 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78346664 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18062 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 170023102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.137102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.057569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 4750 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78152122 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17905 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169724243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.137034 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.057596 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18318468 10.77% 10.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30068726 17.69% 28.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31619725 18.60% 47.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90016183 52.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18311667 10.79% 10.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29948653 17.65% 28.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31633861 18.64% 47.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89830062 52.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 170023102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.497040 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.015493 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17554244 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18101467 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121824905 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6773054 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5769432 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11065775 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189948 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 305038109 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27237354 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5769432 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37539679 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8956907 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 601126 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108322423 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8833535 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277447852 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13184486 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3097243 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842563 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2612762 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 40533 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26849 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481448776 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187920227 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296497585 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005089 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169724243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498011 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.016218 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17545924 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18077628 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121579812 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6764631 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5756248 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 32661376 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 214759 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304427843 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27289068 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5756248 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37507593 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8946109 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 602389 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108088153 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8823751 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 276998119 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13097154 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3089202 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 850461 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2596711 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 40764 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26854 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 480912034 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1185877305 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296009785 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3004340 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188471847 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23626 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13449474 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33921609 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14424624 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2552614 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1816807 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263824183 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45978 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214443460 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5190288 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82234207 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216932052 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 170023102 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.261261 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.018489 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 187935105 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23572 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23567 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13428642 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33801265 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14384966 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2539582 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1819756 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263460878 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45929 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214221426 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5142742 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 81870853 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 215931448 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 713 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169724243 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.262173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.018049 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 53215331 31.30% 31.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36043504 21.20% 52.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65536118 38.55% 91.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13631246 8.02% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1550810 0.91% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 45816 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 277 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 53012533 31.23% 31.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36041444 21.24% 52.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65469642 38.57% 91.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13608265 8.02% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1546158 0.91% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 45935 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 266 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 170023102 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169724243 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35671391 66.13% 66.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153271 0.28% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35712 0.07% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 556 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 40135 0.07% 66.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 13909773 25.79% 92.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3850022 7.14% 99.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 142020 0.26% 99.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 136319 0.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35637562 66.14% 66.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153239 0.28% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35742 0.07% 66.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 559 0.00% 66.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 40182 0.07% 66.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 13886588 25.77% 92.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3846845 7.14% 99.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 141772 0.26% 99.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 136229 0.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167011334 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919426 0.43% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460349 0.21% 78.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206623 0.10% 78.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31296412 14.59% 93.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13233182 6.17% 99.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 576648 0.27% 99.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 147624 0.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166877725 77.90% 77.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919560 0.43% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165187 0.08% 78.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245719 0.11% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460300 0.21% 78.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206641 0.10% 78.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31220842 14.57% 93.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13220710 6.17% 99.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 576371 0.27% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 147395 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214443460 # Type of FU issued -system.cpu.iq.rate 1.244603 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53940732 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251538 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654047721 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344100630 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204290427 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3993321 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2010682 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806323 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266209914 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2174278 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1590245 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214221426 # Type of FU issued +system.cpu.iq.rate 1.245673 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53880251 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251517 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653198075 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 343375917 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204156399 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3992013 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2008700 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806249 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 265928183 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2173494 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1586831 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6025465 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7430 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7094 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1779990 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5905121 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6947 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7000 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1740332 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25605 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25012 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 810 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5769432 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5627104 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 174387 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263890272 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5756248 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5611049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 173372 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263527171 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33921609 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14424624 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23570 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3854 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 167353 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7094 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3148097 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247402 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6395499 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207161825 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30639651 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7281635 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33801265 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14384966 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23521 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3789 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 166382 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7000 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3130012 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3255540 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6385552 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 206995589 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30591856 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7225837 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20111 # number of nop insts executed -system.cpu.iew.exec_refs 43786600 # number of memory reference insts executed -system.cpu.iew.exec_branches 44861358 # Number of branches executed -system.cpu.iew.exec_stores 13146949 # Number of stores executed -system.cpu.iew.exec_rate 1.202341 # Inst execution rate -system.cpu.iew.wb_sent 206406222 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206096750 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129381204 # num instructions producing a value -system.cpu.iew.wb_consumers 221650091 # num instructions consuming a value -system.cpu.iew.wb_rate 1.196160 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583718 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68697467 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20364 # number of nop insts executed +system.cpu.iew.exec_refs 43730352 # number of memory reference insts executed +system.cpu.iew.exec_branches 44853428 # Number of branches executed +system.cpu.iew.exec_stores 13138496 # Number of stores executed +system.cpu.iew.exec_rate 1.203656 # Inst execution rate +system.cpu.iew.wb_sent 206269583 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 205962648 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129302452 # num instructions producing a value +system.cpu.iew.wb_consumers 221536410 # num instructions consuming a value +system.cpu.iew.wb_rate 1.197649 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583662 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68402964 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5762459 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158721175 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.144462 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.650716 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5749347 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158452610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.651768 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 74120611 46.70% 46.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41150811 25.93% 72.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22560961 14.21% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9504738 5.99% 92.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3552513 2.24% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2129219 1.34% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1299436 0.82% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1012456 0.64% 97.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3390430 2.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73893836 46.63% 46.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41104048 25.94% 72.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22555911 14.24% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9496527 5.99% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3557786 2.25% 95.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2129951 1.34% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1320929 0.83% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1010558 0.64% 97.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3383064 2.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158721175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158452610 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,383 +686,389 @@ system.cpu.commit.op_class_0::FloatMemWrite 146246 0.08% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3390430 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 405673353 # The number of ROB reads -system.cpu.rob.rob_writes 512011515 # The number of ROB writes -system.cpu.timesIdled 9971 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2275615 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3383064 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 405117651 # The number of ROB reads +system.cpu.rob.rob_writes 511394543 # The number of ROB writes +system.cpu.timesIdled 9924 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2248164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.999975 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.999975 # CPI: Total CPI of All Threads -system.cpu.ipc 1.000025 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.000025 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218762027 # number of integer regfile reads -system.cpu.int_regfile_writes 114194444 # number of integer regfile writes -system.cpu.fp_regfile_reads 2903946 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441681 # number of floating regfile writes -system.cpu.cc_regfile_reads 708323214 # number of cc regfile reads -system.cpu.cc_regfile_writes 229513810 # number of cc regfile writes -system.cpu.misc_regfile_reads 57456345 # number of misc regfile reads +system.cpu.cpi 0.998081 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.998081 # CPI: Total CPI of All Threads +system.cpu.ipc 1.001922 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.001922 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218599432 # number of integer regfile reads +system.cpu.int_regfile_writes 114087616 # number of integer regfile writes +system.cpu.fp_regfile_reads 2903991 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441715 # number of floating regfile writes +system.cpu.cc_regfile_reads 707769294 # number of cc regfile reads +system.cpu.cc_regfile_writes 229397390 # number of cc regfile writes +system.cpu.misc_regfile_reads 57427586 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72586 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.401008 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41045518 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73098 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.513557 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 555248500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.401008 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998830 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998830 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72391 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.400200 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40997604 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 72903 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 562.358257 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 554902500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.400200 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998829 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998829 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82389396 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82389396 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28659277 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28659277 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341322 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341322 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 365 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 365 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 82292817 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82292817 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28611296 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28611296 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341384 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341384 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 362 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 362 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22154 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22154 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41000599 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41000599 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41000964 # number of overall hits -system.cpu.dcache.overall_hits::total 41000964 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89290 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89290 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22965 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22965 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112255 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112255 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112371 # number of overall misses -system.cpu.dcache.overall_misses::total 112371 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1989594500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1989594500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 244666499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 244666499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 2234260999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 2234260999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 2234260999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 2234260999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28748567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28748567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40952680 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40952680 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40953042 # number of overall hits +system.cpu.dcache.overall_hits::total 40953042 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89081 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89081 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22903 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22903 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 111984 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 111984 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112101 # number of overall misses +system.cpu.dcache.overall_misses::total 112101 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1981259500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1981259500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 246570499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 246570499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2257000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2257000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2227829999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2227829999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 2227829999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2227829999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28700377 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28700377 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 481 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 481 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41112854 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41112854 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41113335 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41113335 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003106 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003106 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241164 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.241164 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22282.388845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22282.388845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10653.886305 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10653.886305 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19903.443045 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19903.443045 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19882.896824 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19882.896824 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 41064664 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41064664 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41065143 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41065143 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001852 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001852 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244259 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.244259 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011291 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011291 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002727 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002727 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002730 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002730 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22241.100796 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22241.100796 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10765.860324 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10765.860324 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8920.948617 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8920.948617 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19894.181303 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19894.181303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19873.417713 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19873.417713 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11152 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11209 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.907407 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72586 # number of writebacks -system.cpu.dcache.writebacks::total 72586 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24872 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24872 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14398 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14398 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39270 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39270 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39270 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39270 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64418 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64418 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8567 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8567 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 72985 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 72985 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73098 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73098 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1060539500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1060539500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87795999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 87795999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 969000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 969000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1148335499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1148335499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1149304499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1149304499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002241 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002241 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.234927 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.234927 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001775 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16463.403086 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16463.403086 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10248.161433 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10248.161433 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8575.221239 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8575.221239 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15733.856258 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15733.856258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15722.789940 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15722.789940 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 53582 # number of replacements -system.cpu.icache.tags.tagsinuse 510.578561 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78288973 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54094 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1447.276463 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 85378568500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.578561 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997224 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997224 # Average percentage of cache occupancy +system.cpu.dcache.avg_blocked_cycles::no_targets 12.958382 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72391 # number of writebacks +system.cpu.dcache.writebacks::total 72391 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24849 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24849 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14345 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14345 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 253 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 253 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39194 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39194 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64232 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8558 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8558 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 72790 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72790 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 72904 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 72904 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1056234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1056234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88380499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 88380499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 977000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 977000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1144614499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1144614499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1145591499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1145591499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002238 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.237996 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.237996 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001773 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001773 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001775 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16444.046581 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16444.046581 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10327.237556 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10327.237556 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8570.175439 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8570.175439 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15724.886647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15724.886647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15713.698823 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15713.698823 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 53106 # number of replacements +system.cpu.icache.tags.tagsinuse 510.578015 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78094905 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 53618 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1456.505371 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 85215430500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.578015 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997223 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997223 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156747350 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156747350 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78288973 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78288973 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78288973 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78288973 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78288973 # number of overall hits -system.cpu.icache.overall_hits::total 78288973 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57655 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57655 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57655 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57655 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57655 # number of overall misses -system.cpu.icache.overall_misses::total 57655 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2247853926 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2247853926 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2247853926 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2247853926 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2247853926 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2247853926 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78346628 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78346628 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78346628 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78346628 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78346628 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78346628 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000736 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000736 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000736 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000736 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000736 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000736 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38988.013633 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38988.013633 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38988.013633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38988.013633 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 94468 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 55 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3203 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.493600 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 53582 # number of writebacks -system.cpu.icache.writebacks::total 53582 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3560 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3560 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3560 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3560 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3560 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3560 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54095 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54095 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54095 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54095 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54095 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54095 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2052751452 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2052751452 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2052751452 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2052751452 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2052751452 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2052751452 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000690 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000690 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000690 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37947.156891 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37947.156891 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 9257 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9257 # number of prefetch candidates identified +system.cpu.icache.tags.tag_accesses 156357779 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156357779 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 78094905 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78094905 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78094905 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78094905 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78094905 # number of overall hits +system.cpu.icache.overall_hits::total 78094905 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57175 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57175 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57175 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57175 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57175 # number of overall misses +system.cpu.icache.overall_misses::total 57175 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2239186435 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2239186435 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2239186435 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2239186435 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2239186435 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2239186435 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78152080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78152080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78152080 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78152080 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78152080 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78152080 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000732 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000732 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000732 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000732 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000732 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000732 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39163.733013 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39163.733013 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39163.733013 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39163.733013 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 91615 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 88 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.176752 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 53106 # number of writebacks +system.cpu.icache.writebacks::total 53106 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3554 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3554 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3554 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3554 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3554 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3554 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 53621 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 53621 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 53621 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 53621 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 53621 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 53621 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2047106952 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2047106952 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2047106952 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2047106952 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2047106952 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2047106952 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38177.336342 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38177.336342 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38177.336342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38177.336342 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 9132 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9132 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1327 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 1308 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1809.107747 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 98955 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2836 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 34.892454 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1811.625085 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 98153 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2844 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 34.512307 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1727.095683 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 82.012064 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.105414 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005006 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.110419 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 131 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2705 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 1727.578627 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 84.046457 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.105443 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005130 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.110573 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 138 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 77 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 198 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 958 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007996 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165100 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4002973 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4002973 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 64701 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 64701 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 50991 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 50991 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8404 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8404 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43901 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 43901 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61671 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 61671 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 43901 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 70075 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 113976 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 43901 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 70075 # number of overall hits -system.cpu.l2cache.overall_hits::total 113976 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 230 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 230 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10194 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 10194 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2793 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2793 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10194 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3023 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 13217 # 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mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103803 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027243 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027243 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.189948 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041452 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.104384 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041452 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.119904 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47911.933105 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81969.432314 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81969.432314 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161810.236530 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161810.236530 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 193500.179533 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 193500.179533 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167110.012876 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151103.346600 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253361 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126188 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10476 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 927 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.120081 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 49936.888721 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82548.936170 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82548.936170 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161668.384880 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161668.384880 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192378.184428 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192378.184428 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161668.384880 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 183837.524818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166741.084273 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161668.384880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 183837.524818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151472.662476 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 252022 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 125518 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 866 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 865 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64701 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54095 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64464 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161771 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380553 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6891264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16215040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2398 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 129591 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.088154 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283547 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 117896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 60939 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 53621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64277 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160345 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 378544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6830336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9298816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16129152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2338 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 128862 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.088172 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283573 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118168 91.19% 91.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11422 8.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 117501 91.18% 91.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11360 8.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 129591 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 252848500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 128862 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 251508000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81149483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 80437981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109651491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109359491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 14324 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 10483 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 14328 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10478 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 14094 # Transaction distribution -system.membus.trans_dist::ReadExReq 229 # Transaction distribution -system.membus.trans_dist::ReadExResp 229 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 14095 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28647 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 916672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14090 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 235 # Transaction distribution +system.membus.trans_dist::ReadExResp 235 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28653 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 916800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 14324 # Request fanout histogram +system.membus.snoop_fanout::samples 14328 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 14324 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14328 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 14324 # Request fanout histogram -system.membus.reqLayer0.occupancy 18004660 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14328 # Request fanout histogram +system.membus.reqLayer0.occupancy 18011178 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 77243027 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77254535 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 4554501a1..059c65964 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103324 # Number of seconds simulated -sim_ticks 103323995500 # Number of ticks simulated -final_tick 103323995500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.102721 # Number of seconds simulated +sim_ticks 102721386000 # Number of ticks simulated +final_tick 102721386000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113414 # Simulator instruction rate (inst/s) -host_op_rate 190092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88727502 # Simulator tick rate (ticks/s) -host_mem_usage 308112 # Number of bytes of host memory used -host_seconds 1164.51 # Real time elapsed on the host +host_inst_rate 115023 # Simulator instruction rate (inst/s) +host_op_rate 192789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89461870 # Simulator tick rate (ticks/s) +host_mem_usage 308536 # Number of bytes of host memory used +host_seconds 1148.21 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 232832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130880 # Number of bytes read from this memory -system.physmem.bytes_read::total 363712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 232832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 232832 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3638 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5683 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2253417 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1266695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3520112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2253417 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2253417 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2253417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1266695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3520112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5683 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 235072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130944 # Number of bytes read from this memory +system.physmem.bytes_read::total 366016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 235072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 235072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2046 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5719 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2288443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1274749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3563192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2288443 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2288443 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2288443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1274749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3563192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5719 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5683 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5719 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 363712 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 366016 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 363712 # Total read bytes from the system interface side +system.physmem.bytesReadSys 366016 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 307 # Per bank write bursts -system.physmem.perBankRdBursts::1 383 # Per bank write bursts -system.physmem.perBankRdBursts::2 475 # Per bank write bursts -system.physmem.perBankRdBursts::3 366 # Per bank write bursts -system.physmem.perBankRdBursts::4 364 # Per bank write bursts -system.physmem.perBankRdBursts::5 336 # Per bank write bursts -system.physmem.perBankRdBursts::6 422 # Per bank write bursts -system.physmem.perBankRdBursts::7 392 # Per bank write bursts -system.physmem.perBankRdBursts::8 390 # Per bank write bursts -system.physmem.perBankRdBursts::9 296 # Per bank write bursts -system.physmem.perBankRdBursts::10 255 # Per bank write bursts -system.physmem.perBankRdBursts::11 273 # Per bank write bursts -system.physmem.perBankRdBursts::12 229 # Per bank write bursts -system.physmem.perBankRdBursts::13 485 # Per bank write bursts -system.physmem.perBankRdBursts::14 425 # Per bank write bursts -system.physmem.perBankRdBursts::15 285 # Per bank write bursts +system.physmem.perBankRdBursts::0 315 # Per bank write bursts +system.physmem.perBankRdBursts::1 393 # Per bank write bursts +system.physmem.perBankRdBursts::2 481 # Per bank write bursts +system.physmem.perBankRdBursts::3 362 # Per bank write bursts +system.physmem.perBankRdBursts::4 367 # Per bank write bursts +system.physmem.perBankRdBursts::5 335 # Per bank write bursts +system.physmem.perBankRdBursts::6 442 # Per bank write bursts +system.physmem.perBankRdBursts::7 357 # Per bank write bursts +system.physmem.perBankRdBursts::8 405 # Per bank write bursts +system.physmem.perBankRdBursts::9 298 # Per bank write bursts +system.physmem.perBankRdBursts::10 258 # Per bank write bursts +system.physmem.perBankRdBursts::11 270 # Per bank write bursts +system.physmem.perBankRdBursts::12 235 # Per bank write bursts +system.physmem.perBankRdBursts::13 489 # Per bank write bursts +system.physmem.perBankRdBursts::14 424 # Per bank write bursts +system.physmem.perBankRdBursts::15 288 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 103323737000 # Total gap between requests +system.physmem.totGap 102721127000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5683 # Read request sizes (log2) +system.physmem.readPktSize::6 5719 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,12 +91,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 973 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 287.745628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.611559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.712964 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 571 45.39% 45.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 250 19.87% 65.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94 7.47% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 5.17% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 43 3.42% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 4.53% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.31% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 22 1.75% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 127 10.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1258 # Bytes accessed per row activation -system.physmem.totQLat 187208250 # Total ticks spent queuing -system.physmem.totMemAccLat 293764500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 28415000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32941.80 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 289.245433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.404896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.969258 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 547 43.45% 43.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 270 21.45% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 107 8.50% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51 4.05% 77.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 47 3.73% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 64 5.08% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 1.91% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.99% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 124 9.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1259 # Bytes accessed per row activation +system.physmem.totQLat 198070500 # Total ticks spent queuing +system.physmem.totMemAccLat 305301750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34633.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51691.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 53383.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.56 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage @@ -217,309 +217,309 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4417 # Number of row buffer hits during reads +system.physmem.readRowHits 4452 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.72 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 18181196.02 # Average gap between requests -system.physmem.pageHitRate 77.72 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5404980 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2853840 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 21741300 # Energy for read commands per rank (pJ) +system.physmem.avgGap 17961379.09 # Average gap between requests +system.physmem.pageHitRate 77.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5319300 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2808300 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 21791280 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 298715040.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 95918460 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 16609440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 744016440 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 410144160 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 24152474700 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 25747878360 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.195533 # Core power per rank (mW) -system.physmem_0.totalIdleTime 103070096750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 32003500 # Time in different power states -system.physmem_0.memoryStateTime::REF 127050000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 100370697500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1068078250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 94522250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1631644000 # Time in different power states -system.physmem_1.actEnergy 3634260 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1920270 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18835320 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 308549280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94282560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 17303520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 739487790 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 445716000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 23991769245 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 25627073595 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.481384 # Core power per rank (mW) +system.physmem_0.totalIdleTime 102469123000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 33581500 # Time in different power states +system.physmem_0.memoryStateTime::REF 131264000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 99687058000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1160707250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87094500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1621680750 # Time in different power states +system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1969605 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19042380 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 228031440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73672500 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12688320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 586536840 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 299079840 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 24303470280 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 25527869070 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.066219 # Core power per rank (mW) -system.physmem_1.totalIdleTime 103129135750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 24348000 # Time in different power states -system.physmem_1.memoryStateTime::REF 96994000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 101064274500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 778849000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 73295500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1286234500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40855234 # Number of BP lookups -system.cpu.branchPred.condPredicted 40855234 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6727710 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 35293159 # Number of BTB lookups +system.physmem_1.refreshEnergy 233563200.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 75326640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12588960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 599034660 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 319716000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 24137455500 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 25402424025 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.294404 # Core power per rank (mW) +system.physmem_1.totalIdleTime 102523153750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 23880000 # Time in different power states +system.physmem_1.memoryStateTime::REF 99310000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 100377149750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 832585250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 74819500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1313641500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40475108 # Number of BP lookups +system.cpu.branchPred.condPredicted 40475108 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6616133 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 34806541 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3199678 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 605841 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 35293159 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 9878902 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 25414257 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 5019418 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 3130768 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 590894 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 34806541 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9997740 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 24808801 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4890379 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 206647992 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 205442773 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 46314104 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 419677545 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40855234 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13078580 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 152558577 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14911731 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 146 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 6162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 75545 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 535 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 173 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 41227932 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1521125 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 10 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 206411107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.413574 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.660203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 45893468 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 415890095 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40475108 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13128508 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 151898710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14677491 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 200 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 64355 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 603 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 40893606 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1496111 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 12 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 205202132 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.402306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.658033 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 99253613 48.09% 48.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5140686 2.49% 50.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5371591 2.60% 53.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5329252 2.58% 55.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6011005 2.91% 58.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5851603 2.83% 61.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5726027 2.77% 64.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4748810 2.30% 66.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68978520 33.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98918732 48.21% 48.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5142243 2.51% 50.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5340112 2.60% 53.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5342271 2.60% 55.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5947890 2.90% 58.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5817544 2.84% 61.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5684313 2.77% 64.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4746268 2.31% 66.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68262759 33.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 206411107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.197704 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.030881 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32267820 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86650194 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 62332865 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17704363 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7455865 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 590435256 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7455865 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42053837 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46607662 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29929 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68827187 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41436627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 551754102 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1587 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36503796 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4817365 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 169314 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 629088770 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1485013522 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 974082903 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 15054868 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 205202132 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.197014 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.024360 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31935878 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86571693 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 61623233 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17732583 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7338745 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 585424017 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7338745 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 41662208 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46227710 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28975 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68218759 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41725735 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 547333455 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1808 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36710047 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4936211 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 172798 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 624155686 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1473918398 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 966803184 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 14714209 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 369659320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2323 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2340 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89508181 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128738720 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 45872059 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 77414851 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25246681 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 490126112 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 61893 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 338153574 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1099180 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 268824621 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 526308720 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 60648 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 206411107 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.638253 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.802953 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 364726236 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2257 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2274 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89803577 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 127813025 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45569326 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 76700063 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25076085 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 486700618 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 63617 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 336591199 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1075816 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 265400851 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 520101355 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 62372 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 205202132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.640291 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.801229 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 73313522 35.52% 35.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46679908 22.62% 58.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32876430 15.93% 74.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20896006 10.12% 84.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15048824 7.29% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8392050 4.07% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5201413 2.52% 98.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2354868 1.14% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1648086 0.80% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72558879 35.36% 35.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46563371 22.69% 58.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32833591 16.00% 74.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20829399 10.15% 84.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14957397 7.29% 91.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8327086 4.06% 95.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5158088 2.51% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2335665 1.14% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1638656 0.80% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 206411107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 205202132 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 756912 19.27% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2690839 68.51% 87.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 431049 10.97% 98.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 45501 1.16% 99.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 3340 0.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 746075 18.99% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2709270 68.98% 87.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 425878 10.84% 98.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 43262 1.10% 99.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 3383 0.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211791 0.36% 0.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 216412325 64.00% 64.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800256 0.24% 64.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7047583 2.08% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1802667 0.53% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 82552665 24.41% 91.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26471074 7.83% 99.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 1726255 0.51% 99.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 128958 0.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212158 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 215249611 63.95% 64.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800532 0.24% 64.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7048368 2.09% 66.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1789279 0.53% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 82235879 24.43% 91.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26412297 7.85% 99.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 1712250 0.51% 99.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 130825 0.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 338153574 # Type of FU issued -system.cpu.iq.rate 1.636375 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3927641 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011615 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 879585731 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 744431622 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 315835107 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8159345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 15410519 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3544176 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 336768258 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4101166 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18155454 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 336591199 # Type of FU issued +system.cpu.iq.rate 1.638370 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3927868 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011670 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 875283157 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 737961913 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 314539873 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8105057 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15024545 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3526208 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 335233754 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4073155 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18221671 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 72089133 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55091 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 866955 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 25356342 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 71163438 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 53029 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 858947 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25053609 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50448 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 55 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50433 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7455865 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35715167 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 589866 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 490188005 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1248811 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128738720 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 45872059 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22561 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 546009 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38338 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 866955 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1295323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6857589 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8152912 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 326241588 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 80652390 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11911986 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7338745 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35257397 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 584477 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 486764235 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1231542 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 127813025 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45569326 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23100 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 542722 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38323 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 858947 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1297189 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6715157 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8012346 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 324846022 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80370790 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11745177 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 106269865 # number of memory reference insts executed -system.cpu.iew.exec_branches 18918443 # Number of branches executed -system.cpu.iew.exec_stores 25617475 # Number of stores executed -system.cpu.iew.exec_rate 1.578731 # Inst execution rate -system.cpu.iew.wb_sent 322387752 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 319379283 # cumulative count of insts written-back -system.cpu.iew.wb_producers 256328359 # num instructions producing a value -system.cpu.iew.wb_consumers 435429845 # num instructions consuming a value -system.cpu.iew.wb_rate 1.545523 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588679 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 268850223 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 105939673 # number of memory reference insts executed +system.cpu.iew.exec_branches 18800592 # Number of branches executed +system.cpu.iew.exec_stores 25568883 # Number of stores executed +system.cpu.iew.exec_rate 1.581200 # Inst execution rate +system.cpu.iew.wb_sent 321037948 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 318066081 # cumulative count of insts written-back +system.cpu.iew.wb_producers 255309822 # num instructions producing a value +system.cpu.iew.wb_consumers 434053597 # num instructions consuming a value +system.cpu.iew.wb_rate 1.548198 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588199 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 265431223 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6732902 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 163914906 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.350477 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.932475 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6620631 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163283495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.355700 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.936592 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67189595 40.99% 40.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 54970007 33.54% 74.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13274329 8.10% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10696589 6.53% 89.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5450081 3.32% 92.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3128441 1.91% 94.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1086544 0.66% 95.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1161401 0.71% 95.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6957919 4.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 66681947 40.84% 40.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54877402 33.61% 74.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13218916 8.10% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10716769 6.56% 89.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5408933 3.31% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3143149 1.92% 94.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1097453 0.67% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1149760 0.70% 95.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6989166 4.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 163914906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163283495 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,469 +569,469 @@ system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6957919 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 647170594 # The number of ROB reads -system.cpu.rob.rob_writes 1023323556 # The number of ROB writes -system.cpu.timesIdled 2853 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 236885 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6989166 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 643088936 # The number of ROB reads +system.cpu.rob.rob_writes 1015902477 # The number of ROB writes +system.cpu.timesIdled 2803 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 240641 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.564671 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.564671 # CPI: Total CPI of All Threads -system.cpu.ipc 0.639112 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.639112 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 524350393 # number of integer regfile reads -system.cpu.int_regfile_writes 288862618 # number of integer regfile writes -system.cpu.fp_regfile_reads 4510095 # number of floating regfile reads -system.cpu.fp_regfile_writes 3309705 # number of floating regfile writes -system.cpu.cc_regfile_reads 106995415 # number of cc regfile reads -system.cpu.cc_regfile_writes 65768687 # number of cc regfile writes -system.cpu.misc_regfile_reads 176729824 # number of misc regfile reads +system.cpu.cpi 1.555546 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.555546 # CPI: Total CPI of All Threads +system.cpu.ipc 0.642861 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.642861 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 522853571 # number of integer regfile reads +system.cpu.int_regfile_writes 287693953 # number of integer regfile writes +system.cpu.fp_regfile_reads 4488277 # number of floating regfile reads +system.cpu.fp_regfile_writes 3288210 # number of floating regfile writes +system.cpu.cc_regfile_reads 106934935 # number of cc regfile reads +system.cpu.cc_regfile_writes 65654592 # number of cc regfile writes +system.cpu.misc_regfile_reads 175824659 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 82 # number of replacements -system.cpu.dcache.tags.tagsinuse 1514.501359 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 82730891 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2127 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 38895.576399 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 101 # number of replacements +system.cpu.dcache.tags.tagsinuse 1519.152295 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82373071 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2121 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38836.902876 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1514.501359 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.369751 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.369751 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 418 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1470 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.499268 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 165469279 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 165469279 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 62216578 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 62216578 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513684 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513684 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 82730262 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 82730262 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 82730262 # number of overall hits -system.cpu.dcache.overall_hits::total 82730262 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1267 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1267 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2047 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2047 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3314 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3314 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3314 # number of overall misses -system.cpu.dcache.overall_misses::total 3314 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 112642500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 112642500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 136500000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 136500000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 249142500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 249142500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 249142500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 249142500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 62217845 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 62217845 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1519.152295 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.370887 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.370887 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2020 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 426 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1452 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.493164 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 164753603 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 164753603 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 61858750 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 61858750 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513717 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513717 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82372467 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82372467 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82372467 # number of overall hits +system.cpu.dcache.overall_hits::total 82372467 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1260 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1260 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2014 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3274 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3274 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3274 # number of overall misses +system.cpu.dcache.overall_misses::total 3274 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128800000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128800000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 138047000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 138047000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 266847000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 266847000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 266847000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 266847000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 61860010 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 61860010 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82733576 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82733576 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82733576 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82733576 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 82375741 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82375741 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82375741 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82375741 # 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average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66682.950660 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66682.950660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75178.786964 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75178.786964 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 331 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 143 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.750000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17 # number of writebacks -system.cpu.dcache.writebacks::total 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 658 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 658 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 664 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 664 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 609 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204711000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 204711000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204711000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 204711000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 102222.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68543.694141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68543.694141 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81504.886988 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81504.886988 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81504.886988 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81504.886988 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 58 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 127 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 22 # number of writebacks +system.cpu.dcache.writebacks::total 22 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 652 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 652 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 663 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 663 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 663 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 663 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 608 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2003 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2611 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2611 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2611 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2611 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79597500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 79597500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135457500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 135457500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215055000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215055000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215055000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215055000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000099 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115991.789819 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115991.789819 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65689.367957 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65689.367957 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 6640 # number of replacements -system.cpu.icache.tags.tagsinuse 1671.571610 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 41214631 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8628 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4776.846430 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 130916.940789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 130916.940789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67627.309036 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67627.309036 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82364.994255 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82364.994255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82364.994255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82364.994255 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 6438 # number of replacements +system.cpu.icache.tags.tagsinuse 1691.823634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 40880551 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8435 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4846.538352 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1671.571610 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.816197 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.816197 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1988 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 860 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 713 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.970703 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 82465000 # Number of tag accesses -system.cpu.icache.tags.data_accesses 82465000 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 41214631 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41214631 # 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number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 657223000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 657223000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 657223000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 41227928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41227928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 41227928 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41227928 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 41227928 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41227928 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000323 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000323 # 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number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.125000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 107 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6640 # number of writebacks -system.cpu.icache.writebacks::total 6640 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4152 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4152 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4152 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4152 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4152 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4152 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9145 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9145 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9145 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9145 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9145 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9145 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 457240000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 457240000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 457240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 457240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 457240000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 457240000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000222 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000222 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000222 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49998.906506 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49998.906506 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49998.906506 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49998.906506 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49998.906506 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49998.906506 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.occ_blocks::cpu.inst 1691.823634 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.826086 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.826086 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1997 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 850 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 731 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.975098 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 81796128 # Number of tag accesses +system.cpu.icache.tags.data_accesses 81796128 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 40880552 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 40880552 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 40880552 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 40880552 # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8434 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2121 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 10555 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994719 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994719 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.435499 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.435499 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.889439 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.889439 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.435499 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964639 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.541829 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.435499 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964639 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.541829 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84197.743862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84197.743862 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106926.490607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106926.490607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 144271.799629 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 144271.799629 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106926.490607 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100023.704790 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 104456.985487 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106926.490607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100023.704790 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 104456.985487 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1513 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1513 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3638 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3638 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3638 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2045 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5683 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3638 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2045 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5683 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 109950500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 109950500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 353832000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 353832000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63372500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63372500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 353832000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173323000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 527155000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 353832000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173323000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 527155000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995395 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995395 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.422042 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.876442 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.876442 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.528799 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.528799 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72670.522141 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72670.522141 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97260.032985 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97260.032985 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 119121.240602 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 119121.240602 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18517 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 6823 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3673 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3673 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 539 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 539 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2046 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5719 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5719 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111816000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111816000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 356011000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 356011000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 72372500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 72372500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 356011000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 184188500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 540199500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 356011000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 184188500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 540199500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994719 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994719 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.435499 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.889439 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.889439 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964639 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.541829 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964639 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.541829 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74197.743862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74197.743862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96926.490607 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96926.490607 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 134271.799629 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 134271.799629 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96926.490607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90023.704790 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94456.985487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96926.490607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90023.704790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94456.985487 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18075 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 6619 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 9751 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6640 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 65 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 9145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 607 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24404 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5382 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 29786 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1113792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 525 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 33600 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11795 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.096651 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.295495 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 9530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6438 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 8925 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 606 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23796 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5323 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 951744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1088896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 491 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 31424 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11536 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091713 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288633 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10655 90.33% 90.33% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1140 9.67% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10478 90.83% 90.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1058 9.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11795 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15915500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11536 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15497500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13716000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13386000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3452000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3426999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5683 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 5719 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4170 # Transaction distribution -system.membus.trans_dist::ReadExReq 1513 # Transaction distribution -system.membus.trans_dist::ReadExResp 1513 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4170 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11366 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11366 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11366 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 363712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 363712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 363712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4212 # Transaction distribution +system.membus.trans_dist::ReadExReq 1507 # Transaction distribution +system.membus.trans_dist::ReadExResp 1507 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4212 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11438 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 366016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 366016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 366016 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5683 # Request fanout histogram +system.membus.snoop_fanout::samples 5719 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5683 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5719 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5683 # Request fanout histogram -system.membus.reqLayer0.occupancy 6909500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5719 # Request fanout histogram +system.membus.reqLayer0.occupancy 6957500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 30126750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 30309750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |