diff options
Diffstat (limited to 'tests/long/se/70.twolf')
15 files changed, 2814 insertions, 2714 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini index 5e0a983c6..35828777f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout index 9e68a8154..4b089cf00 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout @@ -3,11 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4311 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:43 +gem5 executing on e108600-lin, pid 28042 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/minor-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -24,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 53344764500 because target called exit() +122 123 124 Exiting @ tick 53437621500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index d3e370d8a..2c8dfca63 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.053349 # Number of seconds simulated -sim_ticks 53349450500 # Number of ticks simulated -final_tick 53349450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.053438 # Number of seconds simulated +sim_ticks 53437621500 # Number of ticks simulated +final_tick 53437621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 273465 # Simulator instruction rate (inst/s) -host_op_rate 273465 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158745564 # Simulator tick rate (ticks/s) -host_mem_usage 258296 # Number of bytes of host memory used -host_seconds 336.07 # Real time elapsed on the host +host_inst_rate 247892 # Simulator instruction rate (inst/s) +host_op_rate 247892 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 144138078 # Simulator tick rate (ticks/s) +host_mem_usage 256712 # Number of bytes of host memory used +host_seconds 370.74 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory system.physmem.bytes_read::total 340608 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 202880 # Nu system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3802851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6384471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3802851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3802851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3802851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2581620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6384471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3796576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2577360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6373936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3796576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3796576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3796576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2577360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6373936 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5322 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 53349362500 # Total gap between requests +system.physmem.totGap 53437285500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4860 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 449 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 345.743381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.338865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.606559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 303 30.86% 30.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 220 22.40% 53.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94 9.57% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 105 10.69% 73.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 62 6.31% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 3.67% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.95% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 22 2.24% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 111 11.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation -system.physmem.totQLat 40016750 # Total ticks spent queuing -system.physmem.totMemAccLat 139804250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 347.009174 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.710292 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.985210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 311 31.70% 31.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 198 20.18% 51.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 103 10.50% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 115 11.72% 74.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 57 5.81% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 30 3.06% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 3.06% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 2.65% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 111 11.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 981 # Bytes accessed per row activation +system.physmem.totQLat 132267250 # Total ticks spent queuing +system.physmem.totMemAccLat 232054750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7519.12 # Average queueing delay per DRAM burst +system.physmem.avgQLat 24852.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26269.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 43602.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.38 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -217,49 +217,59 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4333 # Number of row buffer hits during reads +system.physmem.readRowHits 4338 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10024307.12 # Average gap between requests -system.physmem.pageHitRate 81.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3462480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1889250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 10040827.79 # Average gap between requests +system.physmem.pageHitRate 81.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3348660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1772265 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18335520 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1795262310 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30431523750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 35736125550 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.920144 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 50622338000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1781260000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 940274500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3923640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2140875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21247200 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 173328480.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64638000 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9138240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 468346770 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 218747040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12435217200 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 13392872175 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.626273 # Core power per rank (mW) +system.physmem_0.totalIdleTime 53271099000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 16953500 # Time in different power states +system.physmem_0.memoryStateTime::REF 73680000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51675337000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 569631000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 74922500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1027097500 # Time in different power states +system.physmem_1.actEnergy 3677100 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1950630 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19663560 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1822659075 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 30407483250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 35741598600 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.022916 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 50582866250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1781260000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 980601250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11450641 # Number of BP lookups -system.cpu.branchPred.condPredicted 8210938 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 765018 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6085190 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5320739 # Number of BTB hits +system.physmem_1.refreshEnergy 191767680.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68393160 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 9924480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 510653310 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 251520000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12393371550 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 13451137230 # Total energy per rank (pJ) +system.physmem_1.averagePower 251.716611 # Core power per rank (mW) +system.physmem_1.totalIdleTime 53261175500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 18732000 # Time in different power states +system.physmem_1.memoryStateTime::REF 81534000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51486455000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 654968250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 76126500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1119805750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 11450652 # Number of BP lookups +system.cpu.branchPred.condPredicted 8210942 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765019 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6085116 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5320742 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.437516 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176674 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.438629 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176677 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits. @@ -282,10 +292,10 @@ system.cpu.dtb.data_hits 26995130 # DT system.cpu.dtb.data_misses 43659 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27038789 # DTB accesses -system.cpu.itb.fetch_hits 22968614 # ITB hits +system.cpu.itb.fetch_hits 22968644 # ITB hits system.cpu.itb.fetch_misses 90 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22968704 # ITB accesses +system.cpu.itb.fetch_accesses 22968734 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 106698901 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 106875243 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2191321 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2191333 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.160994 # CPI: cycles per instruction -system.cpu.ipc 0.861331 # IPC: instructions per cycle +system.cpu.cpi 1.162912 # CPI: cycles per instruction +system.cpu.ipc 0.859910 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction @@ -344,76 +354,76 @@ system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91903089 # Class of committed instruction -system.cpu.tickCycles 103791781 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2907120 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 103792204 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3083039 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.584590 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26572201 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1447.203649 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26572187 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11910.444195 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11910.437920 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584590 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353414 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353414 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.203649 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353321 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353321 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53153439 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53153439 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20074005 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20074005 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498196 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498196 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26572201 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26572201 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26572201 # number of overall hits -system.cpu.dcache.overall_hits::total 26572201 # number of overall hits +system.cpu.dcache.tags.tag_accesses 53153435 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53153435 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20074003 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20074003 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498184 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498184 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26572187 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26572187 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26572187 # number of overall hits +system.cpu.dcache.overall_hits::total 26572187 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2907 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2907 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3403 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3403 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3403 # number of overall misses -system.cpu.dcache.overall_misses::total 3403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37687000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37687000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 223750000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 223750000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 261437000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 261437000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 261437000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 261437000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20074501 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20074501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 2919 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2919 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3415 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3415 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3415 # number of overall misses +system.cpu.dcache.overall_misses::total 3415 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58822000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58822000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 274731500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 274731500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 333553500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 333553500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 333553500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 333553500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20074499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20074499 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26575604 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26575604 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26575604 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26575604 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26575602 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26575602 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26575602 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26575602 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75981.854839 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75981.854839 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76969.384245 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76969.384245 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76825.448134 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76825.448134 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000449 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000449 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 118592.741935 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 118592.741935 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94118.362453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 94118.362453 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 97673.060029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 97673.060029 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +434,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1164 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1164 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1172 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1172 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1172 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1172 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1176 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1176 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1184 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1184 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1184 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1184 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses @@ -438,14 +448,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2231 system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36777500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36777500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 140150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 140150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 176927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176927500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 176927500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 57888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 57888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 165966000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 165966000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 223854500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 223854500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 223854500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 223854500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -454,70 +464,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75363.729508 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75363.729508 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80407.343660 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80407.343660 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 118623.975410 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 118623.975410 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95218.588640 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95218.588640 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13865 # number of replacements -system.cpu.icache.tags.tagsinuse 1642.701416 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22952783 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1642.239495 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22952813 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1449.954706 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1449.956601 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1642.701416 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.802100 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.802100 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1642.239495 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801875 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801875 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45953058 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45953058 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22952783 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22952783 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22952783 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22952783 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22952783 # number of overall hits -system.cpu.icache.overall_hits::total 22952783 # number of overall hits +system.cpu.icache.tags.tag_accesses 45953118 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45953118 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22952813 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22952813 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22952813 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22952813 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22952813 # number of overall hits +system.cpu.icache.overall_hits::total 22952813 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses system.cpu.icache.overall_misses::total 15831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 411111000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 411111000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 411111000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 411111000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 411111000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 411111000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22968614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22968614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22968614 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22968614 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22968614 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22968614 # number of overall (read+write) accesses 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number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22968644 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25968.732234 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25968.732234 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25968.732234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25968.732234 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28831.975238 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28831.975238 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28831.975238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28831.975238 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,46 +542,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15831 system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 395281000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 395281000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 395281000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 395281000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 395281000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 395281000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 440609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 440609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440609000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 440609000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24968.795401 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24968.795401 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27832.038406 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27832.038406 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3575.444447 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3574.446973 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.450993 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.993454 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064162 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.044952 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.109114 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.836656 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.610316 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064143 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044941 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.109083 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits @@ -600,18 +610,18 @@ system.cpu.l2cache.demand_misses::total 5322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses system.cpu.l2cache.overall_misses::total 5322 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 137262000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 137262000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 238604500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 238604500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35483000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 35483000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 238604500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 172745000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 411349500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 238604500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 172745000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 411349500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163078000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 163078000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 283932500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 283932500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 56594000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 56594000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 283932500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 219672000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 503604500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 283932500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 219672000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 503604500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses) @@ -640,18 +650,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294668 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79942.923704 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79942.923704 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75269.558360 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75269.558360 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81570.114943 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81570.114943 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77292.277339 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77292.277339 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94978.450786 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94978.450786 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89568.611987 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89568.611987 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 130101.149425 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 130101.149425 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94626.925968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94626.925968 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,18 +680,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120092000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120092000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 206904500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 206904500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31133000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31133000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206904500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151225000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 358129500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206904500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151225000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 358129500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 145908000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 145908000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252232500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252232500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 52244000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 52244000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252232500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 198152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 450384500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252232500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 198152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 450384500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses @@ -694,25 +704,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69942.923704 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69942.923704 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65269.558360 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65269.558360 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71570.114943 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71570.114943 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84978.450786 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84978.450786 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79568.611987 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79568.611987 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 120101.149425 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 120101.149425 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution @@ -752,7 +762,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3605 # Transaction distribution system.membus.trans_dist::ReadExReq 1717 # Transaction distribution system.membus.trans_dist::ReadExResp 1717 # Transaction distribution @@ -773,9 +783,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5322 # Request fanout histogram -system.membus.reqLayer0.occupancy 6421000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6424500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28180500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28175000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index d82573b75..f4beb67d4 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 1d7fd9550..e5a3bf839 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4313 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28064 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/o3-timing Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav @@ -26,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 21909208500 because target called exit() +122 123 124 Exiting @ tick 21954917500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 720778178..2ed297d74 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021906 # Number of seconds simulated -sim_ticks 21906070500 # Number of ticks simulated -final_tick 21906070500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021955 # Number of seconds simulated +sim_ticks 21954917500 # Number of ticks simulated +final_tick 21954917500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201237 # Simulator instruction rate (inst/s) -host_op_rate 201237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52367931 # Simulator tick rate (ticks/s) -host_mem_usage 260088 # Number of bytes of host memory used -host_seconds 418.31 # Real time elapsed on the host +host_inst_rate 181107 # Simulator instruction rate (inst/s) +host_op_rate 181107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47234568 # Simulator tick rate (ticks/s) +host_mem_usage 257228 # Number of bytes of host memory used +host_seconds 464.81 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 334528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 334464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8945831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6325187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15271018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8945831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8945831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8945831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6325187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15271018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5227 # Number of read requests accepted +system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8923012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6311115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15234127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8923012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8923012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8923012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6311115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15234127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5226 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5226 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334464 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334464 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 470 # Per bank write bursts +system.physmem.perBankRdBursts::0 469 # Per bank write bursts system.physmem.perBankRdBursts::1 292 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts system.physmem.perBankRdBursts::3 523 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21905974500 # Total gap between requests +system.physmem.totGap 21954815500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5227 # Read request sizes (log2) +system.physmem.readPktSize::6 5226 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,105 +187,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 385.707657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.399691 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 360.883028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 260 30.16% 30.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 179 20.77% 50.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 93 10.79% 61.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.61% 68.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 30 3.48% 71.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 4.29% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 31 3.60% 79.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 50 5.80% 85.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 125 14.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 862 # Bytes accessed per row activation -system.physmem.totQLat 40339750 # Total ticks spent queuing -system.physmem.totMemAccLat 138346000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7717.57 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385.932636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.340491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.649518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 261 30.31% 30.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 173 20.09% 50.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 93 10.80% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.62% 67.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37 4.30% 72.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 30 3.48% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 47 5.46% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 3.83% 84.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 130 15.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 861 # Bytes accessed per row activation +system.physmem.totQLat 128746000 # Total ticks spent queuing +system.physmem.totMemAccLat 226733500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26130000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24635.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26467.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 43385.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4357 # Number of row buffer hits during reads +system.physmem.readRowHits 4356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4190926.82 # Average gap between requests -system.physmem.pageHitRate 83.36 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3129840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1707750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19570200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4201074.53 # Average gap between requests +system.physmem.pageHitRate 83.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3034500 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1593900 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18099900 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 905463810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12347522250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14707973130 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.505534 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20538678250 # Time in different power states -system.physmem_0.memoryStateTime::REF 731380000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 632936750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3333960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1819125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20779200 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 118625520.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 48811380 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6176640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 312556080 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 154176960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 5001436845 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 5664547785 # Total energy per rank (pJ) +system.physmem_0.averagePower 258.008156 # Core power per rank (mW) +system.physmem_0.totalIdleTime 21831003750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 11536500 # Time in different power states +system.physmem_0.memoryStateTime::REF 50426000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 20744771750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 401491250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 61308000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 685384000 # Time in different power states +system.physmem_1.actEnergy 3177300 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1673595 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19213740 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 902236185 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12350353500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14709101250 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.557040 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20543762750 # Time in different power states -system.physmem_1.memoryStateTime::REF 731380000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 628284250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16102243 # Number of BP lookups -system.cpu.branchPred.condPredicted 11688063 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 931000 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8962915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7507921 # Number of BTB hits +system.physmem_1.refreshEnergy 106332720.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46621440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 5256960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 301076850 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 131936160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 5018107080 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 5633395845 # Total energy per rank (pJ) +system.physmem_1.averagePower 256.589251 # Core power per rank (mW) +system.physmem_1.totalIdleTime 21838957750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 9258500 # Time in different power states +system.physmem_1.memoryStateTime::REF 45178000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 20835144000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 343577000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 61468500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 660291500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16102182 # Number of BP lookups +system.cpu.branchPred.condPredicted 11688137 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 930988 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8963257 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7508303 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.766509 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1594308 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.767575 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1594537 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 466 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 29379 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25730 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3649 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 29363 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3639 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24059471 # DTB read hits -system.cpu.dtb.read_misses 206747 # DTB read misses -system.cpu.dtb.read_acv 6 # DTB read access violations -system.cpu.dtb.read_accesses 24266218 # DTB read accesses -system.cpu.dtb.write_hits 7167964 # DTB write hits -system.cpu.dtb.write_misses 1190 # DTB write misses +system.cpu.dtb.read_hits 24064359 # DTB read hits +system.cpu.dtb.read_misses 206311 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 24270670 # DTB read accesses +system.cpu.dtb.write_hits 7168837 # DTB write hits +system.cpu.dtb.write_misses 1192 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7169154 # DTB write accesses -system.cpu.dtb.data_hits 31227435 # DTB hits -system.cpu.dtb.data_misses 207937 # DTB misses -system.cpu.dtb.data_acv 6 # DTB access violations -system.cpu.dtb.data_accesses 31435372 # DTB accesses -system.cpu.itb.fetch_hits 15930202 # ITB hits +system.cpu.dtb.write_accesses 7170029 # DTB write accesses +system.cpu.dtb.data_hits 31233196 # DTB hits +system.cpu.dtb.data_misses 207503 # DTB misses +system.cpu.dtb.data_acv 4 # DTB access violations +system.cpu.dtb.data_accesses 31440699 # DTB accesses +system.cpu.itb.fetch_hits 15932695 # ITB hits system.cpu.itb.fetch_misses 79 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15930281 # ITB accesses +system.cpu.itb.fetch_accesses 15932774 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,140 +309,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 43812142 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 43909836 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16640800 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137955116 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16102243 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9127959 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 25951378 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1939862 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2284 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15930202 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367997 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43564561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.166682 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433652 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16643979 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137979397 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16102182 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9128564 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 26000321 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1939876 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2307 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15932695 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367713 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43616730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.163451 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433365 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19388904 44.51% 44.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2617971 6.01% 50.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1329653 3.05% 53.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1933242 4.44% 58.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3001866 6.89% 64.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1292154 2.97% 67.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1355153 3.11% 70.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 885983 2.03% 73.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11759635 26.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19436456 44.56% 44.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2618537 6.00% 50.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1330059 3.05% 53.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1934096 4.43% 58.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3001834 6.88% 64.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1292274 2.96% 67.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1355703 3.11% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 886638 2.03% 73.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11761133 26.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43564561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367529 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.148787 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12866207 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8201064 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19435677 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2103016 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 958597 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2653560 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11864 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132121785 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49799 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 958597 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13983011 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4637206 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10599 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20305280 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3669868 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128752916 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 70736 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2012785 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1367413 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 56554 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94580122 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167299448 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159747069 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7552378 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43616730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.366710 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.142335 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12867029 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8250930 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19434015 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2106147 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 958609 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2654207 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11848 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132149793 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49699 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 958609 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13986200 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4658485 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10631 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20305693 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3697112 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128776944 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70815 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2027533 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1361651 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 79521 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94599397 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167333600 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159779432 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7554167 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26152761 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 954 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 949 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8254781 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26901517 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8704631 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3463893 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1634991 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111837286 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1924 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99746434 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118591 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27659500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21091403 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1535 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43564561 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.289623 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099110 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26172036 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 950 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8272242 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26904484 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8704450 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3461355 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1614052 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111855473 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1918 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99762246 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119439 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27677681 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21095832 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1529 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43616730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.287247 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099564 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11223672 25.76% 25.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7655343 17.57% 43.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7467756 17.14% 60.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5704970 13.10% 73.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4467403 10.25% 83.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2981246 6.84% 90.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2039535 4.68% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1169471 2.68% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 855165 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11270720 25.84% 25.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7659760 17.56% 43.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7470187 17.13% 60.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5700495 13.07% 73.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4466514 10.24% 83.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2981046 6.83% 90.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2041941 4.68% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1170841 2.68% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 855226 1.96% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43564561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43616730 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 481664 20.16% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 484010 20.16% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 522 0.02% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34768 1.46% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12121 0.51% 22.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1011551 42.34% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 688710 28.83% 93.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159620 6.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34926 1.45% 21.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12192 0.51% 22.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1012503 42.17% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 694860 28.94% 93.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 162157 6.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60652801 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 489881 0.49% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60662676 60.81% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2847832 2.86% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115342 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2442782 2.45% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314177 0.31% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 766025 0.77% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2847523 2.85% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2443321 2.45% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314198 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued @@ -454,82 +464,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24850091 24.91% 92.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7267177 7.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24854622 24.91% 92.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7268455 7.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99746434 # Type of FU issued -system.cpu.iq.rate 2.276685 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2388956 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023950 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229877287 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 129889935 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89741335 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15687689 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9649325 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7189295 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93754597 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8380786 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1921314 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99762246 # Type of FU issued +system.cpu.iq.rate 2.271979 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2401186 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024069 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229973015 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129921960 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89757276 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15688832 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9653681 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7189481 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93781523 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8381902 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1923320 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6905319 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11494 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 40918 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2203528 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6908286 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11342 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40947 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2203347 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42864 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1503 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 958597 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3610605 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 461685 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122758059 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241249 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26901517 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8704631 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1924 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38682 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 417297 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 40918 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 531922 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502439 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98421413 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24266766 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1325021 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 958609 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3613912 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 479107 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122779790 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241415 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26904484 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8704450 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1918 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38391 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 434865 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40947 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502384 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034333 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98436741 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24271214 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1325505 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10918849 # number of nop insts executed -system.cpu.iew.exec_refs 31435958 # number of memory reference insts executed -system.cpu.iew.exec_branches 12470734 # Number of branches executed -system.cpu.iew.exec_stores 7169192 # Number of stores executed -system.cpu.iew.exec_rate 2.246441 # Inst execution rate -system.cpu.iew.wb_sent 97629714 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96930630 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66965531 # num instructions producing a value -system.cpu.iew.wb_consumers 94946242 # num instructions consuming a value -system.cpu.iew.wb_rate 2.212415 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705299 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 30856710 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10922399 # number of nop insts executed +system.cpu.iew.exec_refs 31441282 # number of memory reference insts executed +system.cpu.iew.exec_branches 12471732 # Number of branches executed +system.cpu.iew.exec_stores 7170068 # Number of stores executed +system.cpu.iew.exec_rate 2.241792 # Inst execution rate +system.cpu.iew.wb_sent 97645487 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96946757 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66976137 # num instructions producing a value +system.cpu.iew.wb_consumers 94960144 # num instructions consuming a value +system.cpu.iew.wb_rate 2.207860 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705308 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 30878503 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 919666 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39073158 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.352076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.920100 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 919659 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39122931 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.349084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.919383 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14677251 37.56% 37.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8528323 21.83% 59.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3880033 9.93% 69.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1914323 4.90% 74.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1374739 3.52% 77.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1034073 2.65% 80.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692942 1.77% 82.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727068 1.86% 84.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6244406 15.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14724541 37.64% 37.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8532800 21.81% 59.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3880104 9.92% 69.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1909784 4.88% 74.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1376640 3.52% 77.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1034511 2.64% 80.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692868 1.77% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 729092 1.86% 84.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6242591 15.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39073158 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39122931 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -575,118 +585,118 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6244406 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155587477 # The number of ROB reads -system.cpu.rob.rob_writes 250066312 # The number of ROB writes -system.cpu.timesIdled 4758 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 247581 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6242591 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155660858 # The number of ROB reads +system.cpu.rob.rob_writes 250112359 # The number of ROB writes +system.cpu.timesIdled 4774 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 293106 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.520460 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520460 # CPI: Total CPI of All Threads -system.cpu.ipc 1.921379 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.921379 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 132984940 # number of integer regfile reads -system.cpu.int_regfile_writes 72890464 # number of integer regfile writes -system.cpu.fp_regfile_reads 6263699 # number of floating regfile reads -system.cpu.fp_regfile_writes 6177982 # number of floating regfile writes -system.cpu.misc_regfile_reads 719169 # number of misc regfile reads +system.cpu.cpi 0.521620 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.521620 # CPI: Total CPI of All Threads +system.cpu.ipc 1.917104 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.917104 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133010551 # number of integer regfile reads +system.cpu.int_regfile_writes 72904644 # number of integer regfile writes +system.cpu.fp_regfile_reads 6263409 # number of floating regfile reads +system.cpu.fp_regfile_writes 6178123 # number of floating regfile writes +system.cpu.misc_regfile_reads 719113 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.358075 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28585648 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1457.034872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28588531 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12733.028062 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12734.312249 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.358075 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355800 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355800 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.034872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355721 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355721 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57192649 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57192649 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22092545 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22092545 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492630 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492630 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 473 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 473 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28585175 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28585175 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28585175 # number of overall hits -system.cpu.dcache.overall_hits::total 28585175 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1080 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1080 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8473 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8473 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 57198427 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57198427 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22095438 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22095438 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492623 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492623 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28588061 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28588061 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28588061 # number of overall hits +system.cpu.dcache.overall_hits::total 28588061 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1079 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1079 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8480 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8480 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9553 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9553 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9553 # number of overall misses -system.cpu.dcache.overall_misses::total 9553 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 72549500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 72549500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 550211742 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 550211742 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 86000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 86000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 622761242 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 622761242 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 622761242 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 622761242 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22093625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22093625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9559 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9559 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9559 # number of overall misses +system.cpu.dcache.overall_misses::total 9559 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87318000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87318000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 649645257 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 649645257 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 106000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 106000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 736963257 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 736963257 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 736963257 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 736963257 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22096517 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22096517 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 474 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 474 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28594728 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28594728 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28594728 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28594728 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28597620 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28597620 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28597620 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28597620 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001303 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002110 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002110 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67175.462963 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67175.462963 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64937.063850 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64937.063850 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 86000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 86000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65190.122684 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65190.122684 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33457 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 396 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.487374 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80924.930491 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 80924.930491 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76609.110495 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76609.110495 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 106000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 106000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77096.271263 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77096.271263 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 43101 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 174 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 350 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 123.145714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 565 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 565 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6744 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6744 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7309 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7309 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7309 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7309 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6751 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6751 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7315 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7315 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7315 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7315 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1729 # number of WriteReq MSHR misses @@ -697,232 +707,232 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2244 system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 136978995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 136978995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 85000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 85000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177801495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 177801495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177801495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 177801495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47711000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47711000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177283495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 177283495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224994495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 224994495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224994495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 224994495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002110 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002110 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002123 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002123 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79266.990291 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79266.990291 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79224.404280 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79224.404280 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 85000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 85000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 9515 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.893985 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15915792 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11453 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1389.661399 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92642.718447 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92642.718447 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102535.277617 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102535.277617 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 105000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 105000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100264.926471 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 100264.926471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100264.926471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 100264.926471 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 9511 # number of replacements +system.cpu.icache.tags.tagsinuse 1600.395362 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15918262 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11449 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1390.362652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.893985 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781687 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781687 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.395362 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781443 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781443 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 753 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 943 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 31871855 # Number of tag accesses -system.cpu.icache.tags.data_accesses 31871855 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 15915792 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15915792 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15915792 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15915792 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15915792 # number of overall hits -system.cpu.icache.overall_hits::total 15915792 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14409 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14409 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14409 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14409 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14409 # number of overall misses -system.cpu.icache.overall_misses::total 14409 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 447639000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 447639000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 447639000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 447639000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 447639000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 447639000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15930201 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15930201 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15930201 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15930201 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15930201 # 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31066.625026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31066.625026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31066.625026 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 446 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 31876835 # Number of tag accesses +system.cpu.icache.tags.data_accesses 31876835 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 15918262 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15918262 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15918262 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15918262 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15918262 # number of overall hits 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of overall miss cycles +system.cpu.icache.overall_miss_latency::total 508617000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15932693 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15932693 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15932693 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15932693 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15932693 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15932693 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000906 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000906 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000906 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000906 # 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-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29476.863978 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29476.863978 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29476.863978 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29476.863978 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33078.427948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33078.427948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33078.427948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33078.427948 # average overall mshr miss latency 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accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 9511 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 9511 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1729 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1729 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11454 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 11454 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11450 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 11450 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 516 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 516 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11454 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 11450 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13699 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11454 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13695 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11450 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13699 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 13695 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984962 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.984962 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.267330 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.267330 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.267336 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.267336 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.895349 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.895349 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267330 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267336 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964365 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.381561 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267330 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.381599 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267336 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.381561 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78666.764533 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78666.764533 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75775.146963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75775.146963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85606.060606 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85606.060606 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77586.187105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77586.187105 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.381599 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102333.529066 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102333.529066 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89244.691277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89244.691277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100559.523810 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100559.523810 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89244.691277 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101954.965358 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94510.237275 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89244.691277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101954.965358 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94510.237275 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -931,122 +941,122 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1703 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1703 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3062 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3062 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3061 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3061 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 462 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 462 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3062 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3061 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5227 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5226 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3061 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 116939500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 116939500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 201403500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 201403500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34930000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34930000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 201403500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151869500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 353273000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 201403500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151869500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 353273000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 5226 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 157244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 242568000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 242568000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41838500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41838500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 242568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 199082500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 441650500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 242568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 199082500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 441650500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984962 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267330 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267336 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.895349 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.895349 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.381561 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.381599 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.381561 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68666.764533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68666.764533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65775.146963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65775.146963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75606.060606 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75606.060606 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 23372 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9673 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.381599 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92333.529066 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92333.529066 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79244.691277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79244.691277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90559.523810 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90559.523810 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79244.691277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91954.965358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84510.237275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79244.691277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91954.965358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84510.237275 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 23364 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9669 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 11965 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9511 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1729 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1729 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11450 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 516 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32422 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32410 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 37070 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 37058 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341440 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1492544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1492032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 13699 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13695 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13699 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13695 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13699 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21309000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13695 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21301000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17179500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17173500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5227 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 5226 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3524 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3523 # Transaction distribution system.membus.trans_dist::ReadExReq 1703 # Transaction distribution system.membus.trans_dist::ReadExResp 1703 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3524 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3523 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5227 # Request fanout histogram +system.membus.snoop_fanout::samples 5226 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5227 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5226 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5227 # Request fanout histogram -system.membus.reqLayer0.occupancy 6278000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5226 # Request fanout histogram +system.membus.reqLayer0.occupancy 6271000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27461750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27424000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini index cdcb110c1..701cef29f 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout index 90ea58e8e..862c8292b 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:40:38 -gem5 executing on e108600-lin, pid 23114 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:49:48 +gem5 executing on e108600-lin, pid 17449 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/arm/linux/minor-timing Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav @@ -26,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 132485848500 because target called exit() +122 123 124 Exiting @ tick 132538562500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 9382954d5..26e7200e9 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132488 # Number of seconds simulated -sim_ticks 132487590500 # Number of ticks simulated -final_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132539 # Number of seconds simulated +sim_ticks 132538562500 # Number of ticks simulated +final_tick 132538562500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200266 # Simulator instruction rate (inst/s) -host_op_rate 211113 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153975874 # Simulator tick rate (ticks/s) -host_mem_usage 275560 # Number of bytes of host memory used -host_seconds 860.44 # Real time elapsed on the host +host_inst_rate 171463 # Simulator instruction rate (inst/s) +host_op_rate 180750 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131881088 # Simulator tick rate (ticks/s) +host_mem_usage 273644 # Number of bytes of host memory used +host_seconds 1004.99 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247552 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1043017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 824756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1867773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 824756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1867773 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3868 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 132487495500 # Total gap between requests +system.physmem.totGap 132538461500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation -system.physmem.totQLat 28381250 # Total ticks spent queuing -system.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 265.103448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.439776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.287318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 274 29.53% 29.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 366 39.44% 68.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 89 9.59% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.14% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24 2.59% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 19 2.05% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.94% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.94% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 63 6.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 928 # Bytes accessed per row activation +system.physmem.totQLat 84421250 # Total ticks spent queuing +system.physmem.totMemAccLat 156946250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst +system.physmem.avgQLat 21825.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 40575.56 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s @@ -217,56 +217,66 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2936 # Number of row buffer hits during reads +system.physmem.readRowHits 2935 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34252196.35 # Average gap between requests -system.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 34265372.67 # Average gap between requests +system.physmem.pageHitRate 75.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2977380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1582515 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 14822640 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.825360 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states -system.physmem_0.memoryStateTime::REF 4423900000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 159806400.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56564520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6779040 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 507399750 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 193240800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 31407910590 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 32351114145 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.088313 # Core power per rank (mW) +system.physmem_0.totalIdleTime 132395468250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 11004000 # Time in different power states +system.physmem_0.memoryStateTime::REF 67828000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 130780838250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 503202000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 62983500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1112706750 # Time in different power states +system.physmem_1.actEnergy 3684240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1939245 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 12794880 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.826698 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states -system.physmem_1.memoryStateTime::REF 4423900000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 49693795 # Number of BP lookups -system.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted +system.physmem_1.refreshEnergy 142596480.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 50045430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 5323200 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 514216380 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 148467840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 31429438665 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 32308536150 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.767063 # Core power per rank (mW) +system.physmem_1.totalIdleTime 132414854750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 7934000 # Time in different power states +system.physmem_1.memoryStateTime::REF 60464000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 130900584250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 386668500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 55249000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1127662750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 49693791 # Number of BP lookups +system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 264975181 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 265077125 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.537712 # CPI: cycles per instruction -system.cpu.ipc 0.650317 # IPC: instructions per cycle +system.cpu.cpi 1.538304 # CPI: cycles per instruction +system.cpu.ipc 0.650067 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction @@ -432,62 +442,62 @@ system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction -system.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked -system.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 256741537 # Number of cycles that the object actually ticked +system.cpu.idleCycles 8335588 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.587934 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40755397 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22504.360574 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.587934 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336569 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336569 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362636 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362636 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362633 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362633 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits -system.cpu.dcache.overall_hits::total 40710587 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40710121 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40710121 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40710583 # number of overall hits +system.cpu.dcache.overall_hits::total 40710583 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1651 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1651 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1654 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1654 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2402 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2402 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2403 # number of overall misses -system.cpu.dcache.overall_misses::total 2403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2405 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2405 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2406 # number of overall misses +system.cpu.dcache.overall_misses::total 2406 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64864500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64864500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 147460000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 147460000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 212324500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 212324500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 212324500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 212324500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +506,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses @@ -510,14 +520,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86370.838881 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 86370.838881 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89153.567110 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89153.567110 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 88284.615385 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 88284.615385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 88247.921862 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 88247.921862 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,12 +538,12 @@ system.cpu.dcache.writebacks::writebacks 16 # nu system.cpu.dcache.writebacks::total 16 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 552 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 552 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 592 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 592 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 592 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 592 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 555 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 555 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 595 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 595 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 595 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 595 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses @@ -544,16 +554,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61185500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 61185500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 100181500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 100181500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 77000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 77000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161367000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161367000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161444000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161444000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -564,72 +574,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86055.555556 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86055.555556 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91156.960874 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91156.960874 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 77000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 77000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89153.038674 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89153.038674 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89146.327996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89146.327996 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2864 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 70941364 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1424.889067 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 70941363 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15213.674459 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 15213.674244 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.889067 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695747 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695747 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 491 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 131 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 141896719 # Number of tag accesses -system.cpu.icache.tags.data_accesses 141896719 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 70941364 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 70941364 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 70941364 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 70941364 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 70941364 # number of overall hits -system.cpu.icache.overall_hits::total 70941364 # number of overall hits +system.cpu.icache.tags.tag_accesses 141896717 # Number of tag accesses +system.cpu.icache.tags.data_accesses 141896717 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 70941363 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 70941363 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 70941363 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 70941363 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 70941363 # number of overall hits +system.cpu.icache.overall_hits::total 70941363 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 4664 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4664 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 4664 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses system.cpu.icache.overall_misses::total 4664 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 70946028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 70946028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 70946028 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 70946028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 70946028 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 70946028 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 236552500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 236552500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 236552500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 236552500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 236552500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 236552500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 70946027 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 70946027 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 70946027 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 70946027 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 70946027 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 70946027 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50718.803602 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50718.803602 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50718.803602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50718.803602 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,46 +654,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4664 system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231889500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 231889500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231889500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 231889500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231889500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 231889500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49719.018010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49719.018010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2835.336724 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.040521 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.638236 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.698487 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.040518 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.086528 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 367 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits @@ -712,18 +722,18 @@ system.cpu.l2cache.demand_misses::total 3885 # nu system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85311000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 85311000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 299285500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98447500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 98447500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198239500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 198239500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 59270000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 59270000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 198239500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 157717500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 355957000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 198239500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 157717500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 355957000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses) @@ -752,18 +762,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.600000 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77036.164736 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77036.164736 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90236.021998 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90236.021998 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91692.645698 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91692.645698 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93781.645570 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93781.645570 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 91623.423423 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 91623.423423 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -792,18 +802,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3869 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87537500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87537500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176566000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176566000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 51432500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 51432500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176566000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138970000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 315536000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176566000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138970000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 315536000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses @@ -816,25 +826,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80236.021998 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80236.021998 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81705.691809 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81705.691809 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83358.995138 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83358.995138 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution @@ -874,7 +884,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2777 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution @@ -895,9 +905,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3868 # Request fanout histogram -system.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20568250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 86715fd27..3c414751d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 6247d8422..8c06d056d 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -3,11 +3,13 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:31:02 -gem5 executing on e108600-lin, pid 12562 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:43:01 +gem5 executing on e108600-lin, pid 17342 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 84937723500 because target called exit() +122 123 124 Exiting @ tick 86053034000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 834ad990c..04ea23c2f 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085052 # Number of seconds simulated -sim_ticks 85051506000 # Number of ticks simulated -final_tick 85051506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.086053 # Number of seconds simulated +sim_ticks 86053034000 # Number of ticks simulated +final_tick 86053034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137318 # Simulator instruction rate (inst/s) -host_op_rate 144756 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67782320 # Simulator tick rate (ticks/s) -host_mem_usage 272616 # Number of bytes of host memory used -host_seconds 1254.77 # Real time elapsed on the host +host_inst_rate 114393 # Simulator instruction rate (inst/s) +host_op_rate 120589 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57131119 # Simulator tick rate (ticks/s) +host_mem_usage 270696 # Number of bytes of host memory used +host_seconds 1506.24 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 651584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 192256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory -system.physmem.bytes_read::total 914880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 651584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 651584 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 10181 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3004 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14295 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 7661052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2260466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 835259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10756776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7661052 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7661052 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7661052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2260466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 835259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10756776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 14295 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 652224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 193472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 70848 # Number of bytes read from this memory +system.physmem.bytes_read::total 916544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 652224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 652224 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10191 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3023 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1107 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14321 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7579326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2248288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 823306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10650920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7579326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7579326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7579326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2248288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 823306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10650920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14321 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 14295 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14321 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 914880 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 916544 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 914880 # Total read bytes from the system interface side +system.physmem.bytesReadSys 916544 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1374 # Per bank write bursts -system.physmem.perBankRdBursts::1 495 # Per bank write bursts -system.physmem.perBankRdBursts::2 5094 # Per bank write bursts -system.physmem.perBankRdBursts::3 807 # Per bank write bursts -system.physmem.perBankRdBursts::4 2274 # Per bank write bursts +system.physmem.perBankRdBursts::0 1378 # Per bank write bursts +system.physmem.perBankRdBursts::1 501 # Per bank write bursts +system.physmem.perBankRdBursts::2 5089 # Per bank write bursts +system.physmem.perBankRdBursts::3 804 # Per bank write bursts +system.physmem.perBankRdBursts::4 2285 # Per bank write bursts system.physmem.perBankRdBursts::5 424 # Per bank write bursts system.physmem.perBankRdBursts::6 384 # Per bank write bursts -system.physmem.perBankRdBursts::7 621 # Per bank write bursts +system.physmem.perBankRdBursts::7 628 # Per bank write bursts system.physmem.perBankRdBursts::8 270 # Per bank write bursts -system.physmem.perBankRdBursts::9 230 # Per bank write bursts +system.physmem.perBankRdBursts::9 231 # Per bank write bursts system.physmem.perBankRdBursts::10 354 # Per bank write bursts system.physmem.perBankRdBursts::11 348 # Per bank write bursts -system.physmem.perBankRdBursts::12 319 # Per bank write bursts +system.physmem.perBankRdBursts::12 321 # Per bank write bursts system.physmem.perBankRdBursts::13 267 # Per bank write bursts -system.physmem.perBankRdBursts::14 239 # Per bank write bursts -system.physmem.perBankRdBursts::15 795 # Per bank write bursts +system.physmem.perBankRdBursts::14 240 # Per bank write bursts +system.physmem.perBankRdBursts::15 797 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85051447500 # Total gap between requests +system.physmem.totGap 86052975500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 14295 # Read request sizes (log2) +system.physmem.readPktSize::6 14321 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,18 +95,18 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1014 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -191,86 +191,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8758 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.242978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 83.732821 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 121.093987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6415 73.25% 73.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1879 21.45% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 191 2.18% 96.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 97 1.11% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 0.40% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 31 0.35% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21 0.24% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 0.19% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 72 0.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8758 # Bytes accessed per row activation -system.physmem.totQLat 205669486 # Total ticks spent queuing -system.physmem.totMemAccLat 473700736 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 71475000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14387.51 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 8480 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 108.022642 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.441459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 123.287712 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5899 69.56% 69.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2101 24.78% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 209 2.46% 96.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 89 1.05% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 41 0.48% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 0.42% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 15 0.18% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13 0.15% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 77 0.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8480 # Bytes accessed per row activation +system.physmem.totQLat 1499260235 # Total ticks spent queuing +system.physmem.totMemAccLat 1767778985 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71605000 # Total ticks spent in databus transfers +system.physmem.avgQLat 104689.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33137.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 10.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 123439.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 10.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 10.76 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 10.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.08 # Data bus utilization in percentage system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5530 # Number of row buffer hits during reads +system.physmem.readRowHits 5837 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 38.68 # Row buffer hit rate for reads +system.physmem.readRowHitRate 40.76 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 5949734.00 # Average gap between requests -system.physmem.pageHitRate 38.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 56571480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 30867375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 89442600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 6008866.39 # Average gap between requests +system.physmem.pageHitRate 40.76 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 51557940 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 27392310 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 82060020 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 17335593540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 35823020250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 58890496125 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.426384 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 59484367239 # Time in different power states -system.physmem_0.memoryStateTime::REF 2839980000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22725351261 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9616320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5247000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21801000 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 5180800560.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1120628550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 275264640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12259963560 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8345872320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9276913815 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 36622770765 # Total energy per rank (pJ) +system.physmem_0.averagePower 425.583720 # Core power per rank (mW) +system.physmem_0.totalIdleTime 82871785017 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 531109000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2203210000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34253599252 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21734056085 # Time in different power states +system.physmem_0.memoryStateTime::ACT 445220983 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 26885838680 # Time in different power states +system.physmem_1.actEnergy 9017820 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4789290 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20191920 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4216606920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 47330903250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 57139175370 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.834595 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 78723898183 # Time in different power states -system.physmem_1.memoryStateTime::REF 2839980000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3485604317 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85633597 # Number of BP lookups -system.cpu.branchPred.condPredicted 68181299 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5935035 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39958046 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38197568 # Number of BTB hits +system.physmem_1.refreshEnergy 882623040.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 198112620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 50847360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1971627720 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1393669440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18810725700 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23341907430 # Total energy per rank (pJ) +system.physmem_1.averagePower 271.250252 # Core power per rank (mW) +system.physmem_1.totalIdleTime 85485463257 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 101360000 # Time in different power states +system.physmem_1.memoryStateTime::REF 375610000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 77532398500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3629358146 # Time in different power states +system.physmem_1.memoryStateTime::ACT 90573993 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 4323733361 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85625838 # Number of BP lookups +system.cpu.branchPred.condPredicted 68176243 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5935432 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39943176 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38184524 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.594184 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3683467 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81914 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681978 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 654112 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 27866 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40296 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.597115 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683485 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81916 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681521 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 653387 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 28134 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40344 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,131 +401,131 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 170103013 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 172106069 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5682904 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347166765 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85633597 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42535147 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 157608501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11884039 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2048 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5685351 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347171735 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85625838 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42521396 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158200265 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11884759 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 3989 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78333693 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18018 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169239484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.146393 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.050401 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 4307 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78326471 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18089 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169836333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.138878 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.056220 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17572638 10.38% 10.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30072408 17.77% 28.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31601234 18.67% 46.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 89993204 53.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18169241 10.70% 10.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30071574 17.71% 28.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31598899 18.61% 47.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89996619 52.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169239484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.503422 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.040921 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17519961 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17356982 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121861075 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6734206 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5767260 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11064637 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189821 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 304987544 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27243895 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5767260 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37487022 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8574296 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 598391 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108353196 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8459319 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277412346 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13179472 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3059617 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 843440 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2298708 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 38369 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 27077 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481431446 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187749796 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296450503 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005240 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169836333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.497518 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.017196 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17522714 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17948295 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121866676 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6730979 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5767669 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11064280 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189793 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304996623 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27241409 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5767669 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37489750 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8834769 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 601523 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108355832 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8786790 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277419061 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13180458 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3061814 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 846087 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2626546 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 39334 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27085 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481448286 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1187772528 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296460965 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3003847 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188454517 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23636 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23644 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13356506 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33916395 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14406588 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2541453 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1809916 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263792468 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45987 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214404594 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5189732 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82202501 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216956580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 771 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169239484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.266871 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.018138 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 188471357 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23624 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13352846 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33915531 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14406995 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2538352 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1801972 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263797881 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45980 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214410891 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5187410 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82207907 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 216953193 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 764 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169836333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.262456 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.019138 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52525006 31.04% 31.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 35947009 21.24% 52.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65510390 38.71% 90.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13639375 8.06% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570056 0.93% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47432 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 216 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 53122752 31.28% 31.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35940807 21.16% 52.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65514665 38.58% 91.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13639448 8.03% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571104 0.93% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47348 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 209 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169239484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169836333 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35663808 66.17% 66.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153282 0.28% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35657368 66.16% 66.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153250 0.28% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34308 0.06% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14056089 26.08% 92.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3953676 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35732 0.07% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 954 0.00% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34277 0.06% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14055726 26.08% 92.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3956441 7.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 166984371 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919276 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166991462 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919191 0.43% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued @@ -534,91 +544,91 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33016 0.02% 78.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460481 0.21% 78.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206631 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165181 0.08% 78.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245709 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460330 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206622 0.10% 78.87% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31870339 14.86% 93.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13371616 6.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31869240 14.86% 93.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13372180 6.24% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214404594 # Type of FU issued -system.cpu.iq.rate 1.260440 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53899365 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251391 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653186184 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344036614 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204245973 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3951585 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2011286 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806392 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266171590 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2132369 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1599233 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214410891 # Type of FU issued +system.cpu.iq.rate 1.245807 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53895257 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251364 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653788467 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344049655 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204252570 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952315 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2009022 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806352 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266172688 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133460 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1598637 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6020251 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7425 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7087 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1761954 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6019387 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7380 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7051 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1762361 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25499 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25560 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 770 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5767260 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5621824 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 63176 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263858489 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5767669 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5624657 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 173600 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263863986 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33916395 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14406588 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23579 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3874 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56135 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7087 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3147809 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3246868 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6394677 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207120469 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30635063 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7284125 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33915531 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14406995 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23572 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3856 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 166551 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7051 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3148917 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246700 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6395617 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207126816 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30634090 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7284075 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20034 # number of nop insts executed -system.cpu.iew.exec_refs 43773548 # number of memory reference insts executed -system.cpu.iew.exec_branches 44851099 # Number of branches executed -system.cpu.iew.exec_stores 13138485 # Number of stores executed -system.cpu.iew.exec_rate 1.217618 # Inst execution rate -system.cpu.iew.wb_sent 206362307 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206052365 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129396792 # num instructions producing a value -system.cpu.iew.wb_consumers 221653711 # num instructions consuming a value -system.cpu.iew.wb_rate 1.211339 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583779 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68665439 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20125 # number of nop insts executed +system.cpu.iew.exec_refs 43772682 # number of memory reference insts executed +system.cpu.iew.exec_branches 44853086 # Number of branches executed +system.cpu.iew.exec_stores 13138592 # Number of stores executed +system.cpu.iew.exec_rate 1.203484 # Inst execution rate +system.cpu.iew.wb_sent 206368979 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206058922 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129395738 # num instructions producing a value +system.cpu.iew.wb_consumers 221650226 # num instructions consuming a value +system.cpu.iew.wb_rate 1.197279 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583783 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68671574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5760276 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 157944348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.150091 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.652266 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5760722 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158539716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.145772 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.650496 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73354007 46.44% 46.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41142542 26.05% 72.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22532573 14.27% 86.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9515365 6.02% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3551587 2.25% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2142504 1.36% 96.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1329210 0.84% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1010049 0.64% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3366511 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73944910 46.64% 46.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41143540 25.95% 72.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22534900 14.21% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9516225 6.00% 92.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3553894 2.24% 95.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2144247 1.35% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1327660 0.84% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1009164 0.64% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3365176 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 157944348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158539716 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,83 +674,83 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3366511 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 404888417 # The number of ROB reads -system.cpu.rob.rob_writes 511940612 # The number of ROB writes -system.cpu.timesIdled 9843 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 863529 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3365176 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 405491255 # The number of ROB reads +system.cpu.rob.rob_writes 511954468 # The number of ROB writes +system.cpu.timesIdled 10012 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2269736 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.987232 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.987232 # CPI: Total CPI of All Threads -system.cpu.ipc 1.012933 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.012933 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218721236 # number of integer regfile reads -system.cpu.int_regfile_writes 114166498 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904044 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441835 # number of floating regfile writes -system.cpu.cc_regfile_reads 708181937 # number of cc regfile reads -system.cpu.cc_regfile_writes 229500026 # number of cc regfile writes -system.cpu.misc_regfile_reads 57441519 # number of misc regfile reads +system.cpu.cpi 0.998857 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.998857 # CPI: Total CPI of All Threads +system.cpu.ipc 1.001144 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.001144 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218726711 # number of integer regfile reads +system.cpu.int_regfile_writes 114168819 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904003 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441695 # number of floating regfile writes +system.cpu.cc_regfile_reads 708199076 # number of cc regfile reads +system.cpu.cc_regfile_writes 229511616 # number of cc regfile writes +system.cpu.misc_regfile_reads 57440558 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72593 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.410345 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41032184 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73105 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.277396 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 509673500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.410345 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998848 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998848 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72579 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.404028 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41032024 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73091 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.382715 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 516933500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.404028 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998836 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998836 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82362697 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82362697 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28645946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28645946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82362375 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82362375 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28645802 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28645802 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341304 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341304 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40987266 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40987266 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40987630 # number of overall hits -system.cpu.dcache.overall_hits::total 40987630 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89269 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89269 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40987106 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40987106 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40987470 # number of overall hits +system.cpu.dcache.overall_hits::total 40987470 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89259 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89259 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22983 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22983 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112236 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112236 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112352 # number of overall misses -system.cpu.dcache.overall_misses::total 112352 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1192862000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1192862000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 244207999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 244207999 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2309000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1437069999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1437069999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1437069999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1437069999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28735215 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28735215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 112242 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112242 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112358 # number of overall misses +system.cpu.dcache.overall_misses::total 112358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1986737500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1986737500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 247540999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 247540999 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2234278499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2234278499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 2234278499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2234278499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28735061 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28735061 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) @@ -749,14 +759,14 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41099502 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41099502 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41099982 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41099982 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003107 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003107 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41099348 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41099348 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41099828 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41099828 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003106 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003106 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001859 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001859 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses @@ -765,54 +775,54 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13362.555870 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13362.555870 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10632.995123 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10632.995123 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8880.769231 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8880.769231 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12804.002272 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12804.002272 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12790.782532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12790.782532 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10626 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22258.119629 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22258.119629 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10770.613018 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10770.613018 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19905.904198 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19905.904198 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19885.353059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19885.353059 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11288 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 868 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.241935 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72593 # number of writebacks -system.cpu.dcache.writebacks::total 72593 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24834 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24834 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14410 # 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-system.cpu.dcache.overall_mshr_misses::total 73105 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 724757000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 724757000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85765499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85765499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 963000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 963000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 810522499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 810522499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 811485499 # number of overall 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to valid blocks. +system.cpu.icache.tags.sampled_refs 54124 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1446.100233 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 85282294500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.587809 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997242 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997242 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id 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average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167481.071008 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 190882.750660 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 172844.987904 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167481.071008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 190882.750660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 172844.987904 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2014 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 2014 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 236 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 236 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10181 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10181 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2768 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2768 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10181 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3004 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 13185 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10181 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3004 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2014 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15199 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 66910636 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 66910636 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17183500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17183500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 720935500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 720935500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 202978500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 202978500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 720935500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 220162000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 941097500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 720935500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 220162000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66910636 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1008008136 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2057 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 2057 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 238 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 238 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10191 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10191 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2785 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2785 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10191 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3023 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 13214 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10191 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3023 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2057 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15271 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 97518621 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 97518621 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 18660000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 18660000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1645631000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1645631000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 541204500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 541204500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1645631000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 559864500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2205495500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1645631000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 559864500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 97518621 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2303014121 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027365 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027365 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188015 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.042927 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.042927 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041092 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103611 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041092 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188286 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188286 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043200 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043200 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188286 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041359 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103871 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188286 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041359 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.119437 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33222.758689 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72811.440678 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72811.440678 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70811.855417 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70811.855417 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73330.382948 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73330.382948 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71376.374668 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66320.687940 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253485 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126250 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 904 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 903 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.120040 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47408.177443 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78403.361345 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78403.361345 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161478.853891 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161478.853891 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194328.366248 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194328.366248 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161478.853891 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185201.620906 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166905.970940 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161478.853891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185201.620906 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 150809.647109 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253407 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126211 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10475 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 950 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 949 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118630 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54150 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64481 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218803 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380739 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6898304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9324672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16222976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2352 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 118592 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64697 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61494 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54125 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64468 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380622 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6895104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9322880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16217984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2394 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 129607 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.087812 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283049 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 129610 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.088311 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283775 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118227 91.22% 91.22% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11379 8.78% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118165 91.17% 91.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11444 8.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 129607 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 252972500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 129610 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252894500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81228989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81192487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109661492 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109641490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 14295 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 10463 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 14321 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10482 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 14059 # Transaction distribution -system.membus.trans_dist::ReadExReq 236 # Transaction distribution -system.membus.trans_dist::ReadExResp 236 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 14059 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28590 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28590 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 914880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 914880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14082 # Transaction distribution +system.membus.trans_dist::ReadExReq 238 # Transaction distribution +system.membus.trans_dist::ReadExResp 238 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14083 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28641 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28641 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 916480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 14295 # Request fanout histogram +system.membus.snoop_fanout::samples 14321 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 14295 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14321 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 14295 # Request fanout histogram -system.membus.reqLayer0.occupancy 18052130 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14321 # Request fanout histogram +system.membus.reqLayer0.occupancy 18093154 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 77159307 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77218560 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 4ca9409ac..8d26638e4 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -179,7 +179,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -552,7 +552,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -756,6 +756,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -767,7 +768,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -775,29 +776,36 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -817,6 +825,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -848,9 +857,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 6416a69a9..99d577e0b 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18548 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:09:02 +gem5 executing on e108600-lin, pid 17639 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav @@ -20,7 +20,6 @@ Authors: Carl Sechen, Bill Swartz info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. - 1 2 3 4 5 6 7 8 9 10 11 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. @@ -9804,7 +9803,8 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. - 12 13 14 15 +info: Increasing stack size by one page. + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 @@ -9812,4 +9812,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 103324153500 because target called exit() +122 123 124 Exiting @ tick 103189362000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index c2d15923a..f0c12dca0 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103278 # Number of seconds simulated -sim_ticks 103278421500 # Number of ticks simulated -final_tick 103278421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.103189 # Number of seconds simulated +sim_ticks 103189362000 # Number of ticks simulated +final_tick 103189362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68420 # Simulator instruction rate (inst/s) -host_op_rate 114678 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53503682 # Simulator tick rate (ticks/s) -host_mem_usage 309068 # Number of bytes of host memory used -host_seconds 1930.31 # Real time elapsed on the host +host_inst_rate 73255 # Simulator instruction rate (inst/s) +host_op_rate 122783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57235650 # Simulator tick rate (ticks/s) +host_mem_usage 306480 # Number of bytes of host memory used +host_seconds 1802.89 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory -system.physmem.bytes_read::total 362688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5667 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2248214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1263536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3511750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2248214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2248214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2248214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1263536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3511750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5668 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 232704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130112 # Number of bytes read from this memory +system.physmem.bytes_read::total 362816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 232704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 232704 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2033 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5669 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2255116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1260905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3516021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2255116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2255116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2255116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1260905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3516021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5669 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5668 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5669 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 362752 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 362816 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 362752 # Total read bytes from the system interface side +system.physmem.bytesReadSys 362816 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 314 # Per bank write bursts -system.physmem.perBankRdBursts::1 385 # Per bank write bursts -system.physmem.perBankRdBursts::2 471 # Per bank write bursts -system.physmem.perBankRdBursts::3 359 # Per bank write bursts -system.physmem.perBankRdBursts::4 360 # Per bank write bursts -system.physmem.perBankRdBursts::5 334 # Per bank write bursts -system.physmem.perBankRdBursts::6 420 # Per bank write bursts -system.physmem.perBankRdBursts::7 393 # Per bank write bursts -system.physmem.perBankRdBursts::8 389 # Per bank write bursts +system.physmem.perBankRdBursts::0 309 # Per bank write bursts +system.physmem.perBankRdBursts::1 384 # Per bank write bursts +system.physmem.perBankRdBursts::2 476 # Per bank write bursts +system.physmem.perBankRdBursts::3 363 # Per bank write bursts +system.physmem.perBankRdBursts::4 357 # Per bank write bursts +system.physmem.perBankRdBursts::5 335 # Per bank write bursts +system.physmem.perBankRdBursts::6 419 # Per bank write bursts +system.physmem.perBankRdBursts::7 395 # Per bank write bursts +system.physmem.perBankRdBursts::8 387 # Per bank write bursts system.physmem.perBankRdBursts::9 296 # Per bank write bursts -system.physmem.perBankRdBursts::10 257 # Per bank write bursts -system.physmem.perBankRdBursts::11 272 # Per bank write bursts -system.physmem.perBankRdBursts::12 232 # Per bank write bursts -system.physmem.perBankRdBursts::13 487 # Per bank write bursts -system.physmem.perBankRdBursts::14 416 # Per bank write bursts -system.physmem.perBankRdBursts::15 283 # Per bank write bursts +system.physmem.perBankRdBursts::10 260 # Per bank write bursts +system.physmem.perBankRdBursts::11 268 # Per bank write bursts +system.physmem.perBankRdBursts::12 228 # Per bank write bursts +system.physmem.perBankRdBursts::13 486 # Per bank write bursts +system.physmem.perBankRdBursts::14 420 # Per bank write bursts +system.physmem.perBankRdBursts::15 286 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 103278386000 # Total gap between requests +system.physmem.totGap 103189107000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5668 # Read request sizes (log2) +system.physmem.readPktSize::6 5669 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,321 +187,331 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1276 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 283.335423 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.570090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 315.354372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 562 44.04% 44.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 260 20.38% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 126 9.87% 74.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 5.09% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 38 2.98% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 4.08% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.51% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.96% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 116 9.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1276 # Bytes accessed per row activation -system.physmem.totQLat 44968750 # Total ticks spent queuing -system.physmem.totMemAccLat 151243750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 28340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7933.79 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1243 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.012068 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.006967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.689818 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 565 45.45% 45.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 237 19.07% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95 7.64% 72.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 5.23% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 45 3.62% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 4.59% 85.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 29 2.33% 87.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 1.69% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 129 10.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1243 # Bytes accessed per row activation +system.physmem.totQLat 180648250 # Total ticks spent queuing +system.physmem.totMemAccLat 286942000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 31865.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26683.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 50615.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4387 # Number of row buffer hits during reads +system.physmem.readRowHits 4421 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 18221310.16 # Average gap between requests -system.physmem.pageHitRate 77.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5677560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3097875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 23649600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 18202347.33 # Average gap between requests +system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5333580 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2823480 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 21691320 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3123252585 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 59226559500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 69127776960 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.342795 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 98524507750 # Time in different power states -system.physmem_0.memoryStateTime::REF 3448640000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1303957250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3969000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2165625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20412600 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 286422240.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 93806610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 15765120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 717579270 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 394813440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 24141432120 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 25679671980 # Total energy per rank (pJ) +system.physmem_0.averagePower 248.859682 # Core power per rank (mW) +system.physmem_0.totalIdleTime 102941166250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 30119500 # Time in different power states +system.physmem_0.memoryStateTime::REF 121808000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 100340787250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1028168000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 94814000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1573665250 # Time in different power states +system.physmem_1.actEnergy 3577140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1893705 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18785340 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3000772125 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 59333991750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 69106850940 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.140248 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 98704275500 # Time in different power states -system.physmem_1.memoryStateTime::REF 3448640000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1124404000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40909998 # Number of BP lookups -system.cpu.branchPred.condPredicted 40909998 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6747980 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 35338690 # Number of BTB lookups +system.physmem_1.refreshEnergy 224343600.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72770760 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12467520 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 571365720 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 300199680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 24277951200 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 25483354665 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.957187 # Core power per rank (mW) +system.physmem_1.totalIdleTime 102997073250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 23820000 # Time in different power states +system.physmem_1.memoryStateTime::REF 95422000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 100962546500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 781772000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 72828000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1252973500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40834752 # Number of BP lookups +system.cpu.branchPred.condPredicted 40834752 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6720926 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 35301077 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3198330 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 606499 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 35338690 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 9879284 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 25459406 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 5040736 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 3198104 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 606453 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 35301077 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9875363 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 25425714 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 5011557 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 206556844 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 206378725 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 46378865 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 420308215 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40909998 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13077614 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 152415438 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14966481 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 135 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 72789 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 564 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 41283191 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1528436 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 206357094 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.419964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.660932 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 46270336 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 419359791 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40834752 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13073467 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 152339601 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14895691 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 89 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 73704 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 808 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 184 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41191275 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1518616 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 206138472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.415591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.660484 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 99044157 48.00% 48.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5139433 2.49% 50.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5380650 2.61% 53.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5336666 2.59% 55.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6016483 2.92% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5851353 2.84% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5736237 2.78% 64.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4733991 2.29% 66.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 69118124 33.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 99063302 48.06% 48.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5137465 2.49% 50.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5366260 2.60% 53.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5330020 2.59% 55.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6010905 2.92% 58.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5824389 2.83% 61.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5722044 2.78% 64.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4745811 2.30% 66.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68938276 33.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 206357094 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.198057 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.034831 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32325248 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86371056 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 62511253 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17666297 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7483240 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 591444337 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7483240 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42110583 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46566289 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29410 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68967744 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41199828 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 552624215 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1533 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36277086 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4842177 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 151976 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 630066400 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1487530571 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 975657611 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 15077279 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 206138472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.197863 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.031991 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32237214 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86447407 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 62317142 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17688864 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7447845 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 590237823 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7447845 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42013779 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46504501 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 31211 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68811152 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41329984 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 551593859 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1410 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36393589 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4822156 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 169929 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 628796373 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1484193525 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 973498992 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 15084169 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 370636950 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2363 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2376 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89140950 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128894590 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 45939948 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 77227738 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25186602 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 490698604 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 59973 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 338566221 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1098463 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 269395193 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 527209931 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 58728 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 206357094 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.640681 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.805896 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 369366923 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2443 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2459 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89351866 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128676829 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45848779 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 77202780 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25186397 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 489944627 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 61663 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 338268196 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1105632 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 268642906 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 525336348 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 60418 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 206138472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.640976 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805234 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 73312584 35.53% 35.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46573584 22.57% 58.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32816576 15.90% 74.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20907210 10.13% 84.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15065478 7.30% 91.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8412685 4.08% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5234413 2.54% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2370472 1.15% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1664092 0.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 73134407 35.48% 35.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46607709 22.61% 58.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32815647 15.92% 74.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20883524 10.13% 84.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15044203 7.30% 91.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8407546 4.08% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5216740 2.53% 98.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2365929 1.15% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1662767 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 206357094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 206138472 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 762770 19.47% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2718793 69.40% 88.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 436106 11.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 759085 19.35% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2731626 69.64% 88.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 432034 11.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211777 0.36% 0.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 216613901 63.98% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 799985 0.24% 64.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7047582 2.08% 66.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1810682 0.53% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 84424015 24.94% 92.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26658279 7.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211760 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 216459489 63.99% 64.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800418 0.24% 64.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7047773 2.08% 66.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1809637 0.53% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 84315938 24.93% 92.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26623181 7.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 338566221 # Type of FU issued -system.cpu.iq.rate 1.639095 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3917669 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011571 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 880328489 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 745561228 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 316131833 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8177179 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 15427221 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3556889 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 337169115 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4102998 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18179072 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 338268196 # Type of FU issued +system.cpu.iq.rate 1.639065 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3922745 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011597 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 879521716 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 744046350 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 315909602 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8181525 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15431147 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3556535 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 336873543 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4105638 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18155877 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 72245003 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55572 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 872144 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 25424231 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 72027242 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 55091 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 864575 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25333062 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50651 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50542 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 27 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7483240 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35798970 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 583606 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 490758577 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1261619 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128894590 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 45939948 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 21909 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 539997 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 37637 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 872144 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1294345 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6884684 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8179029 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 326602378 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 80777118 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11963843 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7447845 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35704467 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 582987 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 490006290 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1248239 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128676829 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45848779 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22549 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 539423 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38394 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 864575 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1296720 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6850218 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8146938 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 326347367 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80684613 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11920829 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 106442155 # number of memory reference insts executed -system.cpu.iew.exec_branches 18940356 # Number of branches executed -system.cpu.iew.exec_stores 25665037 # Number of stores executed -system.cpu.iew.exec_rate 1.581174 # Inst execution rate -system.cpu.iew.wb_sent 322715986 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 319688722 # cumulative count of insts written-back -system.cpu.iew.wb_producers 256576217 # num instructions producing a value -system.cpu.iew.wb_consumers 435723594 # num instructions consuming a value -system.cpu.iew.wb_rate 1.547703 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588851 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 269420821 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 106316260 # number of memory reference insts executed +system.cpu.iew.exec_branches 18920718 # Number of branches executed +system.cpu.iew.exec_stores 25631647 # Number of stores executed +system.cpu.iew.exec_rate 1.581303 # Inst execution rate +system.cpu.iew.wb_sent 322480012 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 319466137 # cumulative count of insts written-back +system.cpu.iew.wb_producers 256417161 # num instructions producing a value +system.cpu.iew.wb_consumers 435540007 # num instructions consuming a value +system.cpu.iew.wb_rate 1.547961 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588734 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 268667644 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6753005 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 163742250 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.351901 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.936120 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6725958 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163655626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.352617 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.935975 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67180478 41.03% 41.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 54846489 33.50% 74.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13227508 8.08% 82.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10675855 6.52% 89.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5434961 3.32% 92.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3126709 1.91% 94.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1096647 0.67% 95.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1147781 0.70% 95.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7005822 4.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67077696 40.99% 40.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54856110 33.52% 74.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13235317 8.09% 82.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10672053 6.52% 89.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5439540 3.32% 92.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3134329 1.92% 94.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1088236 0.66% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1157500 0.71% 95.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6994845 4.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 163742250 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163655626 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -547,469 +557,469 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 7005822 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 647520633 # The number of ROB reads -system.cpu.rob.rob_writes 1024585644 # The number of ROB writes -system.cpu.timesIdled 2803 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199750 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6994845 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 646691809 # The number of ROB reads +system.cpu.rob.rob_writes 1022946396 # The number of ROB writes +system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 240253 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.563981 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.563981 # CPI: Total CPI of All Threads -system.cpu.ipc 0.639394 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.639394 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 524858514 # number of integer regfile reads -system.cpu.int_regfile_writes 289109549 # number of integer regfile writes -system.cpu.fp_regfile_reads 4527972 # number of floating regfile reads -system.cpu.fp_regfile_writes 3322072 # number of floating regfile writes -system.cpu.cc_regfile_reads 107078976 # number of cc regfile reads -system.cpu.cc_regfile_writes 65816113 # number of cc regfile writes -system.cpu.misc_regfile_reads 177007720 # number of misc regfile reads +system.cpu.cpi 1.562632 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.562632 # CPI: Total CPI of All Threads +system.cpu.ipc 0.639946 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.639946 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 524499390 # number of integer regfile reads +system.cpu.int_regfile_writes 288922915 # number of integer regfile writes +system.cpu.fp_regfile_reads 4524370 # number of floating regfile reads +system.cpu.fp_regfile_writes 3323309 # number of floating regfile writes +system.cpu.cc_regfile_reads 107020933 # number of cc regfile reads +system.cpu.cc_regfile_writes 65779043 # number of cc regfile writes +system.cpu.misc_regfile_reads 176790948 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 77 # number of replacements -system.cpu.dcache.tags.tagsinuse 1524.395872 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 82831685 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2117 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39126.917808 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 81 # number of replacements +system.cpu.dcache.tags.tagsinuse 1508.634180 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82760913 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2105 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39316.348219 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1524.395872 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.372167 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.372167 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2040 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 411 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1479 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 165670739 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 165670739 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 62317357 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 62317357 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513773 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513773 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 82831130 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 82831130 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 82831130 # number of overall hits -system.cpu.dcache.overall_hits::total 82831130 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1223 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1223 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1958 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1958 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3181 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3181 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3181 # number of overall misses -system.cpu.dcache.overall_misses::total 3181 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77985000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77985000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 124974000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 124974000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 202959000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 202959000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 202959000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 202959000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 62318580 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 62318580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1508.634180 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.368319 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.368319 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2024 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 423 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1459 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 165529197 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 165529197 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 62246604 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 62246604 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513664 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513664 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82760268 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82760268 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82760268 # number of overall hits +system.cpu.dcache.overall_hits::total 82760268 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1211 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1211 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2067 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2067 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3278 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3278 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3278 # number of overall misses +system.cpu.dcache.overall_misses::total 3278 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 109883500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 109883500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 137432000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 137432000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 247315500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 247315500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 247315500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 247315500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 62247815 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 62247815 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82834311 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82834311 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82834311 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82834311 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000095 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000095 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63765.331153 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63765.331153 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63827.374872 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63827.374872 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63803.520905 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63803.520905 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 403 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 82763546 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82763546 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82763546 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82763546 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000101 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000101 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 90737.819983 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 90737.819983 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66488.630866 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66488.630866 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75447.071385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75447.071385 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 307 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 143 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.777778 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 76.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 71.500000 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 622 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 622 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 8 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1950 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1950 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47286500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47286500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 122663000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 122663000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 169949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 169949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 169949500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 169949500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000095 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000095 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78679.700499 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78679.700499 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62904.102564 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62904.102564 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66620.736966 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66620.736966 # average overall mshr miss latency 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mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963173 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.535121 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65943.783069 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65943.783069 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67314.911797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67314.911797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76051.136364 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76051.136364 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18024 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7043 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 478 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1515 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1515 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3636 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3636 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 518 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 518 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3636 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2033 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5669 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3636 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2033 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5669 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110602500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110602500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 349163500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 349163500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 60126000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 60126000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 349163500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 170728500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 519892000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 349163500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 170728500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 519892000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995401 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995401 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.427111 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888508 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888508 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.533905 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.533905 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73004.950495 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73004.950495 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96029.565457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96029.565457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 116073.359073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 116073.359073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18313 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7194 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 597 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 9504 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 9638 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6489 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 61 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 8907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 599 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5178 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 29047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 957568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1094080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 433 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 27712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11458 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.082912 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.275760 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackClean 6530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1522 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1522 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 9056 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 583 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24098 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5373 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29471 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 962688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 135744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1098432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 543 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 34752 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11702 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100496 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300673 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10508 91.71% 91.71% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 950 8.29% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10526 89.95% 89.95% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1176 10.05% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11458 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15517998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11702 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15702500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13359000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13582500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3392501 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3428499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5668 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 5669 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4155 # Transaction distribution -system.membus.trans_dist::ReadExReq 1512 # Transaction distribution -system.membus.trans_dist::ReadExResp 1512 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4156 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11335 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11335 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11335 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 362688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4154 # Transaction distribution +system.membus.trans_dist::ReadExReq 1515 # Transaction distribution +system.membus.trans_dist::ReadExResp 1515 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4154 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11338 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11338 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11338 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 362816 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5668 # Request fanout histogram +system.membus.snoop_fanout::samples 5669 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5668 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5669 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5668 # Request fanout histogram -system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5669 # Request fanout histogram +system.membus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 30060000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 30047500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |