diff options
Diffstat (limited to 'tests/long/se/70.twolf')
9 files changed, 467 insertions, 460 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 91cbfaf86..ae31ca40a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -516,7 +516,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 6d5fbd5bb..dc48832a4 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:30 -gem5 started May 8 2012 16:00:57 -gem5 executing on piton +gem5 compiled May 21 2012 19:00:49 +gem5 started May 21 2012 19:00:57 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 @@ -24,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 87727531000 because target called exit() +122 123 124 Exiting @ tick 87751730000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 19ddbed23..247b6d16f 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,159 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.087728 # Number of seconds simulated -sim_ticks 87727531000 # Number of ticks simulated -final_tick 87727531000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.087752 # Number of seconds simulated +sim_ticks 87751730000 # Number of ticks simulated +final_tick 87751730000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36137 # Simulator instruction rate (inst/s) -host_op_rate 60569 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24003841 # Simulator tick rate (ticks/s) -host_mem_usage 234992 # Number of bytes of host memory used -host_seconds 3654.73 # Real time elapsed on the host +host_inst_rate 34298 # Simulator instruction rate (inst/s) +host_op_rate 57486 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22788458 # Simulator tick rate (ticks/s) +host_mem_usage 285268 # Number of bytes of host memory used +host_seconds 3850.71 # Real time elapsed on the host sim_insts 132071227 # Number of instructions simulated sim_ops 221363017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 345792 # Number of bytes read from this memory -system.physmem.bytes_inst_read 220224 # Number of instructions bytes read from this memory +system.physmem.bytes_read 345024 # Number of bytes read from this memory +system.physmem.bytes_inst_read 219584 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5403 # Number of read requests responded to by this memory +system.physmem.num_reads 5391 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3941659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2510318 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3941659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 3931820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2502332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 3931820 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 175455063 # number of cpu cycles simulated +system.cpu.numCycles 175503461 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20916443 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20916443 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2209285 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15543482 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13847483 # Number of BTB hits +system.cpu.BPredUnit.lookups 20929970 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20929970 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2208761 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15515509 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13857635 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27331578 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227091825 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20916443 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13847483 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59872682 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19479342 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 71171142 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9711 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25826236 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 465691 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 175377754 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.138493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.301400 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27320294 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 226942709 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20929970 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13857635 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59854483 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19459786 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71271521 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5211 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25822554 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 471165 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 175426420 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.136612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.300359 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 117181647 66.82% 66.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3214918 1.83% 68.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2487615 1.42% 70.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3152390 1.80% 71.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3541045 2.02% 73.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3761465 2.14% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4534795 2.59% 78.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2814480 1.60% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34689399 19.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 117249103 66.84% 66.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3234615 1.84% 68.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2477718 1.41% 70.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3147881 1.79% 71.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3542128 2.02% 73.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3766355 2.15% 76.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4530628 2.58% 78.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2823565 1.61% 80.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34654427 19.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 175377754 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119213 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.294302 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40655078 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60979767 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46580847 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10170563 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16991499 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 366154541 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16991499 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48551575 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16255360 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22908 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48159937 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45396475 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 356930622 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20611614 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22556100 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 370578330 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 915376002 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 905357204 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10018798 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 136214921 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1884 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1879 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 95075204 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89798900 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 33126150 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59105892 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19470251 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344622515 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7679 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 271009025 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 252543 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122771831 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 234148079 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6433 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 175377754 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.545287 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.468253 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 175426420 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119257 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.293095 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40654970 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 61059749 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46547974 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10189463 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16974264 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 365977737 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16974264 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48548849 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16319097 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23046 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48140036 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45421128 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 356799059 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20636040 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22537767 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 2198 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 506554560 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1130537576 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1120266829 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10270747 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 320143989 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 186410571 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1911 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1906 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95097015 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89808446 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 33130186 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59201466 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19519303 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344515408 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7842 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 270869041 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 254270 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122674827 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 297005948 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6596 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 175426420 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.544061 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.467197 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 49123743 28.01% 28.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 52511910 29.94% 57.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34319849 19.57% 77.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19020528 10.85% 88.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12714994 7.25% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4949443 2.82% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2083502 1.19% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 542650 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 111135 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 49131918 28.01% 28.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 52597598 29.98% 57.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34344441 19.58% 77.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18981959 10.82% 88.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12711399 7.25% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4926918 2.81% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2079867 1.19% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 541264 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 111056 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 175377754 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 175426420 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91290 3.51% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2230006 85.80% 89.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 277845 10.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91065 3.49% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2241508 85.86% 89.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277930 10.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212979 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 176351426 65.07% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212815 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 176257528 65.07% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1596977 0.59% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1592327 0.59% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued @@ -179,86 +180,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68342169 25.22% 91.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23505474 8.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68300084 25.22% 91.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23506287 8.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 271009025 # Type of FU issued -system.cpu.iq.rate 1.544606 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2599141 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009591 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 714934206 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 462829464 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 263397424 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5313282 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4873666 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2553131 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 269732632 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2662555 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18949841 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 270869041 # Type of FU issued +system.cpu.iq.rate 1.543383 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2610503 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009638 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714724682 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 462639790 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 263265519 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5304593 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4857798 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2549095 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 269608691 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2658038 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18925158 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33149310 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 29835 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 306343 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12610434 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33158856 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 30567 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 304625 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12614470 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 47714 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 47486 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16991499 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 515293 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 247384 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 344630194 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 299081 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89798900 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 33126150 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 161274 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 32917 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 306343 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1299828 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1028827 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2328655 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 267903545 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67266011 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3105480 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16974264 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 523635 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 253200 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344523250 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 297274 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89808446 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 33130186 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1859 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 168556 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 31575 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 304625 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1298513 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1028751 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2327264 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 267763849 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67223329 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3105192 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90381113 # number of memory reference insts executed -system.cpu.iew.exec_branches 14784987 # Number of branches executed -system.cpu.iew.exec_stores 23115102 # Number of stores executed -system.cpu.iew.exec_rate 1.526907 # Inst execution rate -system.cpu.iew.wb_sent 266831657 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 265950555 # cumulative count of insts written-back -system.cpu.iew.wb_producers 214539100 # num instructions producing a value -system.cpu.iew.wb_consumers 362277288 # num instructions consuming a value +system.cpu.iew.exec_refs 90337843 # number of memory reference insts executed +system.cpu.iew.exec_branches 14773998 # Number of branches executed +system.cpu.iew.exec_stores 23114514 # Number of stores executed +system.cpu.iew.exec_rate 1.525690 # Inst execution rate +system.cpu.iew.wb_sent 266689649 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 265814614 # cumulative count of insts written-back +system.cpu.iew.wb_producers 214459238 # num instructions producing a value +system.cpu.iew.wb_consumers 504388651 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.515776 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.592196 # average fanout of values written-back +system.cpu.iew.wb_rate 1.514583 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.425186 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 123379420 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 123271968 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2210265 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158386255 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.397615 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.796088 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2209353 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158452156 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.397034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.794480 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 54200924 34.22% 34.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 60421756 38.15% 72.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15533803 9.81% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12711410 8.03% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4532649 2.86% 93.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2958963 1.87% 94.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2077692 1.31% 96.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1244602 0.79% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4704456 2.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 54225216 34.22% 34.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 60443910 38.15% 72.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15544008 9.81% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12710691 8.02% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4546278 2.87% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2974927 1.88% 94.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2086566 1.32% 96.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1244605 0.79% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4675955 2.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158386255 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158452156 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071227 # Number of instructions committed system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -269,64 +270,64 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4704456 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4675955 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 498424236 # The number of ROB reads -system.cpu.rob.rob_writes 706514017 # The number of ROB writes -system.cpu.timesIdled 1681 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 77309 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 498411186 # The number of ROB reads +system.cpu.rob.rob_writes 706281673 # The number of ROB writes +system.cpu.timesIdled 1684 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 77041 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071227 # Number of Instructions Simulated system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated -system.cpu.cpi 1.328488 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.328488 # CPI: Total CPI of All Threads -system.cpu.ipc 0.752735 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.752735 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511675262 # number of integer regfile reads -system.cpu.int_regfile_writes 274174484 # number of integer regfile writes -system.cpu.fp_regfile_reads 3515494 # number of floating regfile reads -system.cpu.fp_regfile_writes 2227241 # number of floating regfile writes -system.cpu.misc_regfile_reads 139504609 # number of misc regfile reads +system.cpu.cpi 1.328855 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.328855 # CPI: Total CPI of All Threads +system.cpu.ipc 0.752528 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.752528 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 657510090 # number of integer regfile reads +system.cpu.int_regfile_writes 365370199 # number of integer regfile writes +system.cpu.fp_regfile_reads 3509073 # number of floating regfile reads +system.cpu.fp_regfile_writes 2221147 # number of floating regfile writes +system.cpu.misc_regfile_reads 139423581 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5602 # number of replacements -system.cpu.icache.tagsinuse 1631.479553 # Cycle average of tags in use -system.cpu.icache.total_refs 25817139 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7573 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3409.103262 # Average number of references to valid blocks. +system.cpu.icache.replacements 5601 # number of replacements +system.cpu.icache.tagsinuse 1627.936468 # Cycle average of tags in use +system.cpu.icache.total_refs 25813461 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7571 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3409.518029 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1631.479553 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.796621 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.796621 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25817139 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25817139 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25817139 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25817139 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25817139 # number of overall hits -system.cpu.icache.overall_hits::total 25817139 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9097 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9097 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9097 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9097 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9097 # number of overall misses -system.cpu.icache.overall_misses::total 9097 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 188035000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 188035000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 188035000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 188035000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 188035000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 188035000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25826236 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25826236 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25826236 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25826236 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25826236 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25826236 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1627.936468 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.794891 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.794891 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25813461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25813461 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25813461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25813461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25813461 # number of overall hits +system.cpu.icache.overall_hits::total 25813461 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9093 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9093 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9093 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9093 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9093 # number of overall misses +system.cpu.icache.overall_misses::total 9093 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 187306000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 187306000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 187306000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 187306000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 187306000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 187306000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25822554 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25822554 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25822554 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25822554 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25822554 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25822554 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20670.001099 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,80 +336,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1378 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1378 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1378 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1378 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1378 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1378 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7719 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7719 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7719 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7719 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7719 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7719 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130954500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 130954500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130954500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 130954500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130954500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 130954500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1367 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1367 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1367 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1367 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1367 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1367 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7726 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7726 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7726 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7726 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7726 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7726 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130634500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130634500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130634500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130634500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130634500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130634500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16965.215702 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16908.426094 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 54 # number of replacements -system.cpu.dcache.tagsinuse 1429.840369 # Cycle average of tags in use -system.cpu.dcache.total_refs 68659767 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1998 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34364.247748 # Average number of references to valid blocks. +system.cpu.dcache.replacements 56 # number of replacements +system.cpu.dcache.tagsinuse 1426.584624 # Cycle average of tags in use +system.cpu.dcache.total_refs 68642098 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1997 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34372.607912 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1429.840369 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.349082 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.349082 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48145557 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48145557 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514023 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514023 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68659580 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68659580 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68659580 # number of overall hits -system.cpu.dcache.overall_hits::total 68659580 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 765 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 765 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1707 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1707 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2472 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2472 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2472 # number of overall misses -system.cpu.dcache.overall_misses::total 2472 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24609000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24609000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64758500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64758500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89367500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89367500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89367500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89367500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48146322 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48146322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1426.584624 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.348287 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.348287 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48127880 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48127880 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514014 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514014 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68641894 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68641894 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68641894 # number of overall hits +system.cpu.dcache.overall_hits::total 68641894 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 772 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 772 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1716 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1716 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2488 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2488 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2488 # number of overall misses +system.cpu.dcache.overall_misses::total 2488 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24823500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24823500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 65115000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 65115000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89938500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89938500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89938500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89938500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48128652 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48128652 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 68662052 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 68662052 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 68662052 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 68662052 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 68644382 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68644382 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68644382 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68644382 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32168.627451 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37937.024019 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32154.792746 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37945.804196 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,119 +420,119 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 323 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 331 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 442 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 442 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1704 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1704 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14613500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14613500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59538000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59538000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 74151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74151500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 74151500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 334 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 334 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 334 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 441 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 441 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1713 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1713 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2154 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2154 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2154 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2154 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14546500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14546500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59868000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59868000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74414500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 74414500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74414500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 74414500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33062.217195 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34940.140845 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34553.355079 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34553.355079 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32985.260771 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34949.211909 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2591.074934 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4164 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3853 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.080716 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2579.336511 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4173 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3841 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.086436 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1.913608 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2287.446518 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 301.714808 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000058 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069807 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.009208 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.079073 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 4132 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 4162 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 1.713269 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2279.819240 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 297.804001 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000052 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.069575 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.009088 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.078715 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 4140 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 4171 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4132 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 38 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 4170 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4132 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 38 # number of overall hits -system.cpu.l2cache.overall_hits::total 4170 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 411 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3852 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 146 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 146 # number of UpgradeReq misses +system.cpu.l2cache.demand_hits::cpu.inst 4140 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 4179 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4140 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits +system.cpu.l2cache.overall_hits::total 4179 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3431 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 409 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3840 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 155 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 155 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1551 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1551 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3441 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5403 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3441 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses -system.cpu.l2cache.overall_misses::total 5403 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117870000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14049500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 131919500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52980000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 52980000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 117870000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 67029500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 184899500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 117870000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 67029500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 184899500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7573 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 441 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 8014 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 3431 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1960 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5391 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3431 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1960 # number of overall misses +system.cpu.l2cache.overall_misses::total 5391 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117518500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13976500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 131495000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52996000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 52996000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 117518500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 66972500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 184491000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 117518500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 66972500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 184491000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7571 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 440 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8011 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 146 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 146 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 155 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 155 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1559 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1559 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7573 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9573 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7573 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9573 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.454377 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.931973 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 7571 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1999 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9570 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7571 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1999 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9570 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.453177 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929545 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.454377 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.981000 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.454377 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.981000 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34254.577158 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34183.698297 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34158.607350 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.453177 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980490 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.453177 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980490 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.967356 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34172.371638 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34168.923275 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,48 +541,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3441 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 411 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3852 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 146 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 146 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3431 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 409 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3840 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 155 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 155 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1551 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3441 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5403 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3441 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5403 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106751500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12743500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119495000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4526000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4526000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48112000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48112000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106751500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60855500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 167607000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106751500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60855500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 167607000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.931973 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3431 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1960 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5391 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3431 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1960 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5391 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106440500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12676500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119117000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4805000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4805000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106440500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60787000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 167227500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106440500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60787000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 167227500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.394362 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.082725 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.987105 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index 8039a1c87..774020e98 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -103,7 +103,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index 8d8c9ffed..776b4fadc 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:30 -gem5 started May 8 2012 16:01:40 -gem5 executing on piton +gem5 compiled May 21 2012 19:00:49 +gem5 started May 21 2012 19:08:43 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 8ac81bf15..be9f62e84 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393100000 # Number of ticks simulated final_tick 131393100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 595335 # Simulator instruction rate (inst/s) -host_op_rate 997834 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 592278441 # Simulator tick rate (ticks/s) -host_mem_usage 222596 # Number of bytes of host memory used -host_seconds 221.84 # Real time elapsed on the host +host_inst_rate 449336 # Simulator instruction rate (inst/s) +host_op_rate 753127 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 447028889 # Simulator tick rate (ticks/s) +host_mem_usage 272700 # Number of bytes of host memory used +host_seconds 293.93 # Real time elapsed on the host sim_insts 132071228 # Number of instructions simulated sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1698379042 # Number of bytes read from this memory @@ -33,8 +33,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls system.cpu.num_int_insts 220339607 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read -system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written +system.cpu.num_int_register_reads 705008819 # number of times the integer registers were read +system.cpu.num_int_register_writes 318312586 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written system.cpu.num_mem_refs 77165306 # number of memory refs diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 4785eec61..8ab20ef21 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -185,7 +185,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index b246803c9..483a9fc09 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:30 -gem5 started May 8 2012 16:03:05 -gem5 executing on piton +gem5 compiled May 21 2012 19:00:49 +gem5 started May 21 2012 19:00:58 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 4699fa0ff..029c5536e 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250961 # Nu sim_ticks 250960631000 # Number of ticks simulated final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 334930 # Simulator instruction rate (inst/s) -host_op_rate 561373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 636431760 # Simulator tick rate (ticks/s) -host_mem_usage 231532 # Number of bytes of host memory used -host_seconds 394.32 # Real time elapsed on the host +host_inst_rate 291052 # Simulator instruction rate (inst/s) +host_op_rate 487829 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 553054781 # Simulator tick rate (ticks/s) +host_mem_usage 281636 # Number of bytes of host memory used +host_seconds 453.77 # Real time elapsed on the host sim_insts 132071228 # Number of instructions simulated sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read 303040 # Number of bytes read from this memory @@ -32,8 +32,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls system.cpu.num_int_insts 220339607 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read -system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written +system.cpu.num_int_register_reads 705008819 # number of times the integer registers were read +system.cpu.num_int_register_writes 318312586 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written system.cpu.num_mem_refs 77165306 # number of memory refs |