diff options
Diffstat (limited to 'tests/long/se/70.twolf')
12 files changed, 2665 insertions, 2101 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 44b065dab..4f9464f49 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041622 # Number of seconds simulated -sim_ticks 41622221000 # Number of ticks simulated -final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041671 # Number of seconds simulated +sim_ticks 41671058000 # Number of ticks simulated +final_tick 41671058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47594 # Simulator instruction rate (inst/s) -host_op_rate 47594 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21554846 # Simulator tick rate (ticks/s) -host_mem_usage 275256 # Number of bytes of host memory used -host_seconds 1930.99 # Real time elapsed on the host +host_inst_rate 79080 # Simulator instruction rate (inst/s) +host_op_rate 79080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35856814 # Simulator tick rate (ticks/s) +host_mem_usage 228800 # Number of bytes of host memory used +host_seconds 1162.15 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4296167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3296701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7592867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4296167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4296167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4296167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3296701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7592867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4291132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3292837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7583969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4291132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4291132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4291132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3292837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7583969 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 316032 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 311 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 293 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 259 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 294 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 351 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 382 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 499 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 209 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 212 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 265 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 469 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 423 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41622168000 # Total gap between requests +system.physmem.totGap 41670985500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,56 +149,135 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 23362750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 122110250 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 858.311111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 328.631203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1420.533351 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 87 24.17% 24.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 46 12.78% 36.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 36 10.00% 46.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 14 3.89% 50.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 20 5.56% 56.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 14 3.89% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 9 2.50% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 7 1.94% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 8 2.22% 66.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3 0.83% 67.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 8 2.22% 70.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 5 1.39% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 1.67% 73.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 7 1.94% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 4 1.11% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 2 0.56% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 1.39% 78.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1 0.28% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.83% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 5 1.39% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.28% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.83% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 1.11% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.56% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.83% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.83% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.56% 85.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 4 1.11% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.28% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 4 1.11% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.56% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.83% 89.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.28% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.28% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 3 0.83% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.56% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.28% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.56% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.28% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 2 0.56% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.28% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.28% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.28% 93.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.56% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.28% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.28% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.28% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.28% 95.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.28% 95.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.56% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.28% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.28% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.28% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.28% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.28% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.28% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation +system.physmem.totQLat 21938250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 110827000 # Sum of mem lat for all requests system.physmem.totBusLat 24690000 # Total cycles spent in databus access -system.physmem.totBankLat 74057500 # Total cycles spent in bank access -system.physmem.avgQLat 4731.22 # Average queueing delay per request -system.physmem.avgBankLat 14997.47 # Average bank access latency per request +system.physmem.totBankLat 64198750 # Total cycles spent in bank access +system.physmem.avgQLat 4442.74 # Average queueing delay per request +system.physmem.avgBankLat 13000.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24728.69 # Average memory access latency -system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22443.70 # Average memory access latency +system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4243 # Number of row buffer hits during reads +system.physmem.readRowHits 4578 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads +system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8428952.61 # Average gap between requests -system.cpu.branchPred.lookups 13412628 # Number of BP lookups -system.cpu.branchPred.condPredicted 9650145 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups -system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits +system.physmem.avgGap 8438838.70 # Average gap between requests +system.membus.throughput 7583969 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3216 # Transaction distribution +system.membus.trans_dist::ReadResp 3216 # Transaction distribution +system.membus.trans_dist::ReadExReq 1722 # Transaction distribution +system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 9876 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 9876 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 316032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 316032 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 316032 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 5804000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 46092250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.branchPred.lookups 13412467 # Number of BP lookups +system.cpu.branchPred.condPredicted 9649930 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4269365 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 7424694 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3768519 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.757723 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 50.756556 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996247 # DTB read hits +system.cpu.dtb.read_hits 19996249 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996257 # DTB read accesses -system.cpu.dtb.write_hits 6501860 # DTB write hits +system.cpu.dtb.read_accesses 19996259 # DTB read accesses +system.cpu.dtb.write_hits 6501862 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501883 # DTB write accesses -system.cpu.dtb.data_hits 26498107 # DTB hits +system.cpu.dtb.write_accesses 6501885 # DTB write accesses +system.cpu.dtb.data_hits 26498111 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498140 # DTB accesses -system.cpu.itb.fetch_hits 9956943 # ITB hits +system.cpu.dtb.data_accesses 26498144 # DTB accesses +system.cpu.itb.fetch_hits 9957259 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9956992 # ITB accesses +system.cpu.itb.fetch_accesses 9957308 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -212,34 +291,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83244443 # number of cpu cycles simulated +system.cpu.numCycles 83342117 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7506964 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570548 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 5905707 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7506760 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73570716 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146020 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136146188 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206130 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38521871 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26722393 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57404029 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 8058018 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38521724 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26722400 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3469281 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 799226 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4268507 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5972195 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 41.681781 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57404114 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82970150 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82971475 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10684 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7636716 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607727 # Number of cycles cpu stages are processed. -system.cpu.activity 90.826155 # Percentage of cycles cpu is active +system.cpu.timesIdled 10802 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7733735 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75608382 # Number of cycles cpu stages are processed. +system.cpu.activity 90.720496 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -251,72 +330,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.905785 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.906848 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.905785 # CPI: Total CPI of All Threads -system.cpu.ipc 1.104014 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.906848 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102720 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.104014 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27564085 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680358 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.887778 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33992749 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251694 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.165143 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33393108 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49851335 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.885481 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65217942 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.654900 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29384710 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859733 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.700695 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7635 # number of replacements -system.cpu.icache.tagsinuse 1492.649281 # Cycle average of tags in use -system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks. +system.cpu.ipc_total 1.102720 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27661043 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55681074 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.810247 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34090230 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251887 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.096035 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33490685 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851432 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.815414 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65315589 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026528 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.629554 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29482268 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859849 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.625007 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 7633 # number of replacements +system.cpu.icache.tagsinuse 1492.272065 # Cycle average of tags in use +system.cpu.icache.total_refs 9945862 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9518 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1044.952931 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.649281 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9945578 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9945578 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9945578 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9945578 # number of overall hits -system.cpu.icache.overall_hits::total 9945578 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11365 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11365 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11365 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses -system.cpu.icache.overall_misses::total 11365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259163500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259163500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259163500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259163500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259163500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259163500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9956943 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9956943 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9956943 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001141 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001141 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001141 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22803.651562 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22803.651562 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22803.651562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22803.651562 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1492.272065 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728648 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728648 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 9945862 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9945862 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9945862 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9945862 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9945862 # number of overall hits +system.cpu.icache.overall_hits::total 9945862 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11397 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11397 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11397 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11397 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11397 # number of overall misses +system.cpu.icache.overall_misses::total 11397 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 317452000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 317452000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 317452000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 317452000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 317452000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 317452000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9957259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9957259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9957259 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9957259 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9957259 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9957259 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27853.996666 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27853.996666 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27853.996666 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27853.996666 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -325,63 +404,83 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1845 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1845 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1845 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1845 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209587500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 209587500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209587500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 209587500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209587500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 209587500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9518 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9518 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9518 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9518 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9518 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9518 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 260091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 260091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 260091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 260091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 260091000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 260091000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22015.493697 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22015.493697 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22015.493697 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22015.493697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22015.493697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22015.493697 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27326.223997 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27326.223997 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 18196610 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 9993 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 9993 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19036 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 23589 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 609152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 758272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 758272 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 6031000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 14277000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2190.263303 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2189.717368 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6791 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.069165 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.839003 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1821.325102 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.099198 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 17.843612 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.867359 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.006398 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 6724 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6777 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # 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number of ReadReq misses @@ -393,52 +492,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132531500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24055000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 156586500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84148000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84148000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 132531500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 108203000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 240734500 # 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number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9520 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 9518 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 11743 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9520 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 11741 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9518 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 11743 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293487 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 11741 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293549 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.321761 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.321825 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293487 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293549 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.420506 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.420577 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293549 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47434.323550 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57002.369668 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48689.832090 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48866.434379 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48866.434379 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47434.323550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50467.817164 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 48751.417578 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47434.323550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50467.817164 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48751.417578 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.420577 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65517.895490 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71539.099526 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66307.991294 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66602.206736 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66602.206736 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66410.591333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66410.591333 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -458,73 +557,73 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97814921 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18797852 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116612773 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63183937 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63183937 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97814921 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81981789 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 179796710 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97814921 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81981789 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 179796710 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 148372000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24939500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 173311500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93717750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93717750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 148372000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118657250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 267029250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 148372000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118657250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 267029250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.420577 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35008.919470 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44544.672986 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36260.190609 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36692.181765 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36692.181765 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35008.919470 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38237.774720 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36410.836371 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35008.919470 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38237.774720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36410.836371 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.420577 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53103.793844 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59098.341232 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53890.391791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54423.780488 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54423.780488 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.801421 # Cycle average of tags in use -system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.455577 # Cycle average of tags in use +system.cpu.dcache.total_refs 26488507 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11915.657670 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.801421 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493002 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493002 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488625 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488625 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488625 # number of overall hits -system.cpu.dcache.overall_hits::total 26488625 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8101 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8101 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8676 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8676 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8676 # number of overall misses -system.cpu.dcache.overall_misses::total 8676 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31369500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31369500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 346048500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 346048500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 377418000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 377418000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 377418000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 377418000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.455577 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492885 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492885 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488507 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488507 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488507 # number of overall hits +system.cpu.dcache.overall_hits::total 26488507 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 576 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 576 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8218 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8218 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8794 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8794 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8794 # number of overall misses +system.cpu.dcache.overall_misses::total 8794 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 38984000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 38984000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 463524000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 463524000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 502508000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 502508000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 502508000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 502508000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -535,38 +634,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54555.652174 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54555.652174 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42716.763363 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42716.763363 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 43501.383126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 43501.383126 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13712 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001264 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001264 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000332 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000332 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000332 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000332 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67680.555556 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67680.555556 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56403.504502 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56403.504502 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57142.142370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57142.142370 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21765 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 825 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.681265 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.381818 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6353 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6353 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6453 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6453 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6453 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6453 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6470 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6470 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6571 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6571 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6571 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6571 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -575,14 +674,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25078500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25078500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86165500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86165500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111244000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 111244000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111244000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 111244000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116706500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116706500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147919500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 147919500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147919500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 147919500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -591,14 +690,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52796.842105 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52796.842105 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49293.764302 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49293.764302 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65711.578947 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65711.578947 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66765.732265 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66765.732265 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 557ecc886..183d79059 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023380 # Number of seconds simulated -sim_ticks 23379948000 # Number of ticks simulated -final_tick 23379948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023497 # Number of seconds simulated +sim_ticks 23497413000 # Number of ticks simulated +final_tick 23497413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61366 # Simulator instruction rate (inst/s) -host_op_rate 61366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17043654 # Simulator tick rate (ticks/s) -host_mem_usage 277304 # Number of bytes of host memory used -host_seconds 1371.77 # Real time elapsed on the host +host_inst_rate 127551 # Simulator instruction rate (inst/s) +host_op_rate 127551 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35603882 # Simulator tick rate (ticks/s) +host_mem_usage 231880 # Number of bytes of host memory used +host_seconds 659.97 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 195840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138688 # Number of bytes read from this memory -system.physmem.bytes_read::total 334528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195840 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3060 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2167 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8376409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5931921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14308330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8376409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8376409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8376409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5931921 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14308330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5227 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 195392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory +system.physmem.bytes_read::total 334016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195392 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3053 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5219 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8315469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5899543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14215012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8315469 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8315469 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8315469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5899543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14215012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5219 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5227 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 334528 # Total number of bytes read from memory +system.physmem.cpureqs 5219 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 334016 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 334528 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 334016 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 311 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 281 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 365 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 377 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 354 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 400 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 237 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 398 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 491 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 446 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23379842000 # Total gap between requests +system.physmem.totGap 23497287000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5227 # Categorize read packet sizes +system.physmem.readPktSize::6 5219 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 547 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,56 +149,139 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 29390250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 134711500 # Sum of mem lat for all requests -system.physmem.totBusLat 26135000 # Total cycles spent in databus access -system.physmem.totBankLat 79186250 # Total cycles spent in bank access -system.physmem.avgQLat 5622.78 # Average queueing delay per request -system.physmem.avgBankLat 15149.46 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 779.330144 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 283.808293 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1370.086091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 124 29.67% 29.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 51 12.20% 41.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 42 10.05% 51.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 20 4.78% 56.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15 3.59% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 19 4.55% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7 1.67% 66.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 9 2.15% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 7 1.67% 70.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3 0.72% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 8 1.91% 72.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 7 1.67% 74.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 1.44% 76.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 5 1.20% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 4 0.96% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1 0.24% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 6 1.44% 79.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 5 1.20% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.72% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.72% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.72% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.72% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.48% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.48% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.24% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 2 0.48% 91.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.24% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.24% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.24% 93.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.24% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.24% 95.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.24% 96.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.48% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.24% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.24% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.24% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.24% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.48% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 4 0.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 418 # Bytes accessed per row activation +system.physmem.totQLat 22102000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 116465750 # Sum of mem lat for all requests +system.physmem.totBusLat 26095000 # Total cycles spent in databus access +system.physmem.totBankLat 68268750 # Total cycles spent in bank access +system.physmem.avgQLat 4234.91 # Average queueing delay per request +system.physmem.avgBankLat 13080.81 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25772.24 # Average memory access latency -system.physmem.avgRdBW 14.31 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22315.72 # Average memory access latency +system.physmem.avgRdBW 14.22 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.31 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.22 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.11 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time +system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4448 # Number of row buffer hits during reads +system.physmem.readRowHits 4801 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 91.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4472898.79 # Average gap between requests -system.cpu.branchPred.lookups 14842140 # Number of BP lookups -system.cpu.branchPred.condPredicted 10766991 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 921197 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8255704 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6953438 # Number of BTB hits +system.physmem.avgGap 4502258.48 # Average gap between requests +system.membus.throughput 14215012 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3511 # Transaction distribution +system.membus.trans_dist::ReadResp 3511 # Transaction distribution +system.membus.trans_dist::ReadExReq 1708 # Transaction distribution +system.membus.trans_dist::ReadExResp 1708 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 10438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 10438 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334016 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 334016 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334016 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 6341000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 48807250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.branchPred.lookups 14862551 # Number of BP lookups +system.cpu.branchPred.condPredicted 10783549 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 926034 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8413875 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6968843 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 84.225864 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1467825 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3067 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.825607 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1469354 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3121 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23110097 # DTB read hits -system.cpu.dtb.read_misses 194589 # DTB read misses +system.cpu.dtb.read_hits 23132924 # DTB read hits +system.cpu.dtb.read_misses 192093 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23304686 # DTB read accesses -system.cpu.dtb.write_hits 7067053 # DTB write hits -system.cpu.dtb.write_misses 1113 # DTB write misses -system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 7068166 # DTB write accesses -system.cpu.dtb.data_hits 30177150 # DTB hits -system.cpu.dtb.data_misses 195702 # DTB misses -system.cpu.dtb.data_acv 8 # DTB access violations -system.cpu.dtb.data_accesses 30372852 # DTB accesses -system.cpu.itb.fetch_hits 14723480 # ITB hits -system.cpu.itb.fetch_misses 97 # ITB misses +system.cpu.dtb.read_accesses 23325017 # DTB read accesses +system.cpu.dtb.write_hits 7072345 # DTB write hits +system.cpu.dtb.write_misses 1094 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 7073439 # DTB write accesses +system.cpu.dtb.data_hits 30205269 # DTB hits +system.cpu.dtb.data_misses 193187 # DTB misses +system.cpu.dtb.data_acv 4 # DTB access violations +system.cpu.dtb.data_accesses 30398456 # DTB accesses +system.cpu.itb.fetch_hits 14755058 # ITB hits +system.cpu.itb.fetch_misses 101 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14723577 # ITB accesses +system.cpu.itb.fetch_accesses 14755159 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -212,139 +295,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46759897 # number of cpu cycles simulated +system.cpu.numCycles 46994827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15452025 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126885771 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14842140 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8421263 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22118402 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4462593 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5523983 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2725 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 15489149 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127098752 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14862551 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8438197 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22157137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4490975 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5583322 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2356 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14723480 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 324121 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46604653 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.722599 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 14755058 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 326188 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46762472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.717965 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.375306 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24486251 52.54% 52.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2361565 5.07% 57.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1190149 2.55% 60.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1742976 3.74% 63.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2754417 5.91% 69.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1149365 2.47% 72.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1217917 2.61% 74.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 773119 1.66% 76.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10928894 23.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24605335 52.62% 52.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2364392 5.06% 57.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1192796 2.55% 60.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1746753 3.74% 63.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2761574 5.91% 69.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1153115 2.47% 72.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1218931 2.61% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 773556 1.65% 76.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10946020 23.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46604653 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317412 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.713560 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17272805 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4225851 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20520611 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1089695 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3495691 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2514029 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12278 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123910172 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32104 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3495691 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18413803 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 951839 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7350 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20446933 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3289037 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121090735 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 56 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 399536 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2410998 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88918567 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157348562 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 147674536 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9674026 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46762472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316259 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.704526 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17321703 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4276623 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20543509 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1101986 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3518651 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2516350 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12158 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 124100512 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31524 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3518651 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18468008 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 966877 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7668 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20476490 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3324778 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121264521 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 82 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 403236 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2443262 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89058236 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157582364 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 147884300 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9698064 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20491206 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 720 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 712 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8742624 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25345876 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8236695 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2569867 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 913943 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105383195 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1656 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96551560 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178239 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20729473 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15559619 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1267 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46604653 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.071715 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.877215 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20630875 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 727 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 718 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8817740 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25385211 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8251770 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2611914 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 924495 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105530247 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1715 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96635335 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178536 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20879466 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15657073 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1326 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46762472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.066515 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875135 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12094878 25.95% 25.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9328666 20.02% 45.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8376475 17.97% 63.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6286526 13.49% 77.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4922367 10.56% 87.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2863469 6.14% 94.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1727619 3.71% 97.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 799385 1.72% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 205268 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12166038 26.02% 26.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9374565 20.05% 46.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8425963 18.02% 64.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6292522 13.46% 77.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4920709 10.52% 88.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2854864 6.11% 94.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1726414 3.69% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 795538 1.70% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 205859 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46604653 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46762472 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 187515 11.95% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 174 0.01% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7228 0.46% 12.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5644 0.36% 12.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843061 53.75% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 446254 28.45% 94.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78748 5.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 190796 12.16% 12.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 179 0.01% 12.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7128 0.45% 12.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5650 0.36% 12.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843178 53.72% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 444699 28.33% 95.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77939 4.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58727382 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479803 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58779410 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479944 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2798335 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115384 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386573 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311072 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760041 0.79% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2800605 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115340 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387840 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311019 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760059 0.79% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued @@ -366,84 +449,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23822951 24.67% 92.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7149693 7.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23845244 24.68% 92.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7155548 7.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96551560 # Type of FU issued -system.cpu.iq.rate 2.064837 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568624 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016246 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226343159 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117415886 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87055232 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15111477 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8732806 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7062055 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90134309 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7985868 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1517472 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96635335 # Type of FU issued +system.cpu.iq.rate 2.056297 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1569569 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016242 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226659120 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117679968 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87126809 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15122127 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8766253 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7066480 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90213613 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7991284 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1520773 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5349678 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18734 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34491 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1735592 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5389013 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18483 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34901 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1750667 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10525 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1599 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10533 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1986 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3495691 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 132330 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18056 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115618245 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 370442 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25345876 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8236695 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1656 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2792 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34491 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 533607 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 495069 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1028676 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95323071 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23305173 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1228489 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3518651 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 134178 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18459 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115772618 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 373350 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25385211 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8251770 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1715 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3175 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34901 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 538953 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495548 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034501 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95401130 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23325510 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1234205 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10233394 # number of nop insts executed -system.cpu.iew.exec_refs 30373541 # number of memory reference insts executed -system.cpu.iew.exec_branches 12020857 # Number of branches executed -system.cpu.iew.exec_stores 7068368 # Number of stores executed -system.cpu.iew.exec_rate 2.038565 # Inst execution rate -system.cpu.iew.wb_sent 94638543 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94117287 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64469301 # num instructions producing a value -system.cpu.iew.wb_consumers 89849772 # num instructions consuming a value +system.cpu.iew.exec_nop 10240656 # number of nop insts executed +system.cpu.iew.exec_refs 30399148 # number of memory reference insts executed +system.cpu.iew.exec_branches 12029434 # Number of branches executed +system.cpu.iew.exec_stores 7073638 # Number of stores executed +system.cpu.iew.exec_rate 2.030035 # Inst execution rate +system.cpu.iew.wb_sent 94712572 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94193289 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64506867 # num instructions producing a value +system.cpu.iew.wb_consumers 89893282 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.012778 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717523 # average fanout of values written-back +system.cpu.iew.wb_rate 2.004333 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717594 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23716139 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23870674 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 909447 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43108962 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.131878 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.747863 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 914298 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43243821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.125230 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.743207 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16687185 38.71% 38.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9891500 22.95% 61.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4481461 10.40% 72.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2260770 5.24% 77.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1601496 3.71% 81.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1124303 2.61% 83.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 719465 1.67% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 820222 1.90% 87.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5522560 12.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16770420 38.78% 38.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9933071 22.97% 61.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4488153 10.38% 72.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2264318 5.24% 77.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1614513 3.73% 81.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1126501 2.60% 83.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722210 1.67% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820173 1.90% 87.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5504462 12.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43108962 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43243821 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -454,192 +537,212 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5522560 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5504462 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153204556 # The number of ROB reads -system.cpu.rob.rob_writes 234757733 # The number of ROB writes -system.cpu.timesIdled 5297 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 155244 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153512048 # The number of ROB reads +system.cpu.rob.rob_writes 235089898 # The number of ROB writes +system.cpu.timesIdled 5458 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 232355 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.555477 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555477 # CPI: Total CPI of All Threads -system.cpu.ipc 1.800254 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.800254 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129030140 # number of integer regfile reads -system.cpu.int_regfile_writes 70506108 # number of integer regfile writes -system.cpu.fp_regfile_reads 6188141 # number of floating regfile reads -system.cpu.fp_regfile_writes 6043644 # number of floating regfile writes -system.cpu.misc_regfile_reads 714512 # number of misc regfile reads +system.cpu.cpi 0.558268 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.558268 # CPI: Total CPI of All Threads +system.cpu.ipc 1.791255 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.791255 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129137938 # number of integer regfile reads +system.cpu.int_regfile_writes 70566847 # number of integer regfile writes +system.cpu.fp_regfile_reads 6190616 # number of floating regfile reads +system.cpu.fp_regfile_writes 6048237 # number of floating regfile writes +system.cpu.misc_regfile_reads 714522 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 9682 # number of replacements -system.cpu.icache.tagsinuse 1594.464074 # Cycle average of tags in use -system.cpu.icache.total_refs 14709198 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11615 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1266.396728 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 38347030 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12236 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12236 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 28049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 750272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 901056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 901056 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 7148500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 17584500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3370500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 9791 # number of replacements +system.cpu.icache.tagsinuse 1591.709559 # Cycle average of tags in use +system.cpu.icache.total_refs 14740526 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11723 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1257.402201 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1594.464074 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.778547 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.778547 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14709198 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14709198 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14709198 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14709198 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14709198 # number of overall hits -system.cpu.icache.overall_hits::total 14709198 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14281 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14281 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14281 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14281 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14281 # number of overall misses -system.cpu.icache.overall_misses::total 14281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 321909000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 321909000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 321909000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 321909000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 321909000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 321909000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14723479 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14723479 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14723479 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14723479 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14723479 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14723479 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000970 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000970 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22541.068553 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22541.068553 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22541.068553 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22541.068553 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22541.068553 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22541.068553 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1591.709559 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777202 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777202 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14740526 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14740526 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14740526 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14740526 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14740526 # number of overall hits +system.cpu.icache.overall_hits::total 14740526 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14531 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14531 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14531 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14531 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14531 # number of overall misses +system.cpu.icache.overall_misses::total 14531 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 399004500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 399004500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 399004500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 399004500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 399004500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 399004500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14755057 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14755057 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14755057 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14755057 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14755057 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14755057 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000985 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000985 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000985 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000985 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000985 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000985 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27458.846604 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27458.846604 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27458.846604 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27458.846604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27458.846604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27458.846604 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.714286 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2666 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2666 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2666 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2666 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2666 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2666 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11615 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11615 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11615 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11615 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11615 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11615 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242799000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 242799000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242799000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 242799000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242799000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 242799000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000789 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000789 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000789 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000789 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000789 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000789 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20903.917348 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20903.917348 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20903.917348 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20903.917348 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20903.917348 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20903.917348 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2808 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2808 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2808 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2808 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2808 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2808 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11723 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11723 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11723 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11723 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11723 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11723 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 297568500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 297568500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 297568500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 297568500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 297568500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 297568500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000795 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000795 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000795 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000795 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000795 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000795 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25383.306321 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25383.306321 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25383.306321 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 25383.306321 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25383.306321 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 25383.306321 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2409.273789 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8624 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3589 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.402898 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2401.280211 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8740 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3578 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.442705 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.672119 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2009.862780 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 381.738890 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.673510 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2001.216545 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 382.390156 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061336 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011650 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073525 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8555 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.061072 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011670 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073281 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8670 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8610 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8725 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8555 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 8670 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8636 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8555 # number of overall hits +system.cpu.l2cache.demand_hits::total 8751 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8670 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits -system.cpu.l2cache.overall_hits::total 8636 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 356653797 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 72000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 407577797 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 407577797 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 407577797 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 407577797 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21580514 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21580514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9193 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9193 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9193 # number of overall misses +system.cpu.dcache.overall_misses::total 9193 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59585500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59585500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 475543278 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 475543278 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 535128778 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 535128778 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 535128778 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 535128778 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21599678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21599678 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 236 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 236 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28081617 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28081617 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28081617 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28081617 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004237 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004237 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000324 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000324 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50570.009930 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50570.009930 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44042.207582 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44042.207582 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 44764.173202 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 44764.173202 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 44764.173202 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 44764.173202 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14165 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 219 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 219 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28100781 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28100781 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28100781 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28100781 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001265 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001265 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004566 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004566 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61365.087539 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61365.087539 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57837.907808 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57837.907808 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58210.462091 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58210.462091 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21885 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 330 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 353 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.924242 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.997167 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # number of writebacks system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 491 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 491 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6367 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6367 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6858 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6858 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6858 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6858 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 516 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 516 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6488 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6488 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6947 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6947 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6947 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6947 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30419500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30419500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88590998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 88590998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 70000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 70000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 119010498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 119010498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119010498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 119010498 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34660000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34660000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116538997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116538997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151198997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151198997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151198997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151198997 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004237 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004237 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004566 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004566 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58952.519380 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58952.519380 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51179.086077 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51179.086077 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52964.173565 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52964.173565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52964.173565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52964.173565 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67695.312500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67695.312500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67208.187428 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67208.187428 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index e64f41702..31612b0d4 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1141309 # Simulator instruction rate (inst/s) -host_op_rate 1141309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 570654979 # Simulator tick rate (ticks/s) -host_mem_usage 267644 # Number of bytes of host memory used -host_seconds 80.52 # Real time elapsed on the host +host_inst_rate 3944537 # Simulator instruction rate (inst/s) +host_op_rate 3944535 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1972268010 # Simulator tick rate (ticks/s) +host_mem_usage 220188 # Number of bytes of host memory used +host_seconds 23.30 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 672903574 # Wr system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11030545389 # Throughput (bytes/s) +system.membus.data_through_bus 506870851 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index aead393ef..b57d95ab0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316000 # Number of ticks simulated final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1044383 # Simulator instruction rate (inst/s) -host_op_rate 1044383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1349235521 # Simulator tick rate (ticks/s) -host_mem_usage 276220 # Number of bytes of host memory used -host_seconds 88.00 # Real time elapsed on the host +host_inst_rate 852211 # Simulator instruction rate (inst/s) +host_op_rate 852211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1100968725 # Simulator tick rate (ticks/s) +host_mem_usage 228676 # Number of bytes of host memory used +host_seconds 107.84 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 1412827 # In system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 2568532 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3043 # Transaction distribution +system.membus.trans_dist::ReadResp 3043 # Transaction distribution +system.membus.trans_dist::ReadExReq 1722 # Transaction distribution +system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 9530 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 304960 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -396,5 +411,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 5843207 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 17020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 21573 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 544640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 693760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 0198a0866..e580bbf9c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074157 # Number of seconds simulated -sim_ticks 74157495500 # Number of ticks simulated -final_tick 74157495500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074184 # Number of seconds simulated +sim_ticks 74184344000 # Number of ticks simulated +final_tick 74184344000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51189 # Simulator instruction rate (inst/s) -host_op_rate 56047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22031117 # Simulator tick rate (ticks/s) -host_mem_usage 291420 # Number of bytes of host memory used -host_seconds 3366.03 # Real time elapsed on the host +host_inst_rate 120810 # Simulator instruction rate (inst/s) +host_op_rate 132276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52014122 # Simulator tick rate (ticks/s) +host_mem_usage 249648 # Number of bytes of host memory used +host_seconds 1426.23 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111936 # Number of bytes read from this memory -system.physmem.bytes_read::total 243712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131776 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2059 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1749 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3808 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1776975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1509436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3286411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1776975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1776975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1776975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1509436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3286411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3809 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 131136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory +system.physmem.bytes_read::total 242944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131136 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2049 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3796 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1767705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1507164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3274869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1767705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1767705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1767705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1507164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3274869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3796 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3811 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 243712 # Total number of bytes read from memory +system.physmem.cpureqs 3798 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 242944 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 243712 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 242944 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 272 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 252 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 262 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 217 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 288 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 201 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 199 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 274 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 189 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 206 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 199 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74157477000 # Total gap between requests +system.physmem.totGap 74184191000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3809 # Categorize read packet sizes +system.physmem.readPktSize::6 3796 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 2784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,36 +149,114 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 17510750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 103435750 # Sum of mem lat for all requests -system.physmem.totBusLat 19045000 # Total cycles spent in databus access -system.physmem.totBankLat 66880000 # Total cycles spent in bank access -system.physmem.avgQLat 4597.20 # Average queueing delay per request -system.physmem.avgBankLat 17558.41 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 376 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 621.446809 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 226.720612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1211.628472 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 135 35.90% 35.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 51 13.56% 49.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 26 6.91% 56.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 29 7.71% 64.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 14 3.72% 67.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 14 3.72% 71.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6 1.60% 73.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 5 1.33% 74.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 7 1.86% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 7 1.86% 78.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 5 1.33% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 1.60% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1 0.27% 81.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 5 1.33% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.80% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 4 1.06% 84.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 2 0.53% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.80% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.80% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1 0.27% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.27% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 5 1.33% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.53% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.27% 89.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.80% 90.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.80% 90.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.27% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.27% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.27% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.27% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.53% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.27% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.27% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.27% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.27% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.27% 93.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.27% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.27% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.27% 94.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.27% 94.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.27% 95.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.27% 95.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.27% 95.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 3 0.80% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.27% 96.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.27% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.27% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.27% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.27% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 1 0.27% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.27% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.27% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.27% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.27% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 2 0.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 376 # Bytes accessed per row activation +system.physmem.totQLat 13471250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 86310000 # Sum of mem lat for all requests +system.physmem.totBusLat 18980000 # Total cycles spent in databus access +system.physmem.totBankLat 53858750 # Total cycles spent in bank access +system.physmem.avgQLat 3548.80 # Average queueing delay per request +system.physmem.avgBankLat 14188.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27155.62 # Average memory access latency -system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22737.09 # Average memory access latency +system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3021 # Number of row buffer hits during reads +system.physmem.readRowHits 3420 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19469014.70 # Average gap between requests -system.cpu.branchPred.lookups 94703867 # Number of BP lookups -system.cpu.branchPred.condPredicted 74722053 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6280216 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44664544 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43035053 # Number of BTB hits +system.physmem.avgGap 19542726.82 # Average gap between requests +system.membus.throughput 3274869 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2721 # Transaction distribution +system.membus.trans_dist::ReadResp 2721 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 1075 # Transaction distribution +system.membus.trans_dist::ReadExResp 1075 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 7596 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 7596 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 242944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 242944 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 242944 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 4823500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 35740248 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.branchPred.lookups 94757540 # Number of BP lookups +system.cpu.branchPred.condPredicted 74764818 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6278340 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44654246 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43033777 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.351712 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4359745 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88611 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.371075 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4354951 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88346 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -222,240 +300,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148314992 # number of cpu cycles simulated +system.cpu.numCycles 148368689 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39662414 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380030694 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94703867 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47394798 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80357293 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27270600 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7200009 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5243 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39647823 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380146219 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94757540 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47388728 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80358140 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27268312 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7203967 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5523 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36857358 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1832427 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148199476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.801422 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36843987 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1833209 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148189615 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802214 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153150 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68011684 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5276203 3.56% 49.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540688 7.11% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10280783 6.94% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8654302 5.84% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6554085 4.42% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6244651 4.21% 77.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7982798 5.39% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24654282 16.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68000764 45.89% 45.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5268021 3.55% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10540392 7.11% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10285161 6.94% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8646262 5.83% 69.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6545573 4.42% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6244018 4.21% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7997629 5.40% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24661795 16.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148199476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638532 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.562322 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45512613 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5867522 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74797201 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1201275 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20820865 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14305085 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164111 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392663870 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 738369 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20820865 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50901215 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 722150 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 593982 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70547488 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4613776 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371203156 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 343152 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3655877 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631482556 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581281661 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1563963855 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17317806 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 148189615 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638663 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.562173 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45498061 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5874830 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74793705 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1202536 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20820483 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14321847 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164416 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392715815 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 749819 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20820483 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50886064 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 722985 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 600307 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70546117 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4613659 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371260855 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 344235 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3657023 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 27 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631666093 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581493948 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1564155420 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17338528 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333438417 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25133 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25129 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13026907 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 42996111 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16422667 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5676383 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3667621 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329112708 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47143 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249432965 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 790911 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139431014 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 361763997 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1927 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148199476 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761808 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 333621954 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25182 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25179 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13028807 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 42981884 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16417977 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5680787 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3667947 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329134626 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249422621 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 787073 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139456652 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 361881130 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148189615 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.683132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761818 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56042939 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22629719 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24820832 16.75% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20320046 13.71% 83.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12535804 8.46% 92.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6521757 4.40% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4030887 2.72% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1115815 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181677 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56042296 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22626121 15.27% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24808060 16.74% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20320875 13.71% 83.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12548887 8.47% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6516147 4.40% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4031410 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1113540 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182279 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148199476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148189615 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 963057 38.38% 38.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5596 0.22% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 51 0.00% 38.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1167699 46.53% 85.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372909 14.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 962595 38.42% 38.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5594 0.22% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 107 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1164588 46.49% 85.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 372359 14.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194880762 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 980286 0.39% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33071 0.01% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194884583 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979638 0.39% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33073 0.01% 78.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254305 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76429 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465674 0.19% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206396 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38348799 15.37% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13950639 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164452 0.07% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254844 0.10% 78.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76427 0.03% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465912 0.19% 78.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206449 0.08% 79.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71875 0.03% 79.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 79.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38337954 15.37% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13947091 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249432965 # Type of FU issued -system.cpu.iq.rate 1.681779 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2509413 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010060 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646629225 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466421271 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237868779 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3736505 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2188097 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1840763 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250067463 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1874915 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2006857 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249422621 # Type of FU issued +system.cpu.iq.rate 1.681100 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2505291 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010044 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646588556 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466464832 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237860517 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3738665 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2192143 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1842020 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250052019 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1875893 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2007355 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13146627 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11917 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18980 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3778033 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13132400 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11727 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18993 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3773343 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 13 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20820865 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17088 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 846 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329176829 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 784787 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 42996111 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16422667 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24735 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18980 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3891833 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3757719 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7649552 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242934999 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36843669 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6497966 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20820483 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18849 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 902 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329198829 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 786805 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 42981884 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16417977 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 191 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18993 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3888167 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3760327 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7648494 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242926605 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36835264 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6496016 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 16978 # number of nop insts executed -system.cpu.iew.exec_refs 50492106 # number of memory reference insts executed -system.cpu.iew.exec_branches 53412943 # Number of branches executed -system.cpu.iew.exec_stores 13648437 # Number of stores executed -system.cpu.iew.exec_rate 1.637967 # Inst execution rate -system.cpu.iew.wb_sent 240767037 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239709542 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148457899 # num instructions producing a value -system.cpu.iew.wb_consumers 267241195 # num instructions consuming a value +system.cpu.iew.exec_nop 17000 # number of nop insts executed +system.cpu.iew.exec_refs 50481074 # number of memory reference insts executed +system.cpu.iew.exec_branches 53424163 # Number of branches executed +system.cpu.iew.exec_stores 13645810 # Number of stores executed +system.cpu.iew.exec_rate 1.637317 # Inst execution rate +system.cpu.iew.wb_sent 240758455 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239702537 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148455856 # num instructions producing a value +system.cpu.iew.wb_consumers 267256641 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.616219 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555520 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615587 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555481 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140505920 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140527929 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6126595 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127378611 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186353 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6124743 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127369132 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.186316 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57698651 45.30% 45.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31675595 24.87% 70.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13783953 10.82% 80.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7631475 5.99% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4374952 3.43% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321227 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1703973 1.34% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1307096 1.03% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7881689 6.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57689921 45.29% 45.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31670367 24.87% 70.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13785643 10.82% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7636266 6.00% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4374586 3.43% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1321093 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1699680 1.33% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1314057 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7877519 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127378611 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127369132 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -466,200 +544,220 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7881689 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7877519 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448668532 # The number of ROB reads -system.cpu.rob.rob_writes 679284219 # The number of ROB writes -system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 115516 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448685232 # The number of ROB reads +system.cpu.rob.rob_writes 679327064 # The number of ROB writes +system.cpu.timesIdled 2810 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 179074 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.860780 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.860780 # CPI: Total CPI of All Threads -system.cpu.ipc 1.161737 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.161737 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079304778 # number of integer regfile reads -system.cpu.int_regfile_writes 384845307 # number of integer regfile writes -system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads -system.cpu.fp_regfile_writes 2496150 # number of floating regfile writes -system.cpu.misc_regfile_reads 54492663 # number of misc regfile reads +system.cpu.cpi 0.861092 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861092 # CPI: Total CPI of All Threads +system.cpu.ipc 1.161317 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.161317 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079239284 # number of integer regfile reads +system.cpu.int_regfile_writes 384835773 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913699 # number of floating regfile reads +system.cpu.fp_regfile_writes 2498274 # number of floating regfile writes +system.cpu.misc_regfile_reads 54487026 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.icache.replacements 2376 # number of replacements -system.cpu.icache.tagsinuse 1350.566241 # Cycle average of tags in use -system.cpu.icache.total_refs 36852122 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4106 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8975.188018 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 5142648 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4861 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4861 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3727 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 11907 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 261696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 381376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 381376 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2998500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 6138496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2786987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 2359 # number of replacements +system.cpu.icache.tagsinuse 1350.344535 # Cycle average of tags in use +system.cpu.icache.total_refs 36838706 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4089 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 9009.221326 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1350.566241 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.659456 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.659456 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36852123 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36852123 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36852123 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36852123 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36852123 # number of overall hits -system.cpu.icache.overall_hits::total 36852123 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5235 # number of overall misses -system.cpu.icache.overall_misses::total 5235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 167149000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 167149000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 167149000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 167149000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 167149000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 167149000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36857358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36857358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36857358 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36857358 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36857358 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36857358 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31929.130850 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31929.130850 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31929.130850 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31929.130850 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31929.130850 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31929.130850 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 608 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1350.344535 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.659348 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.659348 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36838706 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36838706 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36838706 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36838706 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36838706 # number of overall hits +system.cpu.icache.overall_hits::total 36838706 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5281 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5281 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5281 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5281 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5281 # number of overall misses +system.cpu.icache.overall_misses::total 5281 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 212968998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 212968998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 212968998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 212968998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 212968998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 212968998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36843987 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36843987 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36843987 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36843987 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36843987 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36843987 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000143 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000143 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000143 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000143 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000143 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000143 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40327.399735 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40327.399735 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40327.399735 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40327.399735 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58.350000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1123 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 128908500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128908500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 128908500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128908500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 128908500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161081503 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 161081503 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39374.603520 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39374.603520 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39374.603520 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39374.603520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39374.603520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39374.603520 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1970.529288 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2136 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2737 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.780417 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1965.775294 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2123 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2730 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.777656 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 4.024044 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1429.621147 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 536.884097 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.043629 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.060136 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2045 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 90 # 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number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 17 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 17 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2037 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 93 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2130 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2037 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 93 # number of overall hits +system.cpu.l2cache.overall_hits::total 2130 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2052 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2737 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65684.090909 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66162.775446 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -668,193 +766,193 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38106.668447 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45409.607143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39902.998902 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54679250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54679250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110944750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93185500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 204130250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110944750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93185500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 204130250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.501101 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.872727 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559992 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.501101 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.638842 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38106.668447 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38060.950829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38085.676030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38106.668447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38060.950829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38085.676030 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50864.418605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50864.418605 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54145.802831 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53340.297653 # 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number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46738642 # number of overall hits -system.cpu.dcache.overall_hits::total 46738642 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1903 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1903 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7738 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7738 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46730710 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46730710 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46730710 # number of overall hits +system.cpu.dcache.overall_hits::total 46730710 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1909 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1909 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7752 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7752 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9641 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9641 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9641 # number of overall misses -system.cpu.dcache.overall_misses::total 9641 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 93214000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 93214000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 305598496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 305598496 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 398812496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 398812496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 398812496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 398812496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34383996 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34383996 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9661 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9661 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9661 # number of overall misses +system.cpu.dcache.overall_misses::total 9661 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 115578500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 115578500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 443691996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 443691996 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 141000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 141000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 559270496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 559270496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 559270496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 559270496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34376084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34376084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22467 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22467 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46748283 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46748283 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46748283 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46748283 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000626 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000626 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 46740371 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46740371 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46740371 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46740371 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48982.658960 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48982.658960 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39493.214784 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39493.214784 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41366.299761 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41366.299761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41366.299761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41366.299761 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 527 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 67 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60544.002095 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60544.002095 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57235.809598 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57235.809598 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57889.503778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57889.503778 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 581 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 112 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 33.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.416667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 19 # number of writebacks -system.cpu.dcache.writebacks::total 19 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6648 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6648 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17 # number of writebacks +system.cpu.dcache.writebacks::total 17 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6669 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6669 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7776 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7776 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7776 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7776 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1090 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1865 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1865 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1865 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1865 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41130000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41130000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 50620998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 50620998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 91750998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 91750998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 91750998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 91750998 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7806 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7806 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7806 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7806 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 772 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 772 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1083 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1083 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1855 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1855 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1855 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1855 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49331013 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 49331013 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69111498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 69111498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118442511 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 118442511 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118442511 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 118442511 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53070.967742 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53070.967742 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46441.282569 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46441.282569 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63900.275907 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63900.275907 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63814.864266 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63814.864266 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index b26eb976b..24cdef337 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu sim_ticks 103106766000 # Number of ticks simulated final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1465257 # Simulator instruction rate (inst/s) -host_op_rate 1604314 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 876741604 # Simulator tick rate (ticks/s) -host_mem_usage 282008 # Number of bytes of host memory used -host_seconds 117.60 # Real time elapsed on the host +host_inst_rate 2813934 # Simulator instruction rate (inst/s) +host_op_rate 3080985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1683727447 # Simulator tick rate (ticks/s) +host_mem_usage 236772 # Number of bytes of host memory used +host_seconds 61.24 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 188670891 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 438893991 # Wr system.physmem.bw_total::cpu.inst 7365570985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1510925103 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 8876496088 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 8876496088 # Throughput (bytes/s) +system.membus.data_through_bus 915226805 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index b91e59a80..6b5d6bef1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu sim_ticks 232072304000 # Number of ticks simulated final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 817822 # Simulator instruction rate (inst/s) -host_op_rate 895603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1104464333 # Simulator tick rate (ticks/s) -host_mem_usage 290584 # Number of bytes of host memory used -host_seconds 210.12 # Real time elapsed on the host +host_inst_rate 1198657 # Simulator instruction rate (inst/s) +host_op_rate 1312657 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1618778979 # Simulator tick rate (ticks/s) +host_mem_usage 245268 # Number of bytes of host memory used +host_seconds 143.36 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 188185920 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 476817 # In system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 952255 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2361 # Transaction distribution +system.membus.trans_dist::ReadResp 2361 # Transaction distribution +system.membus.trans_dist::ReadExReq 1092 # Transaction distribution +system.membus.trans_dist::ReadExResp 1092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 6906 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 220992 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -414,5 +429,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1339169 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 6102 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3594 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 9696 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 195264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 115520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 310784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 8a8554f1f..806cadbfa 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu sim_ticks 96722945000 # Number of ticks simulated final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1868868 # Simulator instruction rate (inst/s) -host_op_rate 1868870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 934440193 # Simulator tick rate (ticks/s) -host_mem_usage 277724 # Number of bytes of host memory used -host_seconds 103.51 # Real time elapsed on the host +host_inst_rate 3763101 # Simulator instruction rate (inst/s) +host_op_rate 3763105 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1881563141 # Simulator tick rate (ticks/s) +host_mem_usage 229516 # Number of bytes of host memory used +host_seconds 51.41 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory @@ -35,6 +35,9 @@ system.physmem.bw_write::total 745070490 # Wr system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11057254439 # Throughput (bytes/s) +system.membus.data_through_bus 1069490213 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 193445891 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 75edc6876..a79e42f60 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu sim_ticks 270563082000 # Number of ticks simulated final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1012263 # Simulator instruction rate (inst/s) -host_op_rate 1012264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1415810765 # Simulator tick rate (ticks/s) -host_mem_usage 286308 # Number of bytes of host memory used -host_seconds 191.10 # Real time elapsed on the host +host_inst_rate 942019 # Simulator instruction rate (inst/s) +host_op_rate 942020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1317563963 # Simulator tick rate (ticks/s) +host_mem_usage 238020 # Number of bytes of host memory used +host_seconds 205.35 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 850848 # In system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 1223641 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4095 # Transaction distribution +system.membus.trans_dist::ReadResp 4095 # Transaction distribution +system.membus.trans_dist::ReadExReq 1078 # Transaction distribution +system.membus.trans_dist::ReadExResp 1078 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 10346 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 331072 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 541126164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -379,5 +394,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 3279915 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 24576 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 27730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 786432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 100992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 887424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 682644ea7..18746b39c 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144599 # Number of seconds simulated -sim_ticks 144599413000 # Number of ticks simulated -final_tick 144599413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144456 # Number of seconds simulated +sim_ticks 144456233500 # Number of ticks simulated +final_tick 144456233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53694 # Simulator instruction rate (inst/s) -host_op_rate 89995 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58787129 # Simulator tick rate (ticks/s) -host_mem_usage 325332 # Number of bytes of host memory used -host_seconds 2459.71 # Real time elapsed on the host +host_inst_rate 58579 # Simulator instruction rate (inst/s) +host_op_rate 98184 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64072469 # Simulator tick rate (ticks/s) +host_mem_usage 278680 # Number of bytes of host memory used +host_seconds 2254.58 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362962 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125312 # Number of bytes read from this memory -system.physmem.bytes_read::total 343104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3403 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 342592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1958 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1506175 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 866615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2372790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1506175 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1506175 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1506175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 866615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2372790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5365 # Total number of read requests seen +system.physmem.num_reads::total 5353 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1504123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 867474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2371597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1504123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1504123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1504123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 867474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2371597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5356 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5519 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 343104 # Total number of bytes read from memory +system.physmem.cpureqs 5495 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 342592 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 343104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 342592 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 154 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 322 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 281 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 370 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 377 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 366 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 249 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 139 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 357 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 448 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 380 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 210 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 283 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 144599380000 # Total gap between requests +system.physmem.totGap 144456205000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5365 # Categorize read packet sizes +system.physmem.readPktSize::6 5356 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,14 +149,79 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 15365500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 134288000 # Sum of mem lat for all requests -system.physmem.totBusLat 26825000 # Total cycles spent in databus access -system.physmem.totBankLat 92097500 # Total cycles spent in bank access -system.physmem.avgQLat 2864.03 # Average queueing delay per request -system.physmem.avgBankLat 17166.36 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25030.38 # Average memory access latency +system.physmem.bytesPerActivate::samples 510 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 662.337255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 234.191565 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1287.834177 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 176 34.51% 34.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 77 15.10% 49.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 39 7.65% 57.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 29 5.69% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 22 4.31% 67.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 12 2.35% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 18 3.53% 73.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 5 0.98% 74.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 13 2.55% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 6 1.18% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3 0.59% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 1.18% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 3 0.59% 80.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 6 1.18% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 7 1.37% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.20% 83.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 6 1.18% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.39% 85.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.39% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.39% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 6 1.18% 87.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.20% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.59% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.20% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.39% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.20% 89.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.39% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 3 0.59% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 3 0.59% 91.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 4 0.78% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.20% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 3 0.59% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 2 0.39% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.20% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.78% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.20% 94.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.20% 95.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.39% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.20% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.20% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.20% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.20% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 5 0.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 510 # Bytes accessed per row activation +system.physmem.totQLat 13729500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 120235750 # Sum of mem lat for all requests +system.physmem.totBusLat 26770000 # Total cycles spent in databus access +system.physmem.totBankLat 79736250 # Total cycles spent in bank access +system.physmem.avgQLat 2563.39 # Average queueing delay per request +system.physmem.avgBankLat 14887.28 # Average bank access latency per request +system.physmem.avgBusLat 4998.13 # Average bus latency per request +system.physmem.avgMemAccLat 22448.80 # Average memory access latency system.physmem.avgRdBW 2.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.37 # Average consumed read bandwidth in MB/s @@ -165,251 +230,272 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4467 # Number of row buffer hits during reads +system.physmem.readRowHits 4844 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26952354.15 # Average gap between requests -system.cpu.branchPred.lookups 18673504 # Number of BP lookups -system.cpu.branchPred.condPredicted 18673504 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1493262 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11432454 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10793701 # Number of BTB hits +system.physmem.avgGap 26970912.06 # Average gap between requests +system.membus.throughput 2371597 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3826 # Transaction distribution +system.membus.trans_dist::ReadResp 3823 # Transaction distribution +system.membus.trans_dist::UpgradeReq 139 # Transaction distribution +system.membus.trans_dist::UpgradeResp 139 # Transaction distribution +system.membus.trans_dist::ReadExReq 1530 # Transaction distribution +system.membus.trans_dist::ReadExResp 1530 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 10987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10987 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 342592 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 7029500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 50887361 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.branchPred.lookups 18668412 # Number of BP lookups +system.cpu.branchPred.condPredicted 18668412 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1491215 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11464480 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10808529 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.412809 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1324082 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 23521 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.278406 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1321942 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 23508 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 289482612 # number of cpu cycles simulated +system.cpu.numCycles 289199941 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23502455 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 207109778 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18673504 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12117783 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54283022 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15594841 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 178283916 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1444 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8051 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22396392 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 221801 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269918552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.268498 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.756525 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23489092 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206857811 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18668412 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12130471 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54260755 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15560780 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 178047703 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7863 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22383448 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 227467 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269615649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.269321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.757232 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 217073469 80.42% 80.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2850604 1.06% 81.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2315423 0.86% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2639736 0.98% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3229574 1.20% 84.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3384900 1.25% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3844403 1.42% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2562175 0.95% 88.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32018268 11.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216795166 80.41% 80.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2848237 1.06% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2316890 0.86% 82.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2640281 0.98% 83.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3221568 1.19% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3391687 1.26% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3836150 1.42% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2560999 0.95% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32004671 11.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269918552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064506 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.715448 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36985977 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167209662 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41646466 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10236820 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13839627 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336463810 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13839627 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45047343 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116751427 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 32413 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42745141 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51502601 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 330086802 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10951 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26152362 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22736681 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 256 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 382815435 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 919037508 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 910796649 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8240859 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269615649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064552 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.715276 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36944387 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167005183 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41608261 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10249032 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13808786 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336293429 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13808786 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45003701 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116679127 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28084 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42750473 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51345478 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329924152 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10957 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26042658 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22711387 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 324 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 382665072 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 918469595 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 910237815 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8231780 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428606 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 123386829 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2258 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2296 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105258591 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84679198 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30165066 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58703856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19098571 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 323202869 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4566 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260671940 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116724 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 101460757 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 211331898 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3321 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269918552 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.965743 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.342643 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 123236466 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2077 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2071 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105014998 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84558511 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30136347 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58291555 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18982732 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322974285 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4304 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260692143 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 115978 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 101227039 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 210564251 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3059 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269615649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.966903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.344359 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143572602 53.19% 53.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55645964 20.62% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34208859 12.67% 86.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19077068 7.07% 93.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10849323 4.02% 97.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4139320 1.53% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1825268 0.68% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 469630 0.17% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 130518 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143415763 53.19% 53.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55488403 20.58% 73.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34156757 12.67% 86.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19088088 7.08% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10888681 4.04% 97.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4144802 1.54% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1820810 0.68% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 476392 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 135953 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269918552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269615649 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 131441 4.84% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2279294 83.91% 88.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 305503 11.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130533 4.80% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2283697 84.00% 88.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 304445 11.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210514 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162160673 62.21% 62.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788045 0.30% 62.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035797 2.70% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1444934 0.55% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65461399 25.11% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22570578 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210883 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162146963 62.20% 62.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 788849 0.30% 62.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035772 2.70% 65.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1445624 0.55% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65501773 25.13% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22562279 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260671940 # Type of FU issued -system.cpu.iq.rate 0.900475 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2716238 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010420 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 789209442 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 421320217 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255304788 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4885952 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3632838 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2349442 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259718878 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2458786 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18858463 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260692143 # Type of FU issued +system.cpu.iq.rate 0.901425 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2718675 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010429 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 788942081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420863494 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255312010 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4892507 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3626050 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2350305 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259737433 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2462502 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18945833 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 28029611 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25725 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 290431 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9649349 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27908924 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26612 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 289609 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9620630 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49573 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 51419 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13839627 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 84981347 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5427028 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 323207435 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 136147 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84679198 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30165066 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2231 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2677235 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14355 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 290431 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 637937 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 905599 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1543536 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258899576 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64693791 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1772364 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13808786 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85007909 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5442016 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322978589 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 134528 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84558511 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30136347 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2042 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2673918 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13520 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 289609 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 642268 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 899522 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1541790 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258904579 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64718726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1787564 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87060323 # number of memory reference insts executed -system.cpu.iew.exec_branches 14273836 # Number of branches executed -system.cpu.iew.exec_stores 22366532 # Number of stores executed -system.cpu.iew.exec_rate 0.894353 # Inst execution rate -system.cpu.iew.wb_sent 258261406 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257654230 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206076672 # num instructions producing a value -system.cpu.iew.wb_consumers 369295783 # num instructions consuming a value +system.cpu.iew.exec_refs 87077956 # number of memory reference insts executed +system.cpu.iew.exec_branches 14272272 # Number of branches executed +system.cpu.iew.exec_stores 22359230 # Number of stores executed +system.cpu.iew.exec_rate 0.895244 # Inst execution rate +system.cpu.iew.wb_sent 258260440 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257662315 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206077428 # num instructions producing a value +system.cpu.iew.wb_consumers 369317966 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.890051 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.558026 # average fanout of values written-back +system.cpu.iew.wb_rate 0.890949 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557995 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101920014 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101692643 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1494473 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 256078925 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.864433 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.651734 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1492367 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255806863 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.865352 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.655114 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156603135 61.15% 61.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57289650 22.37% 83.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14093127 5.50% 89.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12068952 4.71% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4185763 1.63% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2969218 1.16% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 905577 0.35% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1050426 0.41% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6913077 2.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156513813 61.18% 61.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57168789 22.35% 83.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14010033 5.48% 89.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12060678 4.71% 93.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4174757 1.63% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2964012 1.16% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 898257 0.35% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1048749 0.41% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6967775 2.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 256078925 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255806863 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -420,198 +506,220 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339553 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6913077 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6967775 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 572448824 # The number of ROB reads -system.cpu.rob.rob_writes 660431667 # The number of ROB writes -system.cpu.timesIdled 5928357 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19564060 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571894693 # The number of ROB reads +system.cpu.rob.rob_writes 659945778 # The number of ROB writes +system.cpu.timesIdled 5917549 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19584292 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.191868 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.191868 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456232 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456232 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 554310914 # number of integer regfile reads -system.cpu.int_regfile_writes 293915019 # number of integer regfile writes -system.cpu.fp_regfile_reads 3215317 # number of floating regfile reads -system.cpu.fp_regfile_writes 2009393 # number of floating regfile writes -system.cpu.misc_regfile_reads 133439176 # number of misc regfile reads +system.cpu.cpi 2.189728 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.189728 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456678 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456678 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 554359034 # number of integer regfile reads +system.cpu.int_regfile_writes 293931276 # number of integer regfile writes +system.cpu.fp_regfile_reads 3216619 # number of floating regfile reads +system.cpu.fp_regfile_writes 2010069 # number of floating regfile writes +system.cpu.misc_regfile_reads 133442201 # number of misc regfile reads system.cpu.misc_regfile_writes 845 # number of misc regfile writes -system.cpu.icache.replacements 4633 # number of replacements -system.cpu.icache.tagsinuse 1627.424900 # Cycle average of tags in use -system.cpu.icache.total_refs 22387705 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6601 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3391.562642 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 3896100 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7244 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13426 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4292 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 17718 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 425152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 553920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 553920 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8896 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4481500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 10173000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3068000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 4678 # number of replacements +system.cpu.icache.tagsinuse 1622.603356 # Cycle average of tags in use +system.cpu.icache.total_refs 22374543 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6643 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3368.138341 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1627.424900 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.794641 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.794641 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22387705 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22387705 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22387705 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22387705 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22387705 # number of overall hits -system.cpu.icache.overall_hits::total 22387705 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8687 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8687 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8687 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8687 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8687 # number of overall misses -system.cpu.icache.overall_misses::total 8687 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 264464000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 264464000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 264464000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 264464000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 264464000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 264464000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22396392 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22396392 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22396392 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22396392 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22396392 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22396392 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30443.651433 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30443.651433 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30443.651433 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30443.651433 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30443.651433 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30443.651433 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 666 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1622.603356 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.792287 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.792287 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 22374545 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22374545 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22374545 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22374545 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22374545 # number of overall hits +system.cpu.icache.overall_hits::total 22374545 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8903 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8903 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8903 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8903 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8903 # number of overall misses +system.cpu.icache.overall_misses::total 8903 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 349961000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 349961000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 349961000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 349961000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 349961000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 349961000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22383448 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22383448 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22383448 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22383448 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22383448 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22383448 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39308.210715 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39308.210715 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39308.210715 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39308.210715 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39308.210715 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39308.210715 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1033 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.625000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.388889 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1931 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1931 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1931 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1931 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1931 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1931 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6756 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6756 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6756 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6756 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6756 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6756 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203573500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203573500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203573500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203573500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203573500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203573500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000302 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000302 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000302 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30132.252812 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30132.252812 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30132.252812 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 30132.252812 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30132.252812 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 30132.252812 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2120 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2120 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2120 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2120 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2120 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2120 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6783 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6783 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6783 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6783 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6783 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6783 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262758000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 262758000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262758000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 262758000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262758000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 262758000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38737.726670 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38737.726670 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38737.726670 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38737.726670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38737.726670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38737.726670 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2558.702101 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3231 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3835 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.842503 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2546.215814 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3285 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3827 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.858375 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1.875617 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2246.028041 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 310.798443 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000057 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.068543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.009485 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.078085 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3198 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 28 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3226 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 1.835149 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2229.080076 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 315.300590 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000056 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.068026 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.009622 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.077704 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3248 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3282 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3198 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 35 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3233 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3198 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 35 # number of overall hits -system.cpu.l2cache.overall_hits::total 3233 # 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number of replacements -system.cpu.dcache.tagsinuse 1433.982512 # Cycle average of tags in use -system.cpu.dcache.total_refs 66194680 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1993 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33213.587556 # Average number of references to valid blocks. +system.cpu.dcache.replacements 56 # number of replacements +system.cpu.dcache.tagsinuse 1435.278677 # Cycle average of tags in use +system.cpu.dcache.total_refs 66130970 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1999 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33082.026013 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1433.982512 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.350093 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.350093 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45680422 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45680422 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514038 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514038 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66194460 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66194460 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66194460 # number of overall hits -system.cpu.dcache.overall_hits::total 66194460 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 872 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 872 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1693 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1693 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2565 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2565 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2565 # number of overall misses -system.cpu.dcache.overall_misses::total 2565 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 43604500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 43604500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76098000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76098000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 119702500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 119702500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 119702500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 119702500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45681294 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45681294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1435.278677 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.350410 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.350410 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 45616715 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45616715 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514054 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514054 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66130769 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66130769 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66130769 # number of overall hits +system.cpu.dcache.overall_hits::total 66130769 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 933 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 933 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1677 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1677 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses +system.cpu.dcache.overall_misses::total 2610 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56235500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56235500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104835500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104835500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 161071000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 161071000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 161071000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 161071000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45617648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45617648 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66197025 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66197025 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66197025 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66197025 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 66133379 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66133379 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66133379 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66133379 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50005.160550 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50005.160550 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44948.611931 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44948.611931 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46667.641326 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46667.641326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46667.641326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46667.641326 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 170 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60273.847803 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60273.847803 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62513.714967 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62513.714967 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61713.026820 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61713.026820 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 414 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 414 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 415 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 415 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 415 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 415 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 458 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1692 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1692 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2150 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2150 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2150 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2150 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26607000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26607000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 72678500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 72678500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 99285500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 99285500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 99285500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 99285500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 467 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 466 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 466 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1675 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1675 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32012500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32012500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101366000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 101366000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133378500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 133378500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133378500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 133378500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses @@ -772,14 +880,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58093.886463 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58093.886463 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42954.196217 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42954.196217 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46179.302326 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46179.302326 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46179.302326 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46179.302326 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68696.351931 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68696.351931 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60517.014925 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60517.014925 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 817f7471e..4a8749fb9 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -33,6 +33,9 @@ system.physmem.bw_write::total 759721898 # Wr system.physmem.bw_total::cpu.inst 10563380223 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3122279959 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13685660183 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13685660183 # Throughput (bytes/s) +system.membus.data_through_bus 1798200879 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 262786137 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index cfc0b5abb..de904232a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -27,6 +27,25 @@ system.physmem.bw_inst_read::total 724276 # In system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 1207552 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3160 # Transaction distribution +system.membus.trans_dist::ReadResp 3160 # Transaction distribution +system.membus.trans_dist::ReadExReq 1575 # Transaction distribution +system.membus.trans_dist::ReadExResp 1575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 303040 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 501907914 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -364,5 +383,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1684707 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 9388 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 13205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 300416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 122368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 422784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |