diff options
Diffstat (limited to 'tests/long/se')
19 files changed, 13397 insertions, 13226 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 5d8366912..6e907f4cc 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,96 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026877 # Number of seconds simulated -sim_ticks 26877484000 # Number of ticks simulated -final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026913 # Number of seconds simulated +sim_ticks 26912680500 # Number of ticks simulated +final_tick 26912680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158705 # Simulator instruction rate (inst/s) -host_op_rate 159844 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47086787 # Simulator tick rate (ticks/s) -host_mem_usage 380172 # Number of bytes of host memory used -host_seconds 570.81 # Real time elapsed on the host +host_inst_rate 145850 # Simulator instruction rate (inst/s) +host_op_rate 146897 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43329539 # Simulator tick rate (ticks/s) +host_mem_usage 407732 # Number of bytes of host memory used +host_seconds 621.12 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory -system.physmem.bytes_read::total 992384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44928 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 702 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15506 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1671585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35250919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36922504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1671585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1671585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15506 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15506 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 992384 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 899 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 865 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 876 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 896 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26877282500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15506 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 11153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory +system.physmem.bytes_read::total 992896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1681289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35211951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36893241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1681289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1681289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1681289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35211951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36893241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15514 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 988 # Per bank write bursts +system.physmem.perBankRdBursts::1 886 # Per bank write bursts +system.physmem.perBankRdBursts::2 943 # Per bank write bursts +system.physmem.perBankRdBursts::3 1028 # Per bank write bursts +system.physmem.perBankRdBursts::4 1049 # Per bank write bursts +system.physmem.perBankRdBursts::5 1105 # Per bank write bursts +system.physmem.perBankRdBursts::6 1078 # Per bank write bursts +system.physmem.perBankRdBursts::7 1078 # Per bank write bursts +system.physmem.perBankRdBursts::8 1024 # Per bank write bursts +system.physmem.perBankRdBursts::9 956 # Per bank write bursts +system.physmem.perBankRdBursts::10 938 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 904 # Per bank write bursts +system.physmem.perBankRdBursts::13 865 # Per bank write bursts +system.physmem.perBankRdBursts::14 877 # Per bank write bursts +system.physmem.perBankRdBursts::15 896 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 26912480500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 15514 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 11168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,90 +152,163 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3465.405018 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 823.463699 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3831.282142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 68 24.37% 24.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 22 7.89% 32.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 15 5.38% 37.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 12 4.30% 41.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 10 3.58% 45.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 6 2.15% 47.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 2 0.72% 48.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 2 0.72% 49.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 2 0.72% 49.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3 1.08% 50.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1 0.36% 51.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 4 1.43% 52.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1 0.36% 53.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1 0.36% 53.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1 0.36% 53.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 2 0.72% 54.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.36% 54.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 1 0.36% 55.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.72% 55.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.36% 56.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.36% 56.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.72% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.36% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.72% 58.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.72% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.36% 59.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.36% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.36% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.36% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.36% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.36% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 108 38.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 279 # Bytes accessed per row activation -system.physmem.totQLat 38456500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 288012750 # Sum of mem lat for all requests -system.physmem.totBusLat 77530000 # Total cycles spent in databus access -system.physmem.totBankLat 172026250 # Total cycles spent in bank access -system.physmem.avgQLat 2480.10 # Average queueing delay per request -system.physmem.avgBankLat 11094.17 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18574.28 # Average memory access latency -system.physmem.avgRdBW 36.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 36.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1603.423015 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 482.832317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2202.245443 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 156 25.28% 25.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 69 11.18% 36.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 40 6.48% 42.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 21 3.40% 46.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 12 1.94% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 6 0.97% 49.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 26 4.21% 53.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 13 2.11% 55.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 0.81% 56.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 9 1.46% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.65% 58.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 0.65% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.81% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 1.30% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.49% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.49% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.49% 64.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 19 3.08% 69.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.49% 71.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.49% 72.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 3 0.49% 75.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 3 0.49% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 3 0.49% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 3 0.49% 81.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.49% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.16% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 3 0.49% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 2 0.32% 83.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 3 0.49% 84.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 3 0.49% 86.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 5 0.81% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.49% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 7 1.13% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 2 0.32% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.49% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.49% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 3 0.49% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.32% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 12 1.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 617 # Bytes accessed per row activation +system.physmem.totQLat 103133500 # Total ticks spent queuing +system.physmem.totMemAccLat 356414750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers +system.physmem.totBankLat 175711250 # Total ticks spent accessing banks +system.physmem.avgQLat 6647.77 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11325.98 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 22973.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15227 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 14897 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 98.20 # Row buffer hit rate for reads +system.physmem.readRowHitRate 96.02 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1733347.25 # Average gap between requests -system.membus.throughput 36922504 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 968 # Transaction distribution -system.membus.trans_dist::ReadResp 968 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.physmem.avgGap 1734722.22 # Average gap between requests +system.physmem.pageHitRate 96.02 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.95 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 36893241 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 976 # Transaction distribution +system.membus.trans_dist::ReadResp 976 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31016 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992384 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 992384 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992384 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31028 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 992896 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19247000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145109998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145153250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.branchPred.lookups 26677800 # Number of BP lookups -system.cpu.branchPred.condPredicted 21997882 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 841974 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11370900 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11281126 # Number of BTB hits +system.cpu.branchPred.lookups 26684421 # Number of BP lookups +system.cpu.branchPred.condPredicted 22003515 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 842640 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11361703 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11279248 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.210493 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69875 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 190 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.274273 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 70578 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 175 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -277,134 +352,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53754969 # number of cpu cycles simulated +system.cpu.numCycles 53825362 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14167360 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127859416 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26677800 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11351001 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24030535 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4760658 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11306613 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 14170521 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127888749 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26684421 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11349826 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24033756 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4765472 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11324127 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13839893 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329843 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53406892 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.410540 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214942 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13841798 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 328713 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53434811 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.409872 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214791 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29414657 55.08% 55.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3389704 6.35% 61.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2028213 3.80% 65.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1552667 2.91% 68.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1667858 3.12% 71.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2917621 5.46% 76.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1511775 2.83% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090045 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9834352 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29439353 55.09% 55.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3386965 6.34% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028576 3.80% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1554110 2.91% 68.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1668608 3.12% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2917595 5.46% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1511603 2.83% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1091436 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9836565 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53406892 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.496285 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.378560 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16930336 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9153085 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22398033 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031812 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3893626 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4442083 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8660 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126043342 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42618 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3893626 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18711323 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3589161 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 177598 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21546569 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5488615 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123125799 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 427703 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4597767 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1304 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143579240 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536319966 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 499912232 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 925 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53434811 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.495759 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.375994 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16934142 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9169646 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22402191 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1031199 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3897633 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4442994 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8719 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126071688 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42592 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3897633 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18714767 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3594336 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 187938 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21550636 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5489501 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123153089 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 427273 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4600360 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1278 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143605134 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536434214 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 500014017 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 784 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36165054 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4615 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4613 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12549588 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29468785 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5519570 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2135216 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1252898 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118144684 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8486 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105149299 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26716988 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65524839 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 268 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53406892 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.968834 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.909318 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36190948 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4612 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4610 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12546346 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29477793 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5522687 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2151443 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1269536 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118168344 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8478 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105154526 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78994 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26741749 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65618769 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 260 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53434811 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.908534 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15356551 28.75% 28.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11649216 21.81% 50.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8254544 15.46% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6822524 12.77% 78.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4944372 9.26% 88.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2950581 5.52% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2452903 4.59% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 533996 1.00% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 442205 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15376938 28.78% 28.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11654897 21.81% 50.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8243564 15.43% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6824643 12.77% 78.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4966766 9.30% 88.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2946722 5.51% 93.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2453138 4.59% 98.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 526074 0.98% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442069 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53406892 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53434811 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45764 6.91% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 341696 51.58% 58.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 274978 41.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45800 6.91% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340417 51.39% 58.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 276226 41.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74418524 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74421271 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued @@ -426,90 +501,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 156 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 210 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25604703 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5114728 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25608548 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5113387 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105149299 # Type of FU issued -system.cpu.iq.rate 1.956085 # Inst issue rate -system.cpu.iq.fu_busy_cnt 662465 # FU busy when requested +system.cpu.iq.FU_type_0::total 105154526 # Type of FU issued +system.cpu.iq.rate 1.953624 # Inst issue rate +system.cpu.iq.fu_busy_cnt 662470 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264446249 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144874513 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102679810 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 818 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1193 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 350 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105811363 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 401 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 442313 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 264484578 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144923147 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102682900 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 749 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 323 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105816623 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 441366 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6894819 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6564 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6306 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 774726 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6903827 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6492 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6312 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 777843 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31505 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31495 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3893626 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 957081 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 126869 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118165864 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309166 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29468785 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5519570 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4598 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65994 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6719 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6306 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446848 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 444951 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 891799 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104175749 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25286286 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 973550 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3897633 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 959563 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 126871 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118189516 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 310121 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29477793 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5522687 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4590 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65719 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6709 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6312 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446751 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446217 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892968 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104180481 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25289750 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 974045 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12694 # number of nop insts executed -system.cpu.iew.exec_refs 30344072 # number of memory reference insts executed -system.cpu.iew.exec_branches 21323909 # Number of branches executed -system.cpu.iew.exec_stores 5057786 # Number of stores executed -system.cpu.iew.exec_rate 1.937974 # Inst execution rate -system.cpu.iew.wb_sent 102957516 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102680160 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62240823 # num instructions producing a value -system.cpu.iew.wb_consumers 104288348 # num instructions consuming a value +system.cpu.iew.exec_refs 30346354 # number of memory reference insts executed +system.cpu.iew.exec_branches 21325110 # Number of branches executed +system.cpu.iew.exec_stores 5056604 # Number of stores executed +system.cpu.iew.exec_rate 1.935528 # Inst execution rate +system.cpu.iew.wb_sent 102961531 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102683223 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62241416 # num instructions producing a value +system.cpu.iew.wb_consumers 104299638 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.910152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596815 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907711 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596756 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26915742 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26939491 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 833391 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49513266 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.843000 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540951 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 834010 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49537178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.842111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.540648 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20021121 40.44% 40.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13151741 26.56% 67.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4165163 8.41% 75.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3429722 6.93% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1536672 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 726445 1.47% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 951437 1.92% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253528 0.51% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5277437 10.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20048697 40.47% 40.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13146284 26.54% 67.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4166513 8.41% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3429547 6.92% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1533299 3.10% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 729419 1.47% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 954733 1.93% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253168 0.51% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275518 10.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49513266 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49537178 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -520,222 +595,218 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5277437 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275518 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162398797 # The number of ROB reads -system.cpu.rob.rob_writes 240250691 # The number of ROB writes -system.cpu.timesIdled 46136 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 348077 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162448377 # The number of ROB reads +system.cpu.rob.rob_writes 240302265 # The number of ROB writes +system.cpu.timesIdled 46020 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 390551 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.593389 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.593389 # CPI: Total CPI of All Threads -system.cpu.ipc 1.685236 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.685236 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495533268 # number of integer regfile reads -system.cpu.int_regfile_writes 120542090 # number of integer regfile writes -system.cpu.fp_regfile_reads 173 # number of floating regfile reads -system.cpu.fp_regfile_writes 448 # number of floating regfile writes -system.cpu.misc_regfile_reads 29087390 # number of misc regfile reads +system.cpu.cpi 0.594166 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.594166 # CPI: Total CPI of All Threads +system.cpu.ipc 1.683032 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.683032 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495553334 # number of integer regfile reads +system.cpu.int_regfile_writes 120547287 # number of integer regfile writes +system.cpu.fp_regfile_reads 170 # number of floating regfile reads +system.cpu.fp_regfile_writes 410 # number of floating regfile writes +system.cpu.misc_regfile_reads 29088502 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4503454862 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1454 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838179 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839633 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120994944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121041344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4497529557 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43698 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838143 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888541000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1225499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424134990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 633.195127 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13840808 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 732 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18908.207650 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13838909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13838909 # number of overall hits -system.cpu.icache.overall_hits::total 13838909 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses -system.cpu.icache.overall_misses::total 983 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64555998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64555998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64555998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64555998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64555998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64555998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13839892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13839892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13839892 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13839892 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13839892 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13839892 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 633.195127 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.309177 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.309177 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13840808 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13840808 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13840808 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13840808 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13840808 # number of overall hits +system.cpu.icache.overall_hits::total 13840808 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 989 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 989 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 989 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 989 # number of overall misses +system.cpu.icache.overall_misses::total 989 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66791248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66791248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66791248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66791248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66791248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66791248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13841797 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13841797 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13841797 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13841797 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13841797 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13841797 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65672.429298 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65672.429298 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65672.429298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65672.429298 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 629 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67534.123357 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67534.123357 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67534.123357 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67534.123357 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 596 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.900000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 54.181818 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 729 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 729 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 729 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 729 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 729 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 729 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49190750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49190750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49190750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49190750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49190750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49190750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 256 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 256 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 256 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 256 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 256 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 256 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50590750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50590750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50590750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50590750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50590750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50590750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67477.023320 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67477.023320 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69018.758527 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69018.758527 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10730.387703 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831429 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15497 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 118.179583 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9885.972786 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.301696 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018743 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006997 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903615 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903638 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942919 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942919 # number of Writeback hits +system.cpu.l2cache.tags.occ_blocks::writebacks 9881.039169 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 619.212620 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 230.135914 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.301545 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018897 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007023 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.327465 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903638 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903662 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942911 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942911 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943531 # number of replacements -system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23597130 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23597130 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532905 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532905 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3915 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3915 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 943519 # number of replacements +system.cpu.dcache.tags.tagsinuse 3671.753264 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28141899 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947615 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.697608 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8006034000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.753264 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896424 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896424 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23601231 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23601231 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4532867 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4532867 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28130035 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28130035 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28130035 # number of overall hits -system.cpu.dcache.overall_hits::total 28130035 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173788 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173788 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202076 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202076 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1375864 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1375864 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1375864 # number of overall misses -system.cpu.dcache.overall_misses::total 1375864 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887695479 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13887695479 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7918602355 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7918602355 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 251250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21806297834 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21806297834 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21806297834 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21806297834 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24770918 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24770918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 28134098 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28134098 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28134098 # number of overall hits +system.cpu.dcache.overall_hits::total 28134098 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173780 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173780 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202114 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202114 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1375894 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1375894 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1375894 # number of overall misses +system.cpu.dcache.overall_misses::total 1375894 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893621478 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13893621478 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458573839 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8458573839 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22352195317 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22352195317 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22352195317 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22352195317 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24775011 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24775011 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3923 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3923 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3917 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3917 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29505899 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29505899 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29505899 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29505899 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047386 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047386 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042677 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042677 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002039 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002039 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046630 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046630 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046630 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046630 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.519388 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.519388 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39186.258413 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39186.258413 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31406.250000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31406.250000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15849.166657 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15849.166657 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154131 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29509992 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29509992 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29509992 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29509992 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047378 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047378 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042685 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042685 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.648672 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.648672 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41850.509312 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41850.509312 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16245.579468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16245.579468 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154256 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23950 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.435532 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.440483 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942919 # number of writebacks -system.cpu.dcache.writebacks::total 942919 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269877 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269877 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158357 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158357 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428234 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428234 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428234 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428234 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903911 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903911 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43719 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43719 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947630 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947630 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947630 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947630 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9992457010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9992457010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254142688 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254142688 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11246599698 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11246599698 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11246599698 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11246599698 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036491 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036491 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009233 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009233 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.691236 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.691236 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28686.444978 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28686.444978 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks +system.cpu.dcache.writebacks::total 942911 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269842 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269842 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158436 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158436 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 428278 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428278 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428278 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428278 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903938 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903938 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43678 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43678 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947616 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947616 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947616 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947616 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994572760 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994572760 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319332173 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319332173 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313904933 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11313904933 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313904933 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11313904933 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032112 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032112 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.701632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.701632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30205.874193 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30205.874193 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 3b6f53bfa..1149689b6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,102 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065497 # Number of seconds simulated -sim_ticks 65497052500 # Number of ticks simulated -final_tick 65497052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065614 # Number of seconds simulated +sim_ticks 65613727000 # Number of ticks simulated +final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99498 # Simulator instruction rate (inst/s) -host_op_rate 175200 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41248682 # Simulator tick rate (ticks/s) -host_mem_usage 388584 # Number of bytes of host memory used -host_seconds 1587.86 # Real time elapsed on the host +host_inst_rate 90206 # Simulator instruction rate (inst/s) +host_op_rate 158838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37463203 # Simulator tick rate (ticks/s) +host_mem_usage 416624 # Number of bytes of host memory used +host_seconds 1751.42 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 63296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882240 # Number of bytes read from this memory -system.physmem.bytes_read::total 1945536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63296 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9984 # Number of bytes written to this memory -system.physmem.bytes_written::total 9984 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29410 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30399 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 156 # Number of write requests responded to by this memory -system.physmem.num_writes::total 156 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 966395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28737782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29704176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 966395 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 966395 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 152434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 152434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 152434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 966395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28737782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29856611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30400 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 156 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 30400 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 156 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 1945536 # Total number of bytes read from memory -system.physmem.bytesWritten 9984 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1945536 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9984 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2025 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1898 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1932 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1820 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 14 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 65497035500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30400 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 156 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 29908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10688 # Number of bytes written to this memory +system.physmem.bytes_written::total 10688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30418 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 167 # Number of write requests responded to by this memory +system.physmem.num_writes::total 167 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 969553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28700336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29669889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 969553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 969553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 162893 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 162893 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 162893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 969553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28700336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29832782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30419 # Number of read requests accepted +system.physmem.writeReqs 167 # Number of write requests accepted +system.physmem.readBursts 30419 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 167 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1943936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2880 # Total number of bytes read from write queue +system.physmem.bytesWritten 9856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1946816 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 45 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1928 # Per bank write bursts +system.physmem.perBankRdBursts::1 2077 # Per bank write bursts +system.physmem.perBankRdBursts::2 2029 # Per bank write bursts +system.physmem.perBankRdBursts::3 1927 # Per bank write bursts +system.physmem.perBankRdBursts::4 2026 # Per bank write bursts +system.physmem.perBankRdBursts::5 1899 # Per bank write bursts +system.physmem.perBankRdBursts::6 1963 # Per bank write bursts +system.physmem.perBankRdBursts::7 1862 # Per bank write bursts +system.physmem.perBankRdBursts::8 1939 # Per bank write bursts +system.physmem.perBankRdBursts::9 1933 # Per bank write bursts +system.physmem.perBankRdBursts::10 1805 # Per bank write bursts +system.physmem.perBankRdBursts::11 1795 # Per bank write bursts +system.physmem.perBankRdBursts::12 1792 # Per bank write bursts +system.physmem.perBankRdBursts::13 1800 # Per bank write bursts +system.physmem.perBankRdBursts::14 1821 # Per bank write bursts +system.physmem.perBankRdBursts::15 1778 # Per bank write bursts +system.physmem.perBankWrBursts::0 15 # Per bank write bursts +system.physmem.perBankWrBursts::1 95 # Per bank write bursts +system.physmem.perBankWrBursts::2 7 # Per bank write bursts +system.physmem.perBankWrBursts::3 11 # Per bank write bursts +system.physmem.perBankWrBursts::4 6 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 12 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 5 # Per bank write bursts +system.physmem.perBankWrBursts::10 3 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 65613689500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 30419 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 167 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -125,29 +127,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -157,331 +159,386 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 535 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3610.915888 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 887.471357 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3852.235562 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 128 23.93% 23.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 47 8.79% 32.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 24 4.49% 37.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 12 2.24% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 11 2.06% 41.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 11 2.06% 43.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8 1.50% 45.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 3 0.56% 45.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.68% 47.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 10 1.87% 49.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2 0.37% 49.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 7 1.31% 50.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1 0.19% 51.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 3 0.56% 51.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.56% 52.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1 0.19% 52.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 9 1.68% 54.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.37% 54.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.19% 54.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.19% 54.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.19% 54.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.37% 55.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 1 0.19% 55.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.19% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.37% 56.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.19% 56.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.37% 56.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.19% 56.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.19% 57.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.19% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.37% 57.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.19% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.19% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.19% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.19% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.19% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.37% 58.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.19% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.37% 59.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.19% 59.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.19% 59.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 215 40.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 535 # Bytes accessed per row activation -system.physmem.totQLat 5969250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 581474250 # Sum of mem lat for all requests -system.physmem.totBusLat 151785000 # Total cycles spent in databus access -system.physmem.totBankLat 423720000 # Total cycles spent in bank access -system.physmem.avgQLat 196.64 # Average queueing delay per request -system.physmem.avgBankLat 13957.90 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19154.54 # Average memory access latency -system.physmem.avgRdBW 29.70 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.70 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 1275 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1527.767843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 562.023414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1657.823974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 326 25.57% 25.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 105 8.24% 33.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 43 3.37% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 28 2.20% 39.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 22 1.73% 41.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 22 1.73% 42.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 19 1.49% 44.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 15 1.18% 45.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 17 1.33% 46.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 13 1.02% 47.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 46 3.61% 51.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 12 0.94% 52.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 8 0.63% 53.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 7 0.55% 53.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 12 0.94% 54.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 11 0.86% 55.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 8 0.63% 56.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 16 1.25% 57.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 7 0.55% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 9 0.71% 58.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 9 0.71% 59.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 7 0.55% 59.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 11 0.86% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 6 0.47% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 14 1.10% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 4 0.31% 62.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 9 0.71% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 6 0.47% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 3 0.24% 63.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 12 0.94% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 12 0.94% 65.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 8 0.63% 66.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 32 2.51% 68.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 7 0.55% 69.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 7 0.55% 70.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 5 0.39% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 6 0.47% 70.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 10 0.78% 71.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 5 0.39% 72.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 7 0.55% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 3 0.24% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 9 0.71% 73.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 7 0.55% 74.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 6 0.47% 74.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 5 0.39% 74.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 11 0.86% 75.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 9 0.71% 76.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 7 0.55% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 5 0.39% 77.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 5 0.39% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 8 0.63% 78.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 11 0.86% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 9 0.71% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 10 0.78% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 12 0.94% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 15 1.18% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 10 0.78% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 14 1.10% 84.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 9 0.71% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 8 0.63% 86.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 8 0.63% 86.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 15 1.18% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 13 1.02% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 11 0.86% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 21 1.65% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 10 0.78% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 6 0.47% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 7 0.55% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 4 0.31% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 5 0.39% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 4 0.31% 94.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 4 0.31% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 6 0.47% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 7 0.55% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 5 0.39% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 6 0.47% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 5 0.39% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 6 0.47% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 5 0.39% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 6 0.47% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 4 0.31% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 2 0.16% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 2 0.16% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 2 0.16% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 2 0.16% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568 1 0.08% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 1 0.08% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 1 0.08% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 1 0.08% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080 1 0.08% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208 1 0.08% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592 1 0.08% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656 3 0.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1275 # Bytes accessed per row activation +system.physmem.totQLat 92483500 # Total ticks spent queuing +system.physmem.totMemAccLat 678771000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151870000 # Total ticks spent in databus transfers +system.physmem.totBankLat 434417500 # Total ticks spent accessing banks +system.physmem.avgQLat 3044.82 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14302.28 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 22347.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.67 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.16 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 12.39 # Average write queue length over time -system.physmem.readRowHits 29864 # Number of row buffer hits during reads -system.physmem.writeRowHits 96 # Number of row buffer hits during writes -system.physmem.readRowHitRate 98.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.54 # Row buffer hit rate for writes -system.physmem.avgGap 2143508.17 # Average gap between requests -system.membus.throughput 29855634 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1399 # Transaction distribution -system.membus.trans_dist::ReadResp 1397 # Transaction distribution -system.membus.trans_dist::Writeback 156 # Transaction distribution -system.membus.trans_dist::ReadExReq 29001 # Transaction distribution -system.membus.trans_dist::ReadExResp 29001 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60954 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60954 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60954 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1955456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1955456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1955456 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1955456 # Total data (bytes) +system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.96 # Average write queue length when enqueuing +system.physmem.readRowHits 29156 # Number of row buffer hits during reads +system.physmem.writeRowHits 97 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes +system.physmem.avgGap 2145219.69 # Average gap between requests +system.physmem.pageHitRate 95.78 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.92 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 29832782 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1416 # Transaction distribution +system.membus.trans_dist::ReadResp 1415 # Transaction distribution +system.membus.trans_dist::Writeback 167 # Transaction distribution +system.membus.trans_dist::ReadExReq 29003 # Transaction distribution +system.membus.trans_dist::ReadExResp 29003 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61004 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61004 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61004 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1957440 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 35006500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284183250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.branchPred.lookups 33858224 # Number of BP lookups -system.cpu.branchPred.condPredicted 33858224 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 774589 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19295548 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19203800 # Number of BTB hits +system.cpu.branchPred.lookups 33859770 # Number of BP lookups +system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 774913 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19306649 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19202709 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.524512 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5017950 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5443 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.461636 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5016745 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5399 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 130994109 # number of cpu cycles simulated +system.cpu.numCycles 131227460 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26134025 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182258914 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33858224 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24221750 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55458228 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5352681 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 44757241 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 354 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 26135230 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182265293 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33859770 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24219454 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55459629 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5354571 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 44982751 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 314 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25574362 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 166199 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 130892614 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.454818 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314961 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 25575393 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 166244 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131122211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.450609 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.313707 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77910684 59.52% 59.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1961091 1.50% 61.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2941416 2.25% 63.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3833946 2.93% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7767539 5.93% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757616 3.63% 75.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2666164 2.04% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1316720 1.01% 78.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27737438 21.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78139546 59.59% 59.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1960111 1.49% 61.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2942175 2.24% 63.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3833696 2.92% 66.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7767416 5.92% 72.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757872 3.63% 75.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2665225 2.03% 77.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1316047 1.00% 78.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27740123 21.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 130892614 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258471 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.391352 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36819659 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36980368 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43894473 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8655405 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4542709 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318839804 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4542709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42306626 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9548363 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7363 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46754553 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27733000 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 314999780 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26808 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25879667 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 317173158 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836491506 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 515038229 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 344 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131122211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258024 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.388926 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36831320 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37195756 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43906245 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8644656 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4544234 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318852911 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4544234 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42322552 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9742718 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7418 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46754999 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27750290 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 315016174 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 215 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26317 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25895473 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 317188133 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836523485 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 515056961 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 484 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37960411 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 37975386 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 483 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62657657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101560400 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34776362 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39636404 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5873969 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311477073 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1619 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300261813 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 90477 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32704303 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46143152 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1174 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 130892614 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.293955 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.698909 # Number of insts issued each cycle +system.cpu.rename.skidInsts 62628696 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101555761 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24143436 18.45% 18.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23235636 17.75% 36.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25474582 19.46% 55.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25828603 19.73% 75.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18887958 14.43% 89.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8220714 6.28% 96.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3961121 3.03% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 955436 0.73% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 185128 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 130892614 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131122211 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31366 1.52% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1915737 93.06% 94.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 111488 5.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31436 1.53% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169828970 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11213 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97302750 32.41% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33087237 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300261813 # Type of FU issued -system.cpu.iq.rate 2.292178 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2058591 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733564971 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344215080 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298003281 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 337 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 435 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 126 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302288959 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 169 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54190051 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued +system.cpu.iq.rate 2.288206 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10781015 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32177 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33336 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3336610 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3220 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4542709 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2622554 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 162089 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311478692 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 196017 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101560400 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34776362 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 469 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2626 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33336 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393441 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 427689 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 821130 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298856938 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96890588 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1404875 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129814899 # number of memory reference insts executed -system.cpu.iew.exec_branches 30818444 # Number of branches executed -system.cpu.iew.exec_stores 32924311 # Number of stores executed -system.cpu.iew.exec_rate 2.281453 # Inst execution rate -system.cpu.iew.wb_sent 298373185 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298003407 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218253384 # num instructions producing a value -system.cpu.iew.wb_consumers 296750864 # num instructions consuming a value +system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed +system.cpu.iew.exec_branches 30820824 # Number of branches executed +system.cpu.iew.exec_stores 32925944 # Number of stores executed +system.cpu.iew.exec_rate 2.277516 # Inst execution rate +system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218260008 # num instructions producing a value +system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.274937 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735477 # average fanout of values written-back +system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33298978 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 774634 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126349905 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.201762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.972659 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.197795 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.970921 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58072656 45.96% 45.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19155409 15.16% 61.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11632100 9.21% 70.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9445412 7.48% 77.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1855076 1.47% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2067896 1.64% 80.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1301136 1.03% 81.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 691741 0.55% 82.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22128479 17.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58251121 46.02% 46.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19170530 15.15% 61.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11719383 9.26% 70.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9409192 7.43% 77.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1839491 1.45% 79.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2078967 1.64% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1287907 1.02% 81.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 695737 0.55% 82.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22125649 17.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126349905 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126577977 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -492,214 +549,214 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22128479 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415712868 # The number of ROB reads -system.cpu.rob.rob_writes 627529396 # The number of ROB writes -system.cpu.timesIdled 13705 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 101495 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 415950983 # The number of ROB reads +system.cpu.rob.rob_writes 627545403 # The number of ROB writes +system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.829137 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.829137 # CPI: Total CPI of All Threads -system.cpu.ipc 1.206074 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.206074 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 483722109 # number of integer regfile reads -system.cpu.int_regfile_writes 234582139 # number of integer regfile writes -system.cpu.fp_regfile_reads 117 # number of floating regfile reads -system.cpu.fp_regfile_writes 75 # number of floating regfile writes -system.cpu.cc_regfile_reads 107053198 # number of cc regfile reads -system.cpu.cc_regfile_writes 64000024 # number of cc regfile writes -system.cpu.misc_regfile_reads 191821503 # number of misc regfile reads +system.cpu.cpi 0.830614 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads +system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 483744134 # number of integer regfile reads +system.cpu.int_regfile_writes 234595253 # number of integer regfile writes +system.cpu.fp_regfile_reads 141 # number of floating regfile reads +system.cpu.fp_regfile_writes 77 # number of floating regfile writes +system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads +system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes +system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4049501312 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995298 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82299 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2012 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219810 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221822 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265166016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 265230400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265230400 # Total data (bytes) +system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995298 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066887 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82323 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2022 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6220108 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6222130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265183808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 265248512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265248512 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4138743500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4139141500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1699750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1689999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3122104250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3122002000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 55 # number of replacements -system.cpu.icache.tags.tagsinuse 816.683247 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25573067 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1006 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25420.543738 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 57 # number of replacements +system.cpu.icache.tags.tagsinuse 819.642194 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25574088 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1011 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25295.833828 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 816.683247 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.398771 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.398771 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25573067 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25573067 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25573067 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25573067 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25573067 # number of overall hits -system.cpu.icache.overall_hits::total 25573067 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1295 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1295 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1295 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1295 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1295 # number of overall misses -system.cpu.icache.overall_misses::total 1295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 85604250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 85604250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 85604250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 85604250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 85604250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 85604250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25574362 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25574362 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25574362 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25574362 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25574362 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25574362 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 819.642194 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.400216 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.400216 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25574088 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25574088 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25574088 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25574088 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25574088 # number of overall hits +system.cpu.icache.overall_hits::total 25574088 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1305 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1305 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1305 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses +system.cpu.icache.overall_misses::total 1305 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 88661248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 88661248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 88661248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 88661248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25575393 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25575393 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25575393 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66103.667954 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66103.667954 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66103.667954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66103.667954 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67939.653640 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67939.653640 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67939.653640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67939.653640 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 37.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 289 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 289 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 289 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 289 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 289 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1006 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1006 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1006 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1006 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1006 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1006 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67541250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 67541250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67541250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 67541250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67541250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 67541250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67138.419483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67138.419483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 294 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 294 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 294 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 167 # number of writebacks +system.cpu.l2cache.writebacks::total 167 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 994 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1416 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29003 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1511756500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55574500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1536530000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1592104500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55574500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1536530000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1592104500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000710 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352307 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352307 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55909.959759 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58704.976303 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56742.937853 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52124.142330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52124.142330 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2072493 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.881910 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71371808 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076589 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.369732 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20650704250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.881910 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40030061 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40030061 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341747 # 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number of replacements +system.cpu.dcache.tags.tagsinuse 4069.513707 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71413624 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076610 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.389521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20690834250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40071931 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40071931 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341693 # 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average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.131613 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28347.010453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28347.010453 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12548.143405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12548.143405 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32707 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9490 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9497 # 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average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2066887 # number of writebacks +system.cpu.dcache.writebacks::total 2066887 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631351 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631351 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15843 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15843 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647194 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647194 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994395 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994395 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82216 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82216 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076611 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076611 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076611 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076611 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21996462750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21996462750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2491650748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2491650748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488113498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24488113498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488113498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24488113498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046710 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046710 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028010 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028010 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.140541 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.140541 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30306.153887 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30306.153887 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 76f42f35e..293b4caca 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,104 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202350 # Number of seconds simulated -sim_ticks 202349747500 # Number of ticks simulated -final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202724 # Number of seconds simulated +sim_ticks 202723760000 # Number of ticks simulated +final_tick 202723760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125600 # Simulator instruction rate (inst/s) -host_op_rate 141606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50303215 # Simulator tick rate (ticks/s) -host_mem_usage 251352 # Number of bytes of host memory used -host_seconds 4022.61 # Real time elapsed on the host +host_inst_rate 119496 # Simulator instruction rate (inst/s) +host_op_rate 134724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47946894 # Simulator tick rate (ticks/s) +host_mem_usage 278932 # Number of bytes of host memory used +host_seconds 4228.09 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9268224 # Number of bytes read from this memory -system.physmem.bytes_read::total 9485120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6250688 # Number of bytes written to this memory -system.physmem.bytes_written::total 6250688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144816 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148205 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97667 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97667 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1071887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45802993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46874879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1071887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1071887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30890515 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30890515 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30890515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1071887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45802993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77765395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148206 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 97667 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 148206 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 97667 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 9485120 # Total number of bytes read from memory -system.physmem.bytesWritten 6250688 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9485120 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6250688 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9580 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8983 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9807 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9117 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8328 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8806 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8899 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9634 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9453 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5891 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6047 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5559 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5812 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5895 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6521 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6360 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6066 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6146 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry -system.physmem.totGap 202349728000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148206 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 97667 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 138524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9267712 # Number of bytes read from this memory +system.physmem.bytes_read::total 9484928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6251136 # Number of bytes written to this memory +system.physmem.bytes_written::total 6251136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144808 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148202 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97674 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97674 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1071488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45715963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46787451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1071488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1071488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30835734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30835734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30835734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1071488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45715963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77623185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148203 # Number of read requests accepted +system.physmem.writeReqs 97674 # Number of write requests accepted +system.physmem.readBursts 148203 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97674 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9479680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5312 # Total number of bytes read from write queue +system.physmem.bytesWritten 6250624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9484992 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6251136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 83 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9589 # Per bank write bursts +system.physmem.perBankRdBursts::1 9263 # Per bank write bursts +system.physmem.perBankRdBursts::2 9230 # Per bank write bursts +system.physmem.perBankRdBursts::3 8983 # Per bank write bursts +system.physmem.perBankRdBursts::4 9781 # Per bank write bursts +system.physmem.perBankRdBursts::5 9608 # Per bank write bursts +system.physmem.perBankRdBursts::6 9123 # Per bank write bursts +system.physmem.perBankRdBursts::7 8333 # Per bank write bursts +system.physmem.perBankRdBursts::8 8801 # Per bank write bursts +system.physmem.perBankRdBursts::9 8921 # Per bank write bursts +system.physmem.perBankRdBursts::10 8939 # Per bank write bursts +system.physmem.perBankRdBursts::11 9732 # Per bank write bursts +system.physmem.perBankRdBursts::12 9670 # Per bank write bursts +system.physmem.perBankRdBursts::13 9771 # Per bank write bursts +system.physmem.perBankRdBursts::14 8945 # Per bank write bursts +system.physmem.perBankRdBursts::15 9431 # Per bank write bursts +system.physmem.perBankWrBursts::0 6268 # Per bank write bursts +system.physmem.perBankWrBursts::1 6168 # Per bank write bursts +system.physmem.perBankWrBursts::2 6085 # Per bank write bursts +system.physmem.perBankWrBursts::3 5885 # Per bank write bursts +system.physmem.perBankWrBursts::4 6259 # Per bank write bursts +system.physmem.perBankWrBursts::5 6263 # Per bank write bursts +system.physmem.perBankWrBursts::6 6041 # Per bank write bursts +system.physmem.perBankWrBursts::7 5560 # Per bank write bursts +system.physmem.perBankWrBursts::8 5811 # Per bank write bursts +system.physmem.perBankWrBursts::9 5905 # Per bank write bursts +system.physmem.perBankWrBursts::10 5991 # Per bank write bursts +system.physmem.perBankWrBursts::11 6522 # Per bank write bursts +system.physmem.perBankWrBursts::12 6386 # Per bank write bursts +system.physmem.perBankWrBursts::13 6332 # Per bank write bursts +system.physmem.perBankWrBursts::14 6056 # Per bank write bursts +system.physmem.perBankWrBursts::15 6134 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 202723740000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 148203 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 97674 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,198 +127,177 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 56168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.051275 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.674597 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 689.024149 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 28075 49.98% 49.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 10399 18.51% 68.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4642 8.26% 76.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2823 5.03% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1837 3.27% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1236 2.20% 87.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 832 1.48% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 663 1.18% 89.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 489 0.87% 90.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 349 0.62% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 274 0.49% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 236 0.42% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 206 0.37% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 181 0.32% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 152 0.27% 93.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 162 0.29% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 142 0.25% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 167 0.30% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 179 0.32% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 157 0.28% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 185 0.33% 95.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 244 0.43% 95.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 965 1.72% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 247 0.44% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 159 0.28% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 168 0.30% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 90 0.16% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 119 0.21% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 57 0.10% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 59 0.11% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 42 0.07% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 39 0.07% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 20 0.04% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 31 0.06% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.03% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 11 0.02% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 21 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 16 0.03% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 11 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 15 0.03% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 11 0.02% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 8 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 7 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 8 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 7 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 7 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 6 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 4 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 4 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 4 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 2 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 8 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 8 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 256 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 56168 # Bytes accessed per row activation -system.physmem.totQLat 1531991500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4652987750 # Sum of mem lat for all requests -system.physmem.totBusLat 740665000 # Total cycles spent in databus access -system.physmem.totBankLat 2380331250 # Total cycles spent in bank access -system.physmem.avgQLat 10342.00 # Average queueing delay per request -system.physmem.avgBankLat 16068.88 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31410.88 # Average memory access latency -system.physmem.avgRdBW 46.87 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 30.89 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 46.87 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 30.89 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.128612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.881961 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.200091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 32064 46.30% 46.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 12862 18.57% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5392 7.79% 72.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3385 4.89% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2324 3.36% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2409 3.48% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3469 5.01% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1945 2.81% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 863 1.25% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 531 0.77% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 437 0.63% 94.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 323 0.47% 95.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 295 0.43% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 249 0.36% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 196 0.28% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 174 0.25% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 149 0.22% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 143 0.21% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 144 0.21% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 117 0.17% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 151 0.22% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 829 1.20% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 98 0.14% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 133 0.19% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 72 0.10% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 116 0.17% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 42 0.06% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 50 0.07% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 21 0.03% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 33 0.05% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 14 0.02% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 14 0.02% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 13 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 19 0.03% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 5 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 13 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 5 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 10 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 5 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 12 0.02% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 4 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 4 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 10 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 4 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 2 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 4 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 5 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 3 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 5 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 2 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 1 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 1 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 2 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 5 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 7 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 4 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69255 # Bytes accessed per row activation +system.physmem.totQLat 1733533250 # Total ticks spent queuing +system.physmem.totMemAccLat 4938490750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740600000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2464357500 # Total ticks spent accessing banks +system.physmem.avgQLat 11703.57 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16637.57 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 33341.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 30.84 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.35 # Average write queue length over time -system.physmem.readRowHits 130665 # Number of row buffer hits during reads -system.physmem.writeRowHits 58958 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.37 # Row buffer hit rate for writes -system.physmem.avgGap 822984.74 # Average gap between requests -system.membus.throughput 77765395 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46900 # Transaction distribution -system.membus.trans_dist::ReadResp 46899 # Transaction distribution -system.membus.trans_dist::Writeback 97667 # Transaction distribution -system.membus.trans_dist::UpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 101306 # Transaction distribution -system.membus.trans_dist::ReadExResp 101306 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394092 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15735808 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15735808 # Total data (bytes) +system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.34 # Average write queue length when enqueuing +system.physmem.readRowHits 118615 # Number of row buffer hits during reads +system.physmem.writeRowHits 57916 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.30 # Row buffer hit rate for writes +system.physmem.avgGap 824492.49 # Average gap between requests +system.physmem.pageHitRate 71.82 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 77623185 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46911 # Transaction distribution +system.membus.trans_dist::ReadResp 46910 # Transaction distribution +system.membus.trans_dist::Writeback 97674 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11 # Transaction distribution +system.membus.trans_dist::UpgradeResp 11 # Transaction distribution +system.membus.trans_dist::ReadExReq 101292 # Transaction distribution +system.membus.trans_dist::ReadExResp 101292 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394101 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394101 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15736064 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15736064 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15736064 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1084180500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1083877500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1402154244 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1398233989 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 182791904 # Number of BP lookups -system.cpu.branchPred.condPredicted 143107699 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7265665 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 92799489 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87211157 # Number of BTB hits +system.cpu.branchPred.lookups 182800422 # Number of BP lookups +system.cpu.branchPred.condPredicted 143125984 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7265649 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93161641 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87212337 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.978057 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12678036 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116300 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.613998 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12679601 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116070 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -360,99 +341,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 404699496 # number of cpu cycles simulated +system.cpu.numCycles 405447521 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119376230 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761574875 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182791904 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99889193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170142836 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35680693 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77102658 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 212 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114526886 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2438240 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394234025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166653 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.987457 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119380246 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761599809 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182800422 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99891938 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170150193 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35686156 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77536501 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 421 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114531553 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2441596 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394683462 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164182 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986578 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224103808 56.85% 56.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14182639 3.60% 60.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22897810 5.81% 66.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22745771 5.77% 72.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20892648 5.30% 77.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11601037 2.94% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13057020 3.31% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11991400 3.04% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52761892 13.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224545887 56.89% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14186952 3.59% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22897432 5.80% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22746092 5.76% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20901340 5.30% 77.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11597179 2.94% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13058524 3.31% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11996237 3.04% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52753819 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394234025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.451673 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.881828 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129061557 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 72597650 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158807244 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6229539 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27538035 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26120872 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76664 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825542137 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 294964 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27538035 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135654542 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10112461 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47476958 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158262389 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15189640 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800582614 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1358 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3045147 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8947899 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 349 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954230037 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500483849 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3242011448 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 394683462 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.450861 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.878418 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129072579 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73027799 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158814938 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6226113 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27542033 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26114312 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76721 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825530013 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 296611 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27542033 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135666789 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10114135 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47882735 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158263751 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15214019 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800585655 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1326 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3054919 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8955576 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 319 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954278962 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500427685 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241978538 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 287977746 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292997 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292995 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41790364 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170263021 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73493180 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28522055 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15837658 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755040585 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775393 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665344412 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1377558 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187353857 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479696912 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797761 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394234025 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.687689 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.735339 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288026671 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292807 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292805 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41836607 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170271933 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73467321 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28611863 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15824348 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755053032 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775163 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665355613 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1381173 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187369401 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479711265 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797531 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394683462 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.734889 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 138748910 35.19% 35.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69932496 17.74% 52.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71500115 18.14% 71.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53381002 13.54% 84.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31138415 7.90% 92.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15994110 4.06% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8838982 2.24% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2889382 0.73% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1810613 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 139155313 35.26% 35.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69944135 17.72% 52.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71513404 18.12% 71.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53413889 13.53% 84.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31153204 7.89% 92.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16018566 4.06% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8773221 2.22% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2895809 0.73% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1815921 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394234025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394683462 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 479873 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 480741 5.03% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available @@ -481,15 +462,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6514297 68.24% 73.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2551723 26.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6525777 68.24% 73.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2556117 26.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447783022 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383422 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447788521 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383312 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -515,84 +496,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153378055 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63799818 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153398604 23.06% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63785079 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665344412 # Type of FU issued -system.cpu.iq.rate 1.644046 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9545893 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014347 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1735846081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 946976022 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646072801 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665355613 # Type of FU issued +system.cpu.iq.rate 1.641040 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9562635 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014372 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1736338273 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947004281 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646070374 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674890194 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8556478 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674918135 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8557309 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44233466 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41675 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810117 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16632703 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44242378 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810625 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16606844 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19496 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7207 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19503 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8485 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27538035 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5291148 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 386655 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760374882 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1114721 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170263021 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73493180 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286851 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219754 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12032 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810117 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4339015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4002364 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8341379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655919187 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150094220 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9425225 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27542033 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5268504 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 386055 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760387350 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1120402 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170271933 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73467321 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286621 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219781 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12300 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810625 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4335480 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4005038 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8340518 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655927300 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150116406 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9428313 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558904 # number of nop insts executed -system.cpu.iew.exec_refs 212597859 # number of memory reference insts executed -system.cpu.iew.exec_branches 138494490 # Number of branches executed -system.cpu.iew.exec_stores 62503639 # Number of stores executed -system.cpu.iew.exec_rate 1.620756 # Inst execution rate -system.cpu.iew.wb_sent 651040733 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646072817 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374723288 # num instructions producing a value -system.cpu.iew.wb_consumers 646307001 # num instructions consuming a value +system.cpu.iew.exec_nop 1559155 # number of nop insts executed +system.cpu.iew.exec_refs 212603914 # number of memory reference insts executed +system.cpu.iew.exec_branches 138495848 # Number of branches executed +system.cpu.iew.exec_stores 62487508 # Number of stores executed +system.cpu.iew.exec_rate 1.617786 # Inst execution rate +system.cpu.iew.wb_sent 651044212 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646070390 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374730881 # num instructions producing a value +system.cpu.iew.wb_consumers 646348309 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.596426 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579791 # average fanout of values written-back +system.cpu.iew.wb_rate 1.593475 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579766 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189435177 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189447861 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7191667 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 366695990 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.557061 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.231965 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7191623 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 367141429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.555172 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.229944 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159030399 43.37% 43.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98569557 26.88% 70.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33781130 9.21% 79.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18728324 5.11% 84.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16185625 4.41% 88.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7417790 2.02% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6942685 1.89% 92.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3160022 0.86% 93.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22880458 6.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159432399 43.43% 43.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98512068 26.83% 70.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33823975 9.21% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18780022 5.12% 84.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16190351 4.41% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7453107 2.03% 91.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6987048 1.90% 92.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3180816 0.87% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22781643 6.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 366695990 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 367141429 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,221 +584,225 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22880458 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22781643 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104211738 # The number of ROB reads -system.cpu.rob.rob_writes 1548465628 # The number of ROB writes -system.cpu.timesIdled 328564 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10465471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104768676 # The number of ROB reads +system.cpu.rob.rob_writes 1548495185 # The number of ROB writes +system.cpu.timesIdled 328850 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10764059 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.801008 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.801008 # CPI: Total CPI of All Threads -system.cpu.ipc 1.248427 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.248427 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058780194 # number of integer regfile reads -system.cpu.int_regfile_writes 751998753 # number of integer regfile writes +system.cpu.cpi 0.802489 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.802489 # CPI: Total CPI of All Threads +system.cpu.ipc 1.246124 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.246124 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058844384 # number of integer regfile reads +system.cpu.int_regfile_writes 752016829 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210849013 # number of misc regfile reads +system.cpu.misc_regfile_reads 210849022 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 735301298 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864913 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1111058 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 69 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 69 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348843 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348843 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33804 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504826 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3538630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1079232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147703872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148783104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148783104 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 4928 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273504243 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 734005013 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 865051 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 865050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1111085 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 84 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 84 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348869 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33932 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505059 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3538991 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1082560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147711232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148793792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148793792 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 6464 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273629999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 26125731 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 26093735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1828577727 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1824375488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15008 # number of replacements -system.cpu.icache.tags.tagsinuse 1099.436561 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114505770 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16868 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6788.343016 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 15073 # number of replacements +system.cpu.icache.tags.tagsinuse 1099.985685 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114510320 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16932 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6762.952988 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1099.436561 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.536834 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.536834 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114505770 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114505770 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114505770 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114505770 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114505770 # number of overall hits -system.cpu.icache.overall_hits::total 114505770 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21115 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21115 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21115 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21115 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21115 # number of overall misses -system.cpu.icache.overall_misses::total 21115 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 590629979 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 590629979 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 590629979 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 590629979 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 590629979 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 590629979 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114526885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114526885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114526885 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114526885 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114526885 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114526885 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27972.056784 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27972.056784 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27972.056784 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27972.056784 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 633 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1099.985685 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.537102 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.537102 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114510320 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114510320 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114510320 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114510320 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114510320 # number of overall hits +system.cpu.icache.overall_hits::total 114510320 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21232 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21232 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21232 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21232 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21232 # number of overall misses +system.cpu.icache.overall_misses::total 21232 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 575292732 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 575292732 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 575292732 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 575292732 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 575292732 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 575292732 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114531552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114531552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114531552 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114531552 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114531552 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114531552 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27095.550678 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27095.550678 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27095.550678 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27095.550678 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.121002 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.122117 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77587.132353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80012.989549 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79837.258975 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2299.900000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2299.900000 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74596.904515 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74596.904515 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76256.213394 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76256.213394 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -826,195 +811,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97667 # number of writebacks -system.cpu.l2cache.writebacks::total 97667 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97674 # number of writebacks +system.cpu.l2cache.writebacks::total 97674 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 24 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230113250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8913440001 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9143553251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230113250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8913440001 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9143553251 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051311 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054230 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.086957 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.086957 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290409 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290409 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121002 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122114 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121002 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122114 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67880.014749 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71688.376235 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71413.102345 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10584.166667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10584.166667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57195.245649 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57195.245649 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67880.014749 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67880.014749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3395 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43516 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46911 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3395 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144809 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148204 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3395 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144809 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148204 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220586000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2937177750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3157763750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6271255251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6271255251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220586000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9208433001 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9429019001 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220586000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9208433001 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9429019001 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051314 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64973.784978 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67496.501287 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67313.929569 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61912.029963 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61912.029963 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1192719 # number of replacements -system.cpu.dcache.tags.tagsinuse 4057.784175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 190184088 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1196815 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 158.908510 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4223544250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.784175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136217061 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136217061 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50989456 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50989456 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488807 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488807 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1192807 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.511512 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190198729 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196903 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.909059 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.511512 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990603 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990603 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136233368 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136233368 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50987745 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50987745 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488823 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488823 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # 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number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137917557 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137917557 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187221113 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187221113 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187221113 # number of overall hits +system.cpu.dcache.overall_hits::total 187221113 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1703411 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1703411 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3251561 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3251561 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 36 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4954972 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4954972 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4954972 # number of overall misses +system.cpu.dcache.overall_misses::total 4954972 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29743018227 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29743018227 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 72512845225 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 72512845225 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 596500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 596500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102255863452 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102255863452 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102255863452 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102255863452 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137936779 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137936779 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488848 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488848 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488859 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488859 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192156863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192156863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192156863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192156863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012330 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012330 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059917 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059917 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025762 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025762 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025762 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025762 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17523.954454 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17523.954454 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21417.507178 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21417.507178 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15762.195122 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15762.195122 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20080.030801 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20080.030801 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21739 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 43165 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1718 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 667 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.653667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 64.715142 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192176085 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192176085 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192176085 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192176085 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012349 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012349 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059948 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059948 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025783 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025783 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025783 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025783 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17460.858376 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17460.858376 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22300.933375 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 22300.933375 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.444444 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.444444 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20637.021451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20637.021451 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18554 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 53547 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1675 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.077015 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 81.009077 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111058 # number of writebacks -system.cpu.dcache.writebacks::total 1111058 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 851983 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 851983 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2901479 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2901479 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3753462 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3753462 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3753462 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3753462 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848513 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348371 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348371 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196884 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196884 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196884 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196884 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12602071778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12602071778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9955936491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9955936491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22558008269 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22558008269 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22558008269 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22558008269 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1111085 # number of writebacks +system.cpu.dcache.writebacks::total 1111085 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 854833 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 854833 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2903152 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2903152 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3757985 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3757985 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3757985 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3757985 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848578 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848578 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348409 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348409 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196987 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196987 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196987 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196987 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12415172523 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12415172523 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10430126485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10430126485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22845299008 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22845299008 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22845299008 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22845299008 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14851.948972 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14851.948972 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28578.545548 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28578.545548 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14630.561390 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14630.561390 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29936.443906 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29936.443906 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index c15724aa4..09ddfe08f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,103 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.458276 # Number of seconds simulated -sim_ticks 458276279000 # Number of ticks simulated -final_tick 458276279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.459344 # Number of seconds simulated +sim_ticks 459344378000 # Number of ticks simulated +final_tick 459344378000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81967 # Simulator instruction rate (inst/s) -host_op_rate 151565 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45427941 # Simulator tick rate (ticks/s) -host_mem_usage 343960 # Number of bytes of host memory used -host_seconds 10087.98 # Real time elapsed on the host +host_inst_rate 78845 # Simulator instruction rate (inst/s) +host_op_rate 145792 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43799497 # Simulator tick rate (ticks/s) +host_mem_usage 371908 # Number of bytes of host memory used +host_seconds 10487.44 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24475520 # Number of bytes read from this memory -system.physmem.bytes_read::total 24678208 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18791744 # Number of bytes written to this memory -system.physmem.bytes_written::total 18791744 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382430 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385597 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293621 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293621 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53407783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53850066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41005273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41005273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41005273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442283 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53407783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94855339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385597 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 293621 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 385597 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 293621 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 24678208 # Total number of bytes read from memory -system.physmem.bytesWritten 18791744 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24678208 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18791744 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 167 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 129454 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 26368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24819 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23840 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 23982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 23151 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 22850 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 23658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23921 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 18532 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 19819 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18953 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18410 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18967 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18941 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18561 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18114 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17718 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 17344 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 16935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 17686 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 17818 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry -system.physmem.totGap 458276251500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385597 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293621 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 201792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24475712 # Number of bytes read from this memory +system.physmem.bytes_read::total 24677504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 201792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 201792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18789056 # Number of bytes written to this memory +system.physmem.bytes_written::total 18789056 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3153 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382433 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385586 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293579 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293579 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 439304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53284013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53723318 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 439304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40904073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40904073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40904073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 439304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53284013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94627391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385586 # Number of read requests accepted +system.physmem.writeReqs 293579 # Number of write requests accepted +system.physmem.readBursts 385586 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293579 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24668096 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue +system.physmem.bytesWritten 18787968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24677504 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18789056 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 137816 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24063 # Per bank write bursts +system.physmem.perBankRdBursts::1 26414 # Per bank write bursts +system.physmem.perBankRdBursts::2 24662 # Per bank write bursts +system.physmem.perBankRdBursts::3 24515 # Per bank write bursts +system.physmem.perBankRdBursts::4 23241 # Per bank write bursts +system.physmem.perBankRdBursts::5 23653 # Per bank write bursts +system.physmem.perBankRdBursts::6 24406 # Per bank write bursts +system.physmem.perBankRdBursts::7 24209 # Per bank write bursts +system.physmem.perBankRdBursts::8 23620 # Per bank write bursts +system.physmem.perBankRdBursts::9 23822 # Per bank write bursts +system.physmem.perBankRdBursts::10 24803 # Per bank write bursts +system.physmem.perBankRdBursts::11 24074 # Per bank write bursts +system.physmem.perBankRdBursts::12 23251 # Per bank write bursts +system.physmem.perBankRdBursts::13 22944 # Per bank write bursts +system.physmem.perBankRdBursts::14 23767 # Per bank write bursts +system.physmem.perBankRdBursts::15 23995 # Per bank write bursts +system.physmem.perBankWrBursts::0 18528 # Per bank write bursts +system.physmem.perBankWrBursts::1 19811 # Per bank write bursts +system.physmem.perBankWrBursts::2 18936 # Per bank write bursts +system.physmem.perBankWrBursts::3 18914 # Per bank write bursts +system.physmem.perBankWrBursts::4 18031 # Per bank write bursts +system.physmem.perBankWrBursts::5 18401 # Per bank write bursts +system.physmem.perBankWrBursts::6 18972 # Per bank write bursts +system.physmem.perBankWrBursts::7 18946 # Per bank write bursts +system.physmem.perBankWrBursts::8 18539 # Per bank write bursts +system.physmem.perBankWrBursts::9 18111 # Per bank write bursts +system.physmem.perBankWrBursts::10 18827 # Per bank write bursts +system.physmem.perBankWrBursts::11 17725 # Per bank write bursts +system.physmem.perBankWrBursts::12 17351 # Per bank write bursts +system.physmem.perBankWrBursts::13 16948 # Per bank write bursts +system.physmem.perBankWrBursts::14 17708 # Per bank write bursts +system.physmem.perBankWrBursts::15 17814 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 459344352000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 385586 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 293579 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380798 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -125,346 +127,324 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 125846 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 345.334329 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.235120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 666.634247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 53836 42.78% 42.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 23576 18.73% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 10431 8.29% 69.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 6405 5.09% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 4091 3.25% 78.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 2950 2.34% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 2205 1.75% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1721 1.37% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 1423 1.13% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 1129 0.90% 85.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 1178 0.94% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1088 0.86% 87.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 719 0.57% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 691 0.55% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 593 0.47% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 590 0.47% 89.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 543 0.43% 89.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 555 0.44% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 625 0.50% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 694 0.55% 91.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 625 0.50% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 735 0.58% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6224 4.95% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 501 0.40% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 329 0.26% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 262 0.21% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 235 0.19% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 154 0.12% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 168 0.13% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 127 0.10% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 91 0.07% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 78 0.06% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 63 0.05% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 57 0.05% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 48 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 48 0.04% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 32 0.03% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 31 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 21 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 34 0.03% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 24 0.02% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 22 0.02% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 28 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 15 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 11 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 26 0.02% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 10 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 12 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 9 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 11 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 10 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 11 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 9 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 9 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 11 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 4 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 11 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 3 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 5 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 10 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 5 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 4 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 4 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 12 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 10 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 9 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 8 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 5 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 4 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 3 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 376 0.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 125846 # Bytes accessed per row activation -system.physmem.totQLat 3013395500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11189631750 # Sum of mem lat for all requests -system.physmem.totBusLat 1927150000 # Total cycles spent in databus access -system.physmem.totBankLat 6249086250 # Total cycles spent in bank access -system.physmem.avgQLat 7818.27 # Average queueing delay per request -system.physmem.avgBankLat 16213.28 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29031.55 # Average memory access latency -system.physmem.avgRdBW 53.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.85 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 13203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 13287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 13314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 13327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 13328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 13318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 13383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 13355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 13385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 13360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 13377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 13325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 13360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 13383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 13353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 13304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 13344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 13297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 13513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 13303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 147608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.394450 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 155.776614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 442.926634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 63757 43.19% 43.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 27975 18.95% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 12431 8.42% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7117 4.82% 75.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4833 3.27% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3554 2.41% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2743 1.86% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2234 1.51% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1986 1.35% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1585 1.07% 86.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1916 1.30% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1217 0.82% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1133 0.77% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1065 0.72% 90.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 945 0.64% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 876 0.59% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1005 0.68% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1152 0.78% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1143 0.77% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 849 0.58% 94.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 811 0.55% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 5222 3.54% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 320 0.22% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 205 0.14% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 175 0.12% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 129 0.09% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 96 0.07% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 103 0.07% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 90 0.06% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 59 0.04% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 49 0.03% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 46 0.03% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 39 0.03% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 37 0.03% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 41 0.03% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 25 0.02% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 33 0.02% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 21 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 11 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 24 0.02% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 23 0.02% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 26 0.02% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 13 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 15 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 22 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 19 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 16 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 16 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 15 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 11 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 21 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 9 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 16 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 10 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 11 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 14 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 17 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 17 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 11 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 7 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 10 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 9 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 7 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 6 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 12 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 24 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 37 0.03% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 1 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 9 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 3 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 4 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 5 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 3 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 6 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 5 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 4 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 8 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568 4 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 3 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888 3 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 8 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 10 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080 3 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 3 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272 18 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147608 # Bytes accessed per row activation +system.physmem.totQLat 3829490000 # Total ticks spent queuing +system.physmem.totMemAccLat 12088876250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1927195000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6332191250 # Total ticks spent accessing banks +system.physmem.avgQLat 9935.40 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16428.52 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31363.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 53.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 40.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.72 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 40.90 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.74 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.13 # Average write queue length over time -system.physmem.readRowHits 346215 # Number of row buffer hits during reads -system.physmem.writeRowHits 206987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.49 # Row buffer hit rate for writes -system.physmem.avgGap 674711.58 # Average gap between requests -system.membus.throughput 94855339 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178753 # Transaction distribution -system.membus.trans_dist::ReadResp 178753 # Transaction distribution -system.membus.trans_dist::Writeback 293621 # Transaction distribution -system.membus.trans_dist::UpgradeReq 129454 # Transaction distribution -system.membus.trans_dist::UpgradeResp 129454 # Transaction distribution -system.membus.trans_dist::ReadExReq 206844 # Transaction distribution -system.membus.trans_dist::ReadExResp 206844 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1323723 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1323723 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1323723 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469952 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469952 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43469952 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43469952 # Total data (bytes) +system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing +system.physmem.readRowHits 326974 # Number of row buffer hits during reads +system.physmem.writeRowHits 204419 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.63 # Row buffer hit rate for writes +system.physmem.avgGap 676336.90 # Average gap between requests +system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.85 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 94627391 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178768 # Transaction distribution +system.membus.trans_dist::ReadResp 178768 # Transaction distribution +system.membus.trans_dist::Writeback 293579 # Transaction distribution +system.membus.trans_dist::UpgradeReq 137816 # Transaction distribution +system.membus.trans_dist::UpgradeResp 137816 # Transaction distribution +system.membus.trans_dist::ReadExReq 206818 # Transaction distribution +system.membus.trans_dist::ReadExResp 206818 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1340383 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1340383 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1340383 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43466560 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43466560 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3387419250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3394511250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3898953053 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3904983950 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.branchPred.lookups 205598458 # Number of BP lookups -system.cpu.branchPred.condPredicted 205598458 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9896380 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117174051 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114692881 # Number of BTB hits +system.cpu.branchPred.lookups 205617659 # Number of BP lookups +system.cpu.branchPred.condPredicted 205617659 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9903777 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117094014 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114674529 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.882492 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25059076 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1793638 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.933724 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25071350 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1805580 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 916711426 # number of cpu cycles simulated +system.cpu.numCycles 918847215 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167358741 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131763090 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205598458 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139751957 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352259726 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71078928 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 303625713 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47908 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254198 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162013852 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2539166 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 884476430 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.380618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325214 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167424119 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131762166 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205617659 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139745879 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352279607 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71096448 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 305445808 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47309 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 248301 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162018331 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2527029 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 886385524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.375664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.323603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536284008 60.63% 60.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23384253 2.64% 63.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25253496 2.86% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27902300 3.15% 69.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17749201 2.01% 71.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22913352 2.59% 73.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29416028 3.33% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26647385 3.01% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174926407 19.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 538173800 60.72% 60.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23402088 2.64% 63.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25255439 2.85% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27875375 3.14% 69.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17753006 2.00% 71.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22920695 2.59% 73.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29402684 3.32% 77.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26636320 3.01% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174966117 19.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 884476430 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224278 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.234590 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222500802 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258763432 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295392395 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46889742 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60930059 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071354254 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60930059 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 255984410 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 114277740 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18348 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306680368 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146585505 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035184371 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 17660 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24877077 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106438010 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2138008878 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150477195 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3273486109 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 27867 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 886385524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.223778 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.231720 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222535838 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 260614631 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295382827 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46911879 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60940349 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071401768 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 60940349 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 256088737 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 115827091 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17786 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306634612 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146876949 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035245404 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18048 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25034239 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106622478 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2138089384 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150744592 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3273505517 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 42043 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523968024 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1260 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1188 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 346256555 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495848123 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194451746 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195373810 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54752041 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975440933 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 14060 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772196947 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 491373 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441593338 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734714175 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13508 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 884476430 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.003668 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.883218 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 524048530 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1277 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1209 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346982000 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495887036 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194435860 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195573190 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54925274 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975493038 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13839 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772240867 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484864 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441634059 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 734815554 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13287 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 886385524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.999402 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.882776 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 267871954 30.29% 30.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151795933 17.16% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137193879 15.51% 62.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131984117 14.92% 77.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91584837 10.35% 88.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55972472 6.33% 94.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34407043 3.89% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11912621 1.35% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1753574 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 269512858 30.41% 30.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151842775 17.13% 47.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137668751 15.53% 63.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131788792 14.87% 77.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91572274 10.33% 88.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 55974345 6.31% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34415050 3.88% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11842339 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1768340 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 884476430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 886385524 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4900873 32.33% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7664927 50.56% 82.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2594883 17.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4916629 32.41% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7656958 50.48% 82.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2596197 17.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2622931 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165806661 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 353241 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880883 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2627446 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165802431 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352933 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880848 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -491,84 +471,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429278261 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170254965 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429321200 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170256004 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772196947 # Type of FU issued -system.cpu.iq.rate 1.933211 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15160683 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008555 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4444507102 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2417272272 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744936391 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15278 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 33048 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3640 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784727445 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7254 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172555642 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772240867 # Type of FU issued +system.cpu.iq.rate 1.928766 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15169784 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008560 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4446506063 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417344315 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744979494 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15843 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 54000 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3681 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784775700 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7505 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172548732 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111746790 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 385650 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 328822 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45291560 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111785908 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 387968 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 329381 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45275674 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15317 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 618 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14622 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 560 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60930059 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 66792766 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7181188 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975454993 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 789344 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495848947 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194451746 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4469390 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83563 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 328822 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5897715 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4420728 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10318443 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1753033326 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424140898 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19163621 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60940349 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 68092505 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7152437 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975506877 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 797637 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495888065 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194435860 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3411 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4450354 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83339 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 329381 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5904947 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4426658 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10331605 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1753082670 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424162697 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19158197 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590949993 # number of memory reference insts executed -system.cpu.iew.exec_branches 167484534 # Number of branches executed -system.cpu.iew.exec_stores 166809095 # Number of stores executed -system.cpu.iew.exec_rate 1.912307 # Inst execution rate -system.cpu.iew.wb_sent 1749784390 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744940031 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325078811 # num instructions producing a value -system.cpu.iew.wb_consumers 1946006295 # num instructions consuming a value +system.cpu.iew.exec_refs 590975772 # number of memory reference insts executed +system.cpu.iew.exec_branches 167493044 # Number of branches executed +system.cpu.iew.exec_stores 166813075 # Number of stores executed +system.cpu.iew.exec_rate 1.907915 # Inst execution rate +system.cpu.iew.wb_sent 1749835931 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744983175 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325071563 # num instructions producing a value +system.cpu.iew.wb_consumers 1945952606 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.903478 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680922 # average fanout of values written-back +system.cpu.iew.wb_rate 1.899100 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680937 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446495753 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446546244 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9924967 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823546371 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856591 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.436968 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9931583 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 825445175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.852320 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.435275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 331540397 40.26% 40.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193316161 23.47% 63.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63109500 7.66% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92579702 11.24% 82.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24975285 3.03% 85.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27432624 3.33% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9320772 1.13% 90.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11449898 1.39% 91.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69822032 8.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 333247555 40.37% 40.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193457802 23.44% 63.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63161135 7.65% 71.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92621225 11.22% 82.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24986952 3.03% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27475927 3.33% 89.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9292263 1.13% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11354595 1.38% 91.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69847721 8.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823546371 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 825445175 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -579,228 +559,228 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69822032 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69847721 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2729208793 # The number of ROB reads -system.cpu.rob.rob_writes 4012058416 # The number of ROB writes -system.cpu.timesIdled 3349890 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32234996 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2731132399 # The number of ROB reads +system.cpu.rob.rob_writes 4012169962 # The number of ROB writes +system.cpu.timesIdled 3361848 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32461691 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.108643 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.108643 # CPI: Total CPI of All Threads -system.cpu.ipc 0.902004 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.902004 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2716444328 # number of integer regfile reads -system.cpu.int_regfile_writes 1420478428 # number of integer regfile writes -system.cpu.fp_regfile_reads 3628 # number of floating regfile reads -system.cpu.fp_regfile_writes 22 # number of floating regfile writes -system.cpu.cc_regfile_reads 597234249 # number of cc regfile reads -system.cpu.cc_regfile_writes 405441134 # number of cc regfile writes -system.cpu.misc_regfile_reads 964696527 # number of misc regfile reads +system.cpu.cpi 1.111226 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.111226 # CPI: Total CPI of All Threads +system.cpu.ipc 0.899907 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.899907 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2716502748 # number of integer regfile reads +system.cpu.int_regfile_writes 1420506154 # number of integer regfile writes +system.cpu.fp_regfile_reads 3672 # number of floating regfile reads +system.cpu.fp_regfile_writes 20 # number of floating regfile writes +system.cpu.cc_regfile_reads 597266892 # number of cc regfile reads +system.cpu.cc_regfile_writes 405440972 # number of cc regfile writes +system.cpu.misc_regfile_reads 964759802 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 698612009 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1899997 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1899996 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330686 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 130874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 130874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771776 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771776 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 144643 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7660372 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7805015 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311337920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311775616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311775616 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8381696 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4900939314 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 698195949 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1908531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1908530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 139237 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 139237 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771745 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152897 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7677656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7830553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 434176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311361216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311795392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311795392 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8916992 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4909747073 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 207374491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 219630492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3958743651 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3954804981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5318 # number of replacements -system.cpu.icache.tags.tagsinuse 1036.794557 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161872030 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6894 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23480.131999 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5269 # number of replacements +system.cpu.icache.tags.tagsinuse 1036.495304 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161868325 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6841 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23661.500512 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1036.794557 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506247 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506247 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161874097 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161874097 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161874097 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161874097 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161874097 # number of overall hits -system.cpu.icache.overall_hits::total 161874097 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 139755 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 139755 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 139755 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 139755 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 139755 # number of overall misses -system.cpu.icache.overall_misses::total 139755 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 916174482 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 916174482 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 916174482 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 916174482 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 916174482 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 916174482 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162013852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162013852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162013852 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162013852 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162013852 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162013852 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000863 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000863 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000863 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000863 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000863 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000863 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6555.575700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6555.575700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6555.575700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6555.575700 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1833 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1036.495304 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506101 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506101 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161870260 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161870260 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161870260 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161870260 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161870260 # number of overall hits +system.cpu.icache.overall_hits::total 161870260 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 148071 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 148071 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 148071 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 148071 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 148071 # number of overall misses +system.cpu.icache.overall_misses::total 148071 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 946797737 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 946797737 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 946797737 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 946797737 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 946797737 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 946797737 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162018331 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162018331 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162018331 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162018331 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162018331 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162018331 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000914 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6394.214512 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6394.214512 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6394.214512 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6394.214512 # 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number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -809,168 +789,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293621 # number of writebacks -system.cpu.l2cache.writebacks::total 293621 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3168 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175586 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 178754 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 129428 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 129428 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099641 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101046 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988951 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988951 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268044 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268044 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151772 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151772 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65010.416667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62347.333831 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62394.530797 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10028.390086 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10028.390086 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56210.990119 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56210.990119 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 385610 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200295500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10955219212 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11155514712 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1381780092 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1381780092 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12524720523 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12524720523 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200295500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23479939735 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23680235235 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200295500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23479939735 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23680235235 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099644 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101045 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989629 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989629 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268017 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268017 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151758 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151758 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63505.231452 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62382.024383 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62401.840990 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.941129 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.941129 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60552.407516 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60552.407516 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63505.231452 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61392.525506 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61409.805853 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63505.231452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61392.525506 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61409.805853 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2529873 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.353795 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396071280 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2533969 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.304706 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.353795 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247337709 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247337709 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148240799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148240799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395578508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395578508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395578508 # 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Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 247349433 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247349433 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148232494 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148232494 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395581927 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395581927 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395581927 # number of overall hits +system.cpu.dcache.overall_hits::total 395581927 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2875523 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2875523 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 927708 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 927708 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3803231 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3803231 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3803231 # number of overall misses +system.cpu.dcache.overall_misses::total 3803231 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57896671055 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57896671055 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26926543731 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26926543731 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84823214786 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84823214786 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84823214786 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84823214786 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250224956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250224956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399365220 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399365220 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399365220 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399365220 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011460 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011460 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006164 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006164 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009482 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009482 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009482 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009482 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.853782 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.853782 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28085.185333 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28085.185333 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22003.838445 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22003.838445 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7384 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399385158 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399385158 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399385158 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399385158 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011492 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011492 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006220 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006220 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009523 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009523 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009523 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009523 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20134.309847 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20134.309847 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.804929 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.804929 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22302.935264 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22302.935264 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6209 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 704 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 638 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.488636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.731975 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330686 # number of writebacks -system.cpu.dcache.writebacks::total 2330686 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1104851 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1104851 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17019 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17019 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1121870 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1121870 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1121870 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1121870 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762458 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762458 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 902384 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 902384 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2664842 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2664842 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2664842 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2664842 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30865724250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30865724250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23705880099 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23705880099 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54571604349 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 54571604349 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54571604349 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 54571604349 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2330856 # number of writebacks +system.cpu.dcache.writebacks::total 2330856 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1112832 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1112832 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17000 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17000 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1129832 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1129832 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1129832 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1129832 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762691 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762691 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 910708 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 910708 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2673399 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2673399 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2673399 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2673399 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30862506500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30862506500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24793543019 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 24793543019 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55656049519 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55656049519 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55656049519 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55656049519 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006050 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006050 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006673 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006673 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17512.884988 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17512.884988 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26270.279725 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26270.279725 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006106 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006106 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006694 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006694 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006694 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006694 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.744584 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.744584 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27224.470433 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27224.470433 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index e5b6926d1..0feb1e331 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139916 # Number of seconds simulated -sim_ticks 139916242500 # Number of ticks simulated -final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139926 # Number of seconds simulated +sim_ticks 139926186500 # Number of ticks simulated +final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80792 # Simulator instruction rate (inst/s) -host_op_rate 80792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28354866 # Simulator tick rate (ticks/s) -host_mem_usage 231004 # Number of bytes of host memory used -host_seconds 4934.47 # Real time elapsed on the host +host_inst_rate 122800 # Simulator instruction rate (inst/s) +host_op_rate 122800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43101138 # Simulator tick rate (ticks/s) +host_mem_usage 261428 # Number of bytes of host memory used +host_seconds 3246.46 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1536462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1815486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3351948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1536462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1536462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7328 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 7328 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 468992 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 597 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 448 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 451 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 513 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 395 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 336 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 371 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 139916169000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7328 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 1536353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1815357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3351710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1536353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1536353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1536353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1815357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3351710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7328 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7328 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 468992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 468992 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 507 # Per bank write bursts +system.physmem.perBankRdBursts::1 643 # Per bank write bursts +system.physmem.perBankRdBursts::2 444 # Per bank write bursts +system.physmem.perBankRdBursts::3 597 # Per bank write bursts +system.physmem.perBankRdBursts::4 448 # Per bank write bursts +system.physmem.perBankRdBursts::5 451 # Per bank write bursts +system.physmem.perBankRdBursts::6 505 # Per bank write bursts +system.physmem.perBankRdBursts::7 513 # Per bank write bursts +system.physmem.perBankRdBursts::8 423 # Per bank write bursts +system.physmem.perBankRdBursts::9 395 # Per bank write bursts +system.physmem.perBankRdBursts::10 336 # Per bank write bursts +system.physmem.perBankRdBursts::11 304 # Per bank write bursts +system.physmem.perBankRdBursts::12 416 # Per bank write bursts +system.physmem.perBankRdBursts::13 534 # Per bank write bursts +system.physmem.perBankRdBursts::14 441 # Per bank write bursts +system.physmem.perBankRdBursts::15 371 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 139926113000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7328 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,98 +152,97 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 702 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 659.145299 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 261.737271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1246.496021 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 193 27.49% 27.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 99 14.10% 41.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 67 9.54% 51.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 56 7.98% 59.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 35 4.99% 64.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 20 2.85% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 23 3.28% 70.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 21 2.99% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 2.14% 75.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 12 1.71% 77.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 9 1.28% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.57% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 12 1.71% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.14% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.57% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.71% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 15 2.14% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 0.71% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 6 0.85% 86.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1 0.14% 86.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 4 0.57% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.57% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.57% 88.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.43% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 6 0.85% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.85% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 3 0.43% 91.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.14% 91.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.43% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.57% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 2 0.28% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.28% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.14% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.43% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 3 0.43% 95.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.14% 95.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.14% 95.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.14% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.28% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.28% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.14% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.14% 97.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.14% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.14% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.14% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.14% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.14% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.14% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.14% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.14% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.14% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.14% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation -system.physmem.totQLat 39772250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 175041000 # Sum of mem lat for all requests -system.physmem.totBusLat 36640000 # Total cycles spent in databus access -system.physmem.totBankLat 98628750 # Total cycles spent in bank access -system.physmem.avgQLat 5427.44 # Average queueing delay per request -system.physmem.avgBankLat 13459.16 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23886.60 # Average memory access latency -system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 1198 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.899833 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.568922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 772.018563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 419 34.97% 34.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 201 16.78% 51.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 128 10.68% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 91 7.60% 70.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 61 5.09% 75.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 40 3.34% 78.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 30 2.50% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 22 1.84% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 25 2.09% 84.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 18 1.50% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 20 1.67% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 8 0.67% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 17 1.42% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 10 0.83% 90.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 8 0.67% 91.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.50% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 10 0.83% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 7 0.58% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 7 0.58% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1 0.08% 94.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.33% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.33% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.17% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 5 0.42% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 5 0.42% 95.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.33% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.08% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.17% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.08% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.17% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.08% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.17% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.08% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.17% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.08% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 4 0.33% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.17% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.17% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.08% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.17% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.08% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.08% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.08% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.08% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.08% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.08% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.08% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.08% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.08% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.08% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 2 0.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1198 # Bytes accessed per row activation +system.physmem.totQLat 59880500 # Total ticks spent queuing +system.physmem.totMemAccLat 197624250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers +system.physmem.totBankLat 101103750 # Total ticks spent accessing banks +system.physmem.avgQLat 8171.47 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13796.91 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26968.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6626 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6130 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.65 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19093363.67 # Average gap between requests -system.membus.throughput 3351948 # Throughput (bytes/s) +system.physmem.avgGap 19094720.66 # Average gap between requests +system.physmem.pageHitRate 83.65 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.42 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 3351710 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution system.membus.trans_dist::ReadExReq 3145 # Transaction distribution @@ -252,39 +253,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 468992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68414000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68145750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 53489675 # Number of BP lookups +system.cpu.branchPred.lookups 53489673 # Number of BP lookups system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15212540 # Number of BTB hits +system.cpu.branchPred.BTBLookups 32882350 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 46.263540 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754653 # DTB read hits +system.cpu.dtb.read_hits 94754637 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754674 # DTB read accesses -system.cpu.dtb.write_hits 73521120 # DTB write hits +system.cpu.dtb.read_accesses 94754658 # DTB read accesses +system.cpu.dtb.write_hits 73521124 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521155 # DTB write accesses -system.cpu.dtb.data_hits 168275773 # DTB hits +system.cpu.dtb.write_accesses 73521159 # DTB write accesses +system.cpu.dtb.data_hits 168275761 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275829 # DTB accesses -system.cpu.itb.fetch_hits 48611327 # ITB hits +system.cpu.dtb.data_accesses 168275817 # DTB accesses +system.cpu.itb.fetch_hits 48611324 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655847 # ITB accesses +system.cpu.itb.fetch_accesses 48655844 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -298,18 +299,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279832486 # number of cpu cycles simulated +system.cpu.numCycles 279852374 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 29230507 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileReads 119631950 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484570 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828431 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484574 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -320,12 +321,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400467 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400617 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7142 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13525828 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306658 # Number of cycles cpu stages are processed. -system.cpu.activity 95.166455 # Percentage of cycles cpu is active +system.cpu.timesIdled 7206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13545708 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306666 # Number of cycles cpu stages are processed. +system.cpu.activity 95.159695 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -337,72 +338,72 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.701925 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701974 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.701925 # CPI: Total CPI of All Threads -system.cpu.ipc 1.424654 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701974 # CPI: Total CPI of All Threads +system.cpu.ipc 1.424553 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.424654 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78084810 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201747676 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.095874 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107180757 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651729 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.698244 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102617259 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177215227 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.329040 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181087860 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744626 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.287049 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90364523 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467963 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.707637 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.424553 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107200641 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651733 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.693860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181107759 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744615 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.284537 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90384394 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467980 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.702831 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1975 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1830.939408 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606790 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.699718 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48606795 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606795 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606795 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606795 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606795 # number of overall hits -system.cpu.icache.overall_hits::total 48606795 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4532 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4532 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4532 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4532 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4532 # number of overall misses -system.cpu.icache.overall_misses::total 4532 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 272220250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 272220250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 272220250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 272220250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 272220250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 272220250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611327 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611327 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611327 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611327 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611327 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611327 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939408 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894013 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606790 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606790 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606790 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606790 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606790 # number of overall hits +system.cpu.icache.overall_hits::total 48606790 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4534 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4534 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4534 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4534 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4534 # number of overall misses +system.cpu.icache.overall_misses::total 4534 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 280061250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 280061250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 280061250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 280061250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 280061250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 280061250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611324 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611324 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611324 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611324 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611324 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611324 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60066.251103 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60066.251103 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60066.251103 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60066.251103 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61769.133216 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61769.133216 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61769.133216 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61769.133216 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -411,38 +412,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 110 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 629 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 629 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 629 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 629 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 629 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 631 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 631 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 631 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 631 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 631 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 236384250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 236384250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 236384250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 236384250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 236384250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 236384250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244179750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 244179750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244179750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 244179750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244179750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 244179750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60564.757879 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60564.757879 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62562.067640 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62562.067640 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 3981353 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -458,23 +459,23 @@ system.cpu.toL2Bus.data_through_bus 557056 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6540750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6459750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6779999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6671999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3906.845611 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 370.550028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 370.534640 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.739390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571581 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -499,17 +500,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 226995250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59463500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 286458750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214640250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214640250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 226995250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 274103750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 501099000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 226995250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 274103750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 501099000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234790750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62080250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 296871000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 227075250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 227075250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234790750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 289155500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 523946250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234790750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 289155500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 523946250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -534,17 +535,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67578.222685 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72164.441748 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68481.651924 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68248.092210 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68248.092210 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68381.413755 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68381.413755 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69899.002679 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75340.109223 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70970.834329 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72201.987281 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72201.987281 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71499.215338 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71499.215338 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,17 +565,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 184726250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49135000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 233861250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175601750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175601750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184726250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 224736750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 409463000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184726250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 224736750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 409463000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192686250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51812250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 244498500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 188269250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 188269250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192686250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 240081500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 432767750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192686250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 240081500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 432767750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -586,51 +587,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54994.417982 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59629.854369 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55907.542434 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55835.214626 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55835.214626 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57364.170884 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62878.944175 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58450.513985 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59863.036566 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59863.036566 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3284.890275 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168254255 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40523.664499 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.890275 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801975 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801975 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501075 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501075 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254256 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254256 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254256 # number of overall hits -system.cpu.dcache.overall_hits::total 168254256 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501074 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501074 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254255 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254255 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254255 # number of overall hits +system.cpu.dcache.overall_hits::total 168254255 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19654 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19654 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20962 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20962 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20962 # number of overall misses -system.cpu.dcache.overall_misses::total 20962 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 85220999 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 85220999 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1076127000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1076127000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1161347999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1161347999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1161347999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1161347999 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 19655 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19655 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20963 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20963 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20963 # number of overall misses +system.cpu.dcache.overall_misses::total 20963 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88453749 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88453749 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1129220750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1129220750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1217674499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1217674499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1217674499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1217674499 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -647,19 +648,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65153.668960 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65153.668960 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54753.587056 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54753.587056 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55402.537878 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55402.537878 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67625.190367 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67625.190367 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57452.085983 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57452.085983 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58086.843438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58086.843438 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33688 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 596 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 584 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.743289 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.684932 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -667,12 +668,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16452 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16452 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16810 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16810 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16810 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16810 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16453 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16453 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16811 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16811 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16811 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16811 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -681,14 +682,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61946751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 61946751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218347750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 218347750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 280294501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 280294501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 280294501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 280294501 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64535001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64535001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 230815000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 230815000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 295350001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 295350001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 295350001 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 295350001 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -697,14 +698,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65207.106316 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65207.106316 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68191.052467 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68191.052467 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67931.580000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67931.580000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index e492ac5d0..c079ee28b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,96 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077522 # Number of seconds simulated -sim_ticks 77521581000 # Number of ticks simulated -final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077516 # Number of seconds simulated +sim_ticks 77516381000 # Number of ticks simulated +final_tick 77516381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201802 # Simulator instruction rate (inst/s) -host_op_rate 201802 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41653613 # Simulator tick rate (ticks/s) -host_mem_usage 236024 # Number of bytes of host memory used -host_seconds 1861.10 # Real time elapsed on the host +host_inst_rate 185827 # Simulator instruction rate (inst/s) +host_op_rate 185827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38353496 # Simulator tick rate (ticks/s) +host_mem_usage 262456 # Number of bytes of host memory used +host_seconds 2021.10 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory -system.physmem.bytes_read::total 476288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2850716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3293225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6143941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2850716 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2850716 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2850716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3293225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6143941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7442 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 7442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 476288 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 527 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 436 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 405 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 337 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 305 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 414 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 542 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 454 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 379 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 77521491500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7442 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory +system.physmem.bytes_read::total 476608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221184 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3991 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7447 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2853384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3295097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6148481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2853384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2853384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2853384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3295097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6148481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7447 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7447 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 476608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 476608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 524 # Per bank write bursts +system.physmem.perBankRdBursts::1 653 # Per bank write bursts +system.physmem.perBankRdBursts::2 449 # Per bank write bursts +system.physmem.perBankRdBursts::3 600 # Per bank write bursts +system.physmem.perBankRdBursts::4 447 # Per bank write bursts +system.physmem.perBankRdBursts::5 455 # Per bank write bursts +system.physmem.perBankRdBursts::6 515 # Per bank write bursts +system.physmem.perBankRdBursts::7 524 # Per bank write bursts +system.physmem.perBankRdBursts::8 439 # Per bank write bursts +system.physmem.perBankRdBursts::9 407 # Per bank write bursts +system.physmem.perBankRdBursts::10 340 # Per bank write bursts +system.physmem.perBankRdBursts::11 306 # Per bank write bursts +system.physmem.perBankRdBursts::12 414 # Per bank write bursts +system.physmem.perBankRdBursts::13 542 # Per bank write bursts +system.physmem.perBankRdBursts::14 453 # Per bank write bursts +system.physmem.perBankRdBursts::15 379 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 77516291500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7447 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,138 +152,133 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 756 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 621.460317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 241.668493 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1200.727367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 238 31.48% 31.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 108 14.29% 45.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 62 8.20% 53.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 57 7.54% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 33 4.37% 65.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 22 2.91% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 21 2.78% 71.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 18 2.38% 73.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 1.72% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 16 2.12% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 6 0.79% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.59% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 9 1.19% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 9 1.19% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.66% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.79% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 17 2.25% 86.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 4 0.53% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.53% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.26% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.40% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 7 0.93% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.53% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 4 0.53% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.40% 90.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.79% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 7 0.93% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.13% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 4 0.53% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.40% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 93.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.53% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.40% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.26% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.26% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.13% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.13% 94.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.13% 95.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.13% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 2 0.26% 95.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 3 0.40% 95.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.26% 96.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.13% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.26% 96.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.13% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.13% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.13% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.26% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.13% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.13% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 2 0.26% 97.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.13% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.13% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.13% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.13% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.13% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.13% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.13% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.13% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.13% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.13% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 7 0.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 756 # Bytes accessed per row activation -system.physmem.totQLat 42048500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 179991000 # Sum of mem lat for all requests -system.physmem.totBusLat 37210000 # Total cycles spent in databus access -system.physmem.totBankLat 100732500 # Total cycles spent in bank access -system.physmem.avgQLat 5650.16 # Average queueing delay per request -system.physmem.avgBankLat 13535.68 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24185.84 # Average memory access latency -system.physmem.avgRdBW 6.14 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.14 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 1164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 404.618557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.969320 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 801.678722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 417 35.82% 35.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 184 15.81% 51.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 111 9.54% 61.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 97 8.33% 69.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 49 4.21% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 38 3.26% 76.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 28 2.41% 79.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 28 2.41% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 22 1.89% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 22 1.89% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 9 0.77% 86.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 13 1.12% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 15 1.29% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 15 1.29% 90.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 0.52% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 7 0.60% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 16 1.37% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.26% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.43% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.17% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.26% 93.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 11 0.95% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.34% 94.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 6 0.52% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.26% 95.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.34% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.26% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 3 0.26% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.26% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 3 0.26% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.17% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 5 0.43% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.09% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.09% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 2 0.17% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.09% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.09% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.09% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.17% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.17% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.09% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 1 0.09% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.09% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.17% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.09% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.09% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.09% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.09% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.09% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.09% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.09% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.09% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 3 0.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1164 # Bytes accessed per row activation +system.physmem.totQLat 59913750 # Total ticks spent queuing +system.physmem.totMemAccLat 199861250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37235000 # Total ticks spent in databus transfers +system.physmem.totBankLat 102712500 # Total ticks spent accessing banks +system.physmem.avgQLat 8045.35 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13792.47 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26837.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6686 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6283 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.37 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10416755.11 # Average gap between requests -system.membus.throughput 6143941 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4310 # Transaction distribution -system.membus.trans_dist::ReadResp 4310 # Transaction distribution -system.membus.trans_dist::ReadExReq 3132 # Transaction distribution -system.membus.trans_dist::ReadExResp 3132 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14884 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14884 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 476288 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476288 # Total data (bytes) +system.physmem.avgGap 10409062.91 # Average gap between requests +system.physmem.pageHitRate 84.37 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.56 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6148481 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4317 # Transaction distribution +system.membus.trans_dist::ReadResp 4317 # Transaction distribution +system.membus.trans_dist::ReadExReq 3130 # Transaction distribution +system.membus.trans_dist::ReadExResp 3130 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14894 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 476608 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 476608 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9304000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9290500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69668500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69563000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 50329141 # Number of BP lookups -system.cpu.branchPred.condPredicted 29286929 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1209855 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26570475 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23288927 # Number of BTB hits +system.cpu.branchPred.lookups 50307165 # Number of BP lookups +system.cpu.branchPred.condPredicted 29267262 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1212205 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26317362 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23268236 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.649645 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9008918 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1078 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 88.414014 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9019862 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1049 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101805775 # DTB read hits -system.cpu.dtb.read_misses 78244 # DTB read misses -system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 101884019 # DTB read accesses -system.cpu.dtb.write_hits 78424815 # DTB write hits -system.cpu.dtb.write_misses 1501 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 78426316 # DTB write accesses -system.cpu.dtb.data_hits 180230590 # DTB hits -system.cpu.dtb.data_misses 79745 # DTB misses -system.cpu.dtb.data_acv 48606 # DTB access violations -system.cpu.dtb.data_accesses 180310335 # DTB accesses -system.cpu.itb.fetch_hits 50278510 # ITB hits -system.cpu.itb.fetch_misses 355 # ITB misses +system.cpu.dtb.read_hits 101828804 # DTB read hits +system.cpu.dtb.read_misses 77910 # DTB read misses +system.cpu.dtb.read_acv 48604 # DTB read access violations +system.cpu.dtb.read_accesses 101906714 # DTB read accesses +system.cpu.dtb.write_hits 78465960 # DTB write hits +system.cpu.dtb.write_misses 1494 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 78467454 # DTB write accesses +system.cpu.dtb.data_hits 180294764 # DTB hits +system.cpu.dtb.data_misses 79404 # DTB misses +system.cpu.dtb.data_acv 48608 # DTB access violations +system.cpu.dtb.data_accesses 180374168 # DTB accesses +system.cpu.itb.fetch_hits 50297233 # ITB hits +system.cpu.itb.fetch_misses 369 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50278865 # ITB accesses +system.cpu.itb.fetch_accesses 50297602 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -295,139 +292,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 155043164 # number of cpu cycles simulated +system.cpu.numCycles 155032764 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51171798 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449189873 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50329141 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32297845 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78873322 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6177793 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19775166 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 51194246 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449183514 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50307165 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32288098 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78871438 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6172162 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19742012 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10164 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 10560 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50278510 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 413807 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154759425 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.902504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 50297233 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 412893 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.902843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324835 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75886103 49.03% 49.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4289159 2.77% 51.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6884479 4.45% 56.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5373987 3.47% 59.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11775541 7.61% 67.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7819980 5.05% 72.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5600753 3.62% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1832171 1.18% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35297252 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75867710 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4287409 2.77% 51.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6889018 4.45% 56.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5374428 3.47% 59.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11763624 7.60% 67.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7816659 5.05% 72.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5616009 3.63% 76.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1833388 1.18% 77.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35290903 22.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154759425 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324614 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.897192 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56546720 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15105326 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74238970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3943829 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4924580 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9495837 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4282 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 445245835 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12211 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4924580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59688043 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4892244 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 416020 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75141817 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9696721 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440741300 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25268 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8017940 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287478957 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 579418122 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 413955402 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 165462719 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324494 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.897346 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56553427 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15088868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74238964 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3941388 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4916501 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9487391 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4280 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 445247205 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12161 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4916501 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59699524 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4890372 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 419538 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75126102 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9687111 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440708166 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 170 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18989 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8005915 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287519835 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 579387338 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 414037453 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 165349884 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27946628 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36876 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 265 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27780890 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104697675 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80623147 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8951892 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6419862 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408420930 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401925039 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 976126 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32712161 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15467708 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154759425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.597096 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.996071 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27987506 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36934 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 290 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27862892 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104720393 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80633883 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8938676 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6410471 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408405086 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401961013 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 974296 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32695397 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15321619 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154739148 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.597669 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.996651 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28451061 18.38% 18.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25861408 16.71% 35.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25614965 16.55% 51.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24252162 15.67% 67.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21259746 13.74% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15502795 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8516760 5.50% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3980528 2.57% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1320000 0.85% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28425453 18.37% 18.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25900888 16.74% 35.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25580332 16.53% 51.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24228882 15.66% 67.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21279906 13.75% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15505584 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8490760 5.49% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3998033 2.58% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1329310 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154759425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154739148 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 34116 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 33873 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 59668 0.50% 0.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5432 0.05% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5299 0.04% 0.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1955339 16.54% 17.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1744150 14.75% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5075259 42.92% 75.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2944520 24.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 57850 0.49% 0.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5381 0.05% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5383 0.05% 0.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1948507 16.46% 17.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1748153 14.77% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5077907 42.90% 74.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2960216 25.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155814394 38.77% 38.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126224 0.53% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32839124 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7506811 1.87% 49.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2794214 0.70% 50.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556558 4.12% 54.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1581320 0.39% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155836210 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126206 0.53% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32826139 8.17% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7503461 1.87% 49.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2792900 0.69% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16557877 4.12% 54.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1579224 0.39% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued @@ -449,84 +446,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103393269 25.72% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79279544 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103415840 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79289575 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401925039 # Type of FU issued -system.cpu.iq.rate 2.592343 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11823783 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029418 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634356878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260386455 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234772610 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 337052534 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180795959 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161415506 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241485172 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172230069 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15009534 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401961013 # Type of FU issued +system.cpu.iq.rate 2.592749 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11837270 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029449 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 634505765 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260497209 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234812476 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336966975 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180652533 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161419314 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241576218 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172188484 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15052407 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9943188 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112068 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 49084 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7102418 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9965906 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 111384 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 48996 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7113154 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260799 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3689 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260897 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3921 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4924580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2516499 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 372884 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 433248692 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 121349 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104697675 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80623147 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 81 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 49084 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 956530 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 406825 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1363355 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398354690 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101932663 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3570349 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4916501 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2514816 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 370985 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 433209224 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130314 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104720393 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80633883 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 279 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 48996 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 956631 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 408580 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1365211 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398393230 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101955347 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3567783 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24827504 # number of nop insts executed -system.cpu.iew.exec_refs 180359006 # number of memory reference insts executed -system.cpu.iew.exec_branches 46573877 # Number of branches executed -system.cpu.iew.exec_stores 78426343 # Number of stores executed -system.cpu.iew.exec_rate 2.569315 # Inst execution rate -system.cpu.iew.wb_sent 396825960 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396188116 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193569295 # num instructions producing a value -system.cpu.iew.wb_consumers 271188688 # num instructions consuming a value +system.cpu.iew.exec_nop 24803859 # number of nop insts executed +system.cpu.iew.exec_refs 180422830 # number of memory reference insts executed +system.cpu.iew.exec_branches 46575028 # Number of branches executed +system.cpu.iew.exec_stores 78467483 # Number of stores executed +system.cpu.iew.exec_rate 2.569736 # Inst execution rate +system.cpu.iew.wb_sent 396861812 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396231790 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193564450 # num instructions producing a value +system.cpu.iew.wb_consumers 271143007 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.555341 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713781 # average fanout of values written-back +system.cpu.iew.wb_rate 2.555794 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713883 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34614887 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34575269 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1205659 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149834845 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.660693 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.995613 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1208013 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149822647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.660910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.995203 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55453685 37.01% 37.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22592497 15.08% 52.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13053957 8.71% 60.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11447163 7.64% 68.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8190236 5.47% 73.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5440968 3.63% 77.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5148789 3.44% 80.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3296235 2.20% 83.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25211315 16.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55444792 37.01% 37.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22572343 15.07% 52.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13039784 8.70% 60.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11474023 7.66% 68.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8200661 5.47% 73.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5438800 3.63% 77.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5171862 3.45% 80.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3280269 2.19% 83.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25200113 16.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149834845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149822647 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -537,212 +534,212 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25211315 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25200113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557900023 # The number of ROB reads -system.cpu.rob.rob_writes 871491746 # The number of ROB writes -system.cpu.timesIdled 3551 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 283739 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557859409 # The number of ROB reads +system.cpu.rob.rob_writes 871404727 # The number of ROB writes +system.cpu.timesIdled 3579 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 293616 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.412816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.412816 # CPI: Total CPI of All Threads -system.cpu.ipc 2.422389 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.422389 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 398140602 # number of integer regfile reads -system.cpu.int_regfile_writes 170166273 # number of integer regfile writes -system.cpu.fp_regfile_reads 156587084 # number of floating regfile reads -system.cpu.fp_regfile_writes 104079306 # number of floating regfile writes +system.cpu.cpi 0.412788 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.412788 # CPI: Total CPI of All Threads +system.cpu.ipc 2.422551 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.422551 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398219851 # number of integer regfile reads +system.cpu.int_regfile_writes 170183529 # number of integer regfile writes +system.cpu.fp_regfile_reads 156589680 # number of floating regfile reads +system.cpu.fp_regfile_writes 104065109 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7370748 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5062 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5062 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 666 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17190 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 571392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 571392 # Total data (bytes) +system.cpu.toL2Bus.throughput 7356381 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 659 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9023 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17161 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 570240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 570240 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5130000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5114000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6844000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6775000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6767250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6675000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2147 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.618681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50272888 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4074 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12339.933235 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2141 # number of replacements +system.cpu.icache.tags.tagsinuse 1831.580097 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 50291613 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4069 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12359.698452 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.618681 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894345 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894345 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50272888 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50272888 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50272888 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50272888 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50272888 # number of overall hits -system.cpu.icache.overall_hits::total 50272888 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5622 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5622 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5622 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5622 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5622 # number of overall misses -system.cpu.icache.overall_misses::total 5622 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 322487500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 322487500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 322487500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 322487500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 322487500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 322487500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50278510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50278510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50278510 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50278510 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50278510 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50278510 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1831.580097 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894326 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894326 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50291613 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50291613 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50291613 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50291613 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50291613 # number of overall hits +system.cpu.icache.overall_hits::total 50291613 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5620 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5620 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5620 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5620 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5620 # number of overall misses +system.cpu.icache.overall_misses::total 5620 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 330576500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 330576500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 330576500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 330576500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 330576500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 330576500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50297233 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50297233 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50297233 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50297233 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50297233 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50297233 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57361.704020 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 57361.704020 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 57361.704020 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 57361.704020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 57361.704020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 57361.704020 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 272 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.441281 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58821.441281 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58821.441281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58821.441281 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 892 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 68 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 148.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1548 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1548 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1548 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1548 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1548 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1548 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4074 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4074 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4074 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4074 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4074 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4074 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242677000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 242677000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242677000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 242677000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242677000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 242677000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1551 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1551 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1551 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1551 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1551 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1551 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4069 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4069 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4069 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4069 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4069 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4069 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249127500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249127500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249127500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249127500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249127500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249127500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59567.255768 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59567.255768 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.731138 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.731138 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011333 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090912 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.122330 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 621 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 372.314002 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2972.989124 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 661.395133 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011362 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090728 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020184 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,162 +748,162 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3453 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 857 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4310 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3989 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981191 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849349 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954328 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902557 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954328 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902557 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56435.908565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64807.781649 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58105.628909 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59852.875399 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59852.875399 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56435.908565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60921.824104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58840.002686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56435.908565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60921.824104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58840.002686 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 788 # number of replacements -system.cpu.dcache.tags.tagsinuse 3294.798817 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 160031202 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4188 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 38211.843840 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 780 # number of replacements +system.cpu.dcache.tags.tagsinuse 3295.992263 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 160011153 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4182 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38261.873027 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3294.798817 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804394 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 86530434 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86530434 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500763 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500763 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 160031197 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 160031197 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 160031197 # number of overall hits -system.cpu.dcache.overall_hits::total 160031197 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1798 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1798 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19966 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19966 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21764 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21764 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21764 # number of overall misses -system.cpu.dcache.overall_misses::total 21764 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114434250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114434250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1039316587 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1039316587 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1153750837 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1153750837 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1153750837 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1153750837 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86532232 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86532232 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 3295.992263 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804686 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804686 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 86510267 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86510267 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500882 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500882 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 160011149 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 160011149 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 160011149 # number of overall hits +system.cpu.dcache.overall_hits::total 160011149 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1786 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1786 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19847 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19847 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21633 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21633 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21633 # number of overall misses +system.cpu.dcache.overall_misses::total 21633 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114228250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114228250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1085833087 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1085833087 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1200061337 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1200061337 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1200061337 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1200061337 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86512053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86512053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 160052961 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 160052961 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 160052961 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 160052961 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 160032782 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 160032782 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 160032782 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 160032782 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000272 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000272 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63645.300334 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63645.300334 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52054.321697 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52054.321697 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53011.892897 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53011.892897 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 38531 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63957.586786 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63957.586786 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54710.187283 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54710.187283 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55473.643831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55473.643831 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 40366 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 654 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 653 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.915902 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.816233 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 666 # number of writebacks -system.cpu.dcache.writebacks::total 666 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 810 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 810 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16766 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16766 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17576 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17576 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17576 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17576 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3200 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3200 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4188 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4188 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4188 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4188 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67480500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67480500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218199250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 218199250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 285679750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 285679750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285679750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 285679750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 659 # number of writebacks +system.cpu.dcache.writebacks::total 659 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16657 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16657 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17451 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17451 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17451 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17451 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 992 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 992 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3190 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3190 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 68767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 68767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 229720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 229720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298487000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298487000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298487000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298487000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68300.101215 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68300.101215 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68187.265625 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68187.265625 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69321.572581 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69321.572581 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72012.539185 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72012.539185 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 8bc1d638d..93aa60ef6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,97 +1,99 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068375 # Number of seconds simulated -sim_ticks 68375005500 # Number of ticks simulated -final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068515 # Number of seconds simulated +sim_ticks 68515366500 # Number of ticks simulated +final_tick 68515366500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143200 # Simulator instruction rate (inst/s) -host_op_rate 183074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35860683 # Simulator tick rate (ticks/s) -host_mem_usage 256516 # Number of bytes of host memory used -host_seconds 1906.68 # Real time elapsed on the host +host_inst_rate 128186 # Simulator instruction rate (inst/s) +host_op_rate 163879 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32166693 # Simulator tick rate (ticks/s) +host_mem_usage 283052 # Number of bytes of host memory used +host_seconds 2130.01 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 194304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory system.physmem.bytes_read::total 466432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194176 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3034 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 194304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194304 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory system.physmem.num_reads::total 7288 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2839868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3981806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6821674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2839868 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2839868 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2839868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3981806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6821674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7288 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 7288 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 466432 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 466432 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 802 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 526 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 442 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 353 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 612 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 506 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68374814000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7288 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 2835919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3971781 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6807699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2835919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2835919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2835919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3971781 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6807699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7289 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7289 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 466496 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 466496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 607 # Per bank write bursts +system.physmem.perBankRdBursts::1 801 # Per bank write bursts +system.physmem.perBankRdBursts::2 608 # Per bank write bursts +system.physmem.perBankRdBursts::3 526 # Per bank write bursts +system.physmem.perBankRdBursts::4 443 # Per bank write bursts +system.physmem.perBankRdBursts::5 353 # Per bank write bursts +system.physmem.perBankRdBursts::6 161 # Per bank write bursts +system.physmem.perBankRdBursts::7 217 # Per bank write bursts +system.physmem.perBankRdBursts::8 207 # Per bank write bursts +system.physmem.perBankRdBursts::9 294 # Per bank write bursts +system.physmem.perBankRdBursts::10 325 # Per bank write bursts +system.physmem.perBankRdBursts::11 416 # Per bank write bursts +system.physmem.perBankRdBursts::12 529 # Per bank write bursts +system.physmem.perBankRdBursts::13 687 # Per bank write bursts +system.physmem.perBankRdBursts::14 611 # Per bank write bursts +system.physmem.perBankRdBursts::15 504 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 68515346000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7289 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,119 +152,120 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 639.554318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 239.565124 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1324.415379 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 223 31.06% 31.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 101 14.07% 45.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 63 8.77% 53.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 56 7.80% 61.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 31 4.32% 66.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 32 4.46% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 16 2.23% 72.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 24 3.34% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.25% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 16 2.23% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 9 1.25% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.67% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.70% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 9 1.25% 84.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 7 0.97% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.84% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 0.56% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.42% 87.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.70% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.42% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.42% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.56% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 5 0.70% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.56% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.42% 91.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.42% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.14% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.28% 94.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.14% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.14% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.14% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 2 0.28% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 3 0.42% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.14% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.14% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.28% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.14% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 1 0.14% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.14% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.14% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.28% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.28% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 10 1.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 718 # Bytes accessed per row activation -system.physmem.totQLat 36604250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 168483000 # Sum of mem lat for all requests -system.physmem.totBusLat 36440000 # Total cycles spent in databus access -system.physmem.totBankLat 95438750 # Total cycles spent in bank access -system.physmem.avgQLat 5022.54 # Average queueing delay per request -system.physmem.avgBankLat 13095.33 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23117.86 # Average memory access latency -system.physmem.avgRdBW 6.82 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.82 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 1271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 365.973249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.155512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 760.469459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 520 40.91% 40.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 218 17.15% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 133 10.46% 68.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 73 5.74% 74.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 41 3.23% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 37 2.91% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 29 2.28% 82.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 36 2.83% 85.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 15 1.18% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 25 1.97% 88.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 5 0.39% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 14 1.10% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 4 0.31% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 0.63% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.39% 91.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 8 0.63% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 8 0.63% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 6 0.47% 93.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 7 0.55% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.16% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 5 0.39% 94.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 5 0.39% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.16% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.24% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.24% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.24% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 4 0.31% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.31% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 3 0.24% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.16% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.24% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1271 # Bytes accessed per row activation +system.physmem.totQLat 60705750 # Total ticks spent queuing +system.physmem.totMemAccLat 196384500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36445000 # Total ticks spent in databus transfers +system.physmem.totBankLat 99233750 # Total ticks spent accessing banks +system.physmem.avgQLat 8328.41 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13614.18 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26942.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6570 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9381835.07 # Average gap between requests -system.membus.throughput 6821674 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4467 # Transaction distribution -system.membus.trans_dist::ReadResp 4467 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 2821 # Transaction distribution -system.membus.trans_dist::ReadExResp 2821 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14586 # Packet count per connected master and slave (bytes) +system.physmem.avgGap 9399827.96 # Average gap between requests +system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.15 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6807699 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4464 # Transaction distribution +system.membus.trans_dist::ReadResp 4463 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 2825 # Transaction distribution +system.membus.trans_dist::ReadExResp 2825 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14581 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466432 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 466432 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 466432 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8910500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8930000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68010245 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67824498 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 35388733 # Number of BP lookups -system.cpu.branchPred.condPredicted 21200896 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1644934 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19122518 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16795427 # Number of BTB hits +system.cpu.branchPred.lookups 35429100 # Number of BP lookups +system.cpu.branchPred.condPredicted 21225812 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1661684 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19625450 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16825398 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.830625 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6785564 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8441 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 85.732546 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6780528 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8438 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -306,100 +309,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136750012 # number of cpu cycles simulated +system.cpu.numCycles 137030734 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38949353 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317676023 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35388733 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23580991 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70834954 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6803690 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21493719 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1383 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37560816 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 509146 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136426737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.984407 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454366 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 39012994 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 318080298 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35429100 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23605926 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70957862 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6891670 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21493708 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1614 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37614130 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 516506 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136684696 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.983709 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454255 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66221739 48.54% 48.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6780898 4.97% 53.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5694782 4.17% 57.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6088849 4.46% 62.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4909575 3.60% 65.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4088004 3.00% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3182942 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4139594 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35320354 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66359879 48.55% 48.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6789497 4.97% 53.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5708838 4.18% 57.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6107274 4.47% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4922167 3.60% 65.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4085695 2.99% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3186230 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4137086 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35388030 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136426737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258784 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.323042 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45449120 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16657240 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66693516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2548377 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5078484 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7335953 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69077 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401163284 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 211870 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5078484 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50979253 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1928009 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 329001 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63651330 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14460660 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 393604020 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1657735 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10191603 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1124 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432142984 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2330358431 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1572902779 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200313916 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136684696 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258549 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.321233 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45532866 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16645865 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66825856 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2530463 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5149646 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7344267 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69062 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401846627 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 213953 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5149646 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 51082336 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1907734 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 332489 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63745566 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14466925 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 394259426 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1660076 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10182958 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1156 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432806895 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2333828888 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1575589736 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200458039 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47576791 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11831 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11830 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36438205 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103461367 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91301104 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4273842 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5281559 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384115412 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 48240702 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11816 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11815 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36507596 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103616420 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91395607 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4296163 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5310753 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384620101 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 373986631 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1200950 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34324808 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 86133615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 374263749 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1212133 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34826495 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 87778881 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136426737 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.741300 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.023490 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 136684696 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.738154 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.024883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24929928 18.27% 18.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19932793 14.61% 32.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20578448 15.08% 47.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18152288 13.31% 61.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24038629 17.62% 78.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15699021 11.51% 90.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8799073 6.45% 96.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3376437 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 920120 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25139035 18.39% 18.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19926957 14.58% 32.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20565636 15.05% 48.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18170176 13.29% 61.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24039516 17.59% 78.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15735356 11.51% 90.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8814568 6.45% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3374876 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 918576 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136426737 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136684696 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8934 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4692 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8700 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4687 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -418,127 +421,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46301 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46352 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7704 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 463 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7624 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 437 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190616 1.07% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 3949 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241166 1.36% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9286471 52.35% 55.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7950501 44.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190912 1.08% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4399 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241386 1.36% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9273710 52.31% 55.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7950548 44.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126356667 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175742 0.58% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6779199 1.81% 36.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8471128 2.27% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3427474 0.92% 39.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595849 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20859409 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172834 1.92% 47.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127502 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126477598 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175809 0.58% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6782032 1.81% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8476848 2.26% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3430270 0.92% 39.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595622 0.43% 39.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20869694 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7174273 1.92% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130259 1.91% 49.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101548323 27.15% 76.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88297215 23.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101673859 27.17% 76.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88302195 23.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 373986631 # Type of FU issued -system.cpu.iq.rate 2.734820 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17740799 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047437 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653979183 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 288208067 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249975124 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249362565 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130269118 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118046236 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263130568 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128596862 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11091317 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374263749 # Type of FU issued +system.cpu.iq.rate 2.731239 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17728757 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047370 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654715892 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 289089659 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250133425 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249437192 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130393861 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118075733 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263363212 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128629294 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11082647 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8812619 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 109039 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14268 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8925521 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8967672 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 108753 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14263 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9020024 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 177200 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1779 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 174668 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1902 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5078484 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 284505 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35417 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384139745 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 871852 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103461367 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91301104 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 5149646 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 272927 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35696 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384644450 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 871710 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103616420 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91395607 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 311 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 371 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14268 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1284870 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 366093 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1650963 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370046005 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100262370 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3940626 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 342 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14263 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1301323 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 370771 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1672094 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370296137 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100380791 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3967612 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1545 # number of nop insts executed -system.cpu.iew.exec_refs 187486507 # number of memory reference insts executed -system.cpu.iew.exec_branches 32007235 # Number of branches executed -system.cpu.iew.exec_stores 87224137 # Number of stores executed -system.cpu.iew.exec_rate 2.706003 # Inst execution rate -system.cpu.iew.wb_sent 368676629 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368021360 # cumulative count of insts written-back -system.cpu.iew.wb_producers 182960102 # num instructions producing a value -system.cpu.iew.wb_consumers 363631500 # num instructions consuming a value +system.cpu.iew.exec_nop 1561 # number of nop insts executed +system.cpu.iew.exec_refs 187597519 # number of memory reference insts executed +system.cpu.iew.exec_branches 32011770 # Number of branches executed +system.cpu.iew.exec_stores 87216728 # Number of stores executed +system.cpu.iew.exec_rate 2.702285 # Inst execution rate +system.cpu.iew.wb_sent 368879898 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368209158 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183085663 # num instructions producing a value +system.cpu.iew.wb_consumers 363859128 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.691198 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503147 # average fanout of values written-back +system.cpu.iew.wb_rate 2.687055 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503177 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35074746 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35579507 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1576251 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131348253 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.657554 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659541 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1592984 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131535050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.653780 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659242 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34568937 26.32% 26.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28443468 21.66% 47.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13309150 10.13% 58.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11454276 8.72% 66.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13766870 10.48% 77.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7405227 5.64% 82.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3876233 2.95% 85.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3903284 2.97% 88.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14620808 11.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34731076 26.40% 26.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28455457 21.63% 48.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13342482 10.14% 58.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11433888 8.69% 66.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13770355 10.47% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7412668 5.64% 82.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3873056 2.94% 85.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3888664 2.96% 88.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14627404 11.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131348253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131535050 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -549,220 +552,220 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14620808 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14627404 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 500864729 # The number of ROB reads -system.cpu.rob.rob_writes 773362160 # The number of ROB writes -system.cpu.timesIdled 6666 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 323275 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501549691 # The number of ROB reads +system.cpu.rob.rob_writes 774443009 # The number of ROB writes +system.cpu.timesIdled 6642 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 346038 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.500848 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.500848 # CPI: Total CPI of All Threads -system.cpu.ipc 1.996612 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.996612 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1768925077 # number of integer regfile reads -system.cpu.int_regfile_writes 232843327 # number of integer regfile writes -system.cpu.fp_regfile_reads 188113453 # number of floating regfile reads -system.cpu.fp_regfile_writes 132483580 # number of floating regfile writes -system.cpu.misc_regfile_reads 566770577 # number of misc regfile reads +system.cpu.cpi 0.501877 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.501877 # CPI: Total CPI of All Threads +system.cpu.ipc 1.992522 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.992522 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1770065591 # number of integer regfile reads +system.cpu.int_regfile_writes 233053939 # number of integer regfile writes +system.cpu.fp_regfile_reads 188169392 # number of floating regfile reads +system.cpu.fp_regfile_writes 132536105 # number of floating regfile writes +system.cpu.misc_regfile_reads 566956802 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20110273 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17610 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17610 # Transaction distribution +system.cpu.toL2Bus.throughput 20102702 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17643 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17642 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41937 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2842 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2842 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31749 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 42006 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1015808 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1374656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1374656 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 384 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11782000 # Layer occupancy (ticks) +system.cpu.toL2Bus.tot_pkt_size::total 1377088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1377088 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11799000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24379238 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24347988 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7509966 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7401462 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13946 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.498389 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37543488 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2370.768376 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13986 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.638823 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37596770 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15875 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2368.300472 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.498389 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902587 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902587 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37543488 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37543488 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37543488 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37543488 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37543488 # number of overall hits -system.cpu.icache.overall_hits::total 37543488 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17326 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17326 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17326 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17326 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17326 # number of overall misses -system.cpu.icache.overall_misses::total 17326 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 439962484 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 439962484 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 439962484 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 439962484 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 439962484 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 439962484 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37560814 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37560814 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37560814 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37560814 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37560814 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37560814 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.638823 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902656 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902656 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37596770 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37596770 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37596770 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37596770 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37596770 # number of overall hits +system.cpu.icache.overall_hits::total 37596770 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17358 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17358 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17358 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17358 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17358 # number of overall misses +system.cpu.icache.overall_misses::total 17358 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 450239984 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 450239984 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 450239984 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 450239984 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 450239984 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 450239984 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37614128 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37614128 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37614128 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37614128 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37614128 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37614128 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25393.194275 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25393.194275 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25393.194275 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25393.194275 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 913 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25938.471252 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25938.471252 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25938.471252 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25938.471252 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2006 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 87.217391 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1486 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1486 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1486 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1486 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1486 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1486 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15840 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15840 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15840 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15840 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15840 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15840 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 349391259 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 349391259 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 349391259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 349391259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 349391259 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 349391259 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1481 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1481 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1481 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1481 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1481 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1481 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15877 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15877 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15877 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15877 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15877 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15877 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359424009 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 359424009 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359424009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 359424009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359424009 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 359424009 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22057.528977 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22057.528977 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22057.528977 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22057.528977 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22057.528977 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22057.528977 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22638.030421 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22638.030421 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22638.030421 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22638.030421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22638.030421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22638.030421 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2781.709770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 780.965360 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011446 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084891 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.023833 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120170 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12788 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 298 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13086 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 378.229398 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2786.621740 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 774.920301 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71821.178938 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71315.318077 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,176 +775,176 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 52 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808041 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253076 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994010 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994010 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356521 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356521 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54944.133158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56670.272156 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55497.873293 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10201 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10201 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54420.684155 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54420.684155 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54944.133158 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54944.133158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994018 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994018 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355891 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355891 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58105.037866 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61760.336370 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59273.521505 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.415929 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.415929 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1414 # number of replacements -system.cpu.dcache.tags.tagsinuse 3101.863625 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170862922 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3101.535581 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170993874 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4608 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37079.627170 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37108.045573 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3101.863625 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757291 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757291 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88809743 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88809743 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031242 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031242 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11022 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11022 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 3101.535581 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757211 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757211 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88940583 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88940583 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031381 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031381 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11003 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11003 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170840985 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170840985 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170840985 # number of overall hits -system.cpu.dcache.overall_hits::total 170840985 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3962 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3962 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21423 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21423 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170971964 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170971964 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170971964 # number of overall hits +system.cpu.dcache.overall_hits::total 170971964 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3947 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3947 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21284 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21284 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25385 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25385 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25385 # number of overall misses -system.cpu.dcache.overall_misses::total 25385 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 221925207 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 221925207 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1196433403 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1196433403 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 157000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 157000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1418358610 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1418358610 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1418358610 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1418358610 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88813705 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88813705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25231 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25231 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25231 # number of overall misses +system.cpu.dcache.overall_misses::total 25231 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 233964205 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 233964205 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1259611139 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1259611139 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1493575344 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1493575344 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1493575344 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1493575344 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88944530 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88944530 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11024 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11005 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11005 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170866370 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170866370 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170866370 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170866370 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000149 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000149 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000149 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56013.429329 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56013.429329 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55848.079307 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55848.079307 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55873.886547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55873.886547 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25209 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1225 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 407 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 170997195 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170997195 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170997195 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170997195 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000259 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59276.464403 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59276.464403 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59181.128500 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59181.128500 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59196.042329 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59196.042329 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28298 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 410 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.938575 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 102.083333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.019512 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1037 # number of writebacks system.cpu.dcache.writebacks::total 1037 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2191 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2191 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18581 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18581 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2179 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2179 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18442 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18442 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20772 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20772 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20772 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20772 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20621 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20621 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20621 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20621 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1768 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1768 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4613 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4613 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4613 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4613 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106433039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 106433039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191658495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 191658495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298091534 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298091534 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298091534 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298091534 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4610 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4610 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4610 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4610 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 113556540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 113556540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 202620998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 202620998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 316177538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 316177538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 316177538 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 316177538 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -950,14 +953,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60097.706945 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60097.706945 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67437.894089 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67437.894089 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64228.812217 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64228.812217 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71295.213934 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71295.213934 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 580dd6a6a..23516d587 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.631883 # Number of seconds simulated -sim_ticks 631883288500 # Number of ticks simulated -final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.631518 # Number of seconds simulated +sim_ticks 631518097500 # Number of ticks simulated +final_tick 631518097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151695 # Simulator instruction rate (inst/s) -host_op_rate 151695 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52578725 # Simulator tick rate (ticks/s) -host_mem_usage 240040 # Number of bytes of host memory used -host_seconds 12017.85 # Real time elapsed on the host +host_inst_rate 141288 # Simulator instruction rate (inst/s) +host_op_rate 141288 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48943367 # Simulator tick rate (ticks/s) +host_mem_usage 266484 # Number of bytes of host memory used +host_seconds 12903.04 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295168 # Number of bytes read from this memory -system.physmem.bytes_read::total 30471232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176064 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295488 # Number of bytes read from this memory +system.physmem.bytes_read::total 30471616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176128 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473362 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476113 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2752 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473367 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476119 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 278634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47944246 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48222880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 278634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 278634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6776745 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6776745 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6776745 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 278634 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47944246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54999625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476114 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 66908 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 476114 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 66908 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 30471232 # Total number of bytes read from memory -system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30471232 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29852 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29789 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29692 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29858 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29849 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29915 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29583 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29509 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29637 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4164 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4223 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4099 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4262 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4335 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4247 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4100 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4157 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 631883258500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476114 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66908 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 408378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66892 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 278896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47972478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48251374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 278896 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 278896 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6780664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6780664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6780664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 278896 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47972478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55032038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476119 # Number of read requests accepted +system.physmem.writeReqs 66908 # Number of write requests accepted +system.physmem.readBursts 476119 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30465984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue +system.physmem.bytesWritten 4281664 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30471616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 29449 # Per bank write bursts +system.physmem.perBankRdBursts::1 29798 # Per bank write bursts +system.physmem.perBankRdBursts::2 29850 # Per bank write bursts +system.physmem.perBankRdBursts::3 29793 # Per bank write bursts +system.physmem.perBankRdBursts::4 29695 # Per bank write bursts +system.physmem.perBankRdBursts::5 29771 # Per bank write bursts +system.physmem.perBankRdBursts::6 29867 # Per bank write bursts +system.physmem.perBankRdBursts::7 29856 # Per bank write bursts +system.physmem.perBankRdBursts::8 29771 # Per bank write bursts +system.physmem.perBankRdBursts::9 29894 # Per bank write bursts +system.physmem.perBankRdBursts::10 29844 # Per bank write bursts +system.physmem.perBankRdBursts::11 29915 # Per bank write bursts +system.physmem.perBankRdBursts::12 29793 # Per bank write bursts +system.physmem.perBankRdBursts::13 29587 # Per bank write bursts +system.physmem.perBankRdBursts::14 29511 # Per bank write bursts +system.physmem.perBankRdBursts::15 29637 # Per bank write bursts +system.physmem.perBankWrBursts::0 4125 # Per bank write bursts +system.physmem.perBankWrBursts::1 4164 # Per bank write bursts +system.physmem.perBankWrBursts::2 4223 # Per bank write bursts +system.physmem.perBankWrBursts::3 4160 # Per bank write bursts +system.physmem.perBankWrBursts::4 4142 # Per bank write bursts +system.physmem.perBankWrBursts::5 4099 # Per bank write bursts +system.physmem.perBankWrBursts::6 4262 # Per bank write bursts +system.physmem.perBankWrBursts::7 4226 # Per bank write bursts +system.physmem.perBankWrBursts::8 4233 # Per bank write bursts +system.physmem.perBankWrBursts::9 4334 # Per bank write bursts +system.physmem.perBankWrBursts::10 4241 # Per bank write bursts +system.physmem.perBankWrBursts::11 4241 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4100 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4157 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 631518039500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 476119 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66908 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 408579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 429 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,29 +127,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -157,151 +159,190 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 166584 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 208.562071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.103843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 536.299000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 52740 31.66% 31.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 42613 25.58% 57.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 39946 23.98% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 25368 15.23% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 277 0.17% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 122 0.07% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 95 0.06% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 87 0.05% 96.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 83 0.05% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 94 0.06% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 111 0.07% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 115 0.07% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 83 0.05% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 90 0.05% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 77 0.05% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 81 0.05% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 76 0.05% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 74 0.04% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 77 0.05% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 82 0.05% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3443 2.07% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 36 0.02% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 3 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 3 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 4 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 586 0.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 166584 # Bytes accessed per row activation -system.physmem.totQLat 1351239750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14292404750 # Sum of mem lat for all requests -system.physmem.totBusLat 2380120000 # Total cycles spent in databus access -system.physmem.totBankLat 10561045000 # Total cycles spent in bank access -system.physmem.avgQLat 2838.60 # Average queueing delay per request -system.physmem.avgBankLat 22185.95 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30024.55 # Average memory access latency -system.physmem.avgRdBW 48.22 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.22 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.78 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 182335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 190.554573 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 126.681752 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 408.631079 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 68422 37.53% 37.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 48844 26.79% 64.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 37964 20.82% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 20159 11.06% 96.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 264 0.14% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 246 0.13% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 141 0.08% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 184 0.10% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 113 0.06% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 137 0.08% 96.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 96 0.05% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 186 0.10% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 81 0.04% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 159 0.09% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 151 0.08% 97.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 133 0.07% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 108 0.06% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 148 0.08% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 143 0.08% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 80 0.04% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 131 0.07% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 1760 0.97% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 1531 0.84% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 10 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 19 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 18 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 8 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 14 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 14 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 13 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 14 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 6 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 10 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 10 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 20 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 12 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 11 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 18 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 13 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 12 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 17 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 12 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 11 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 14 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 18 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 12 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 10 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 14 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 17 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 14 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 13 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 6 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 12 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 9 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 8 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 11 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 18 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 9 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 16 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 12 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 17 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 14 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 15 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 5 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 16 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 14 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 17 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 13 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 15 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 11 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 18 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 12 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 8 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 9 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 12 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 6 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 11 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 11 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 15 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 12 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 12 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 11 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 16 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 12 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 11 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 13 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568 16 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 12 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 12 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 17 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 10 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888 11 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 22 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 11 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080 8 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 12 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208 26 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272 26 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336 39 0.02% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400 37 0.02% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464 7 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528 7 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592 6 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656 3 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720 7 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784 8 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848 54 0.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 182335 # Bytes accessed per row activation +system.physmem.totQLat 2888041500 # Total ticks spent queuing +system.physmem.totMemAccLat 14116019000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2380155000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8847822500 # Total ticks spent accessing banks +system.physmem.avgQLat 6066.92 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18586.65 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29653.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.78 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 11.01 # Average write queue length over time -system.physmem.readRowHits 326147 # Number of row buffer hits during reads -system.physmem.writeRowHits 50200 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes -system.physmem.avgGap 1163642.10 # Average gap between requests -system.membus.throughput 54999625 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409258 # Transaction distribution -system.membus.trans_dist::ReadResp 409257 # Transaction distribution +system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.28 # Average write queue length when enqueuing +system.physmem.readRowHits 310714 # Number of row buffer hits during reads +system.physmem.writeRowHits 49883 # Number of row buffer hits during writes +system.physmem.readRowHitRate 65.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes +system.physmem.avgGap 1162958.82 # Average gap between requests +system.physmem.pageHitRate 66.42 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 25.73 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 55031937 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 409266 # Transaction distribution +system.membus.trans_dist::ReadResp 409265 # Transaction distribution system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66856 # Transaction distribution -system.membus.trans_dist::ReadExResp 66856 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019135 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019135 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34753344 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34753344 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34753344 # Total data (bytes) +system.membus.trans_dist::ReadExReq 66853 # Transaction distribution +system.membus.trans_dist::ReadExResp 66853 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019145 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1019145 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34753664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34753664 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34753664 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1232718500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1230653000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4527448500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4488013000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 388901077 # Number of BP lookups -system.cpu.branchPred.condPredicted 255997466 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25785874 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 315302493 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258353491 # Number of BTB hits +system.cpu.branchPred.lookups 388926557 # Number of BP lookups +system.cpu.branchPred.condPredicted 255987580 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25808786 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 317451636 # Number of BTB lookups +system.cpu.branchPred.BTBHits 258383726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.938296 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57247417 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6895 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.393100 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 57269217 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6785 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 522159380 # DTB read hits -system.cpu.dtb.read_misses 590851 # DTB read misses +system.cpu.dtb.read_hits 522276153 # DTB read hits +system.cpu.dtb.read_misses 591029 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 522750231 # DTB read accesses -system.cpu.dtb.write_hits 283002528 # DTB write hits -system.cpu.dtb.write_misses 50162 # DTB write misses +system.cpu.dtb.read_accesses 522867182 # DTB read accesses +system.cpu.dtb.write_hits 283024283 # DTB write hits +system.cpu.dtb.write_misses 50282 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283052690 # DTB write accesses -system.cpu.dtb.data_hits 805161908 # DTB hits -system.cpu.dtb.data_misses 641013 # DTB misses +system.cpu.dtb.write_accesses 283074565 # DTB write accesses +system.cpu.dtb.data_hits 805300436 # DTB hits +system.cpu.dtb.data_misses 641311 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 805802921 # DTB accesses -system.cpu.itb.fetch_hits 394748041 # ITB hits -system.cpu.itb.fetch_misses 630 # ITB misses +system.cpu.dtb.data_accesses 805941747 # DTB accesses +system.cpu.itb.fetch_hits 394923337 # ITB hits +system.cpu.itb.fetch_misses 673 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 394748671 # ITB accesses +system.cpu.itb.fetch_accesses 394924010 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -315,98 +356,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1263766578 # number of cpu cycles simulated +system.cpu.numCycles 1263036196 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 409917284 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3274493634 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388901077 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315600908 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 630100236 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157853545 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75868728 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6965 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 394748041 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11243258 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1247472116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.624903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.139302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 410109211 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3275361916 # Number of instructions fetch has processed +system.cpu.fetch.Branches 388926557 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315652943 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 630278695 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157942219 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 76359250 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7183 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 394923337 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11250821 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1248398015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.623652 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.139094 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 617371880 49.49% 49.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57447684 4.61% 54.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43286408 3.47% 57.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71838123 5.76% 63.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129156368 10.35% 73.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46178870 3.70% 77.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41219816 3.30% 80.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7663689 0.61% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233309278 18.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 618119320 49.51% 49.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57470502 4.60% 54.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43321703 3.47% 57.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71848580 5.76% 63.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129169735 10.35% 73.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46220345 3.70% 77.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41223037 3.30% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7614963 0.61% 81.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 233409830 18.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1247472116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307732 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.591059 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438201536 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62209215 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 606414230 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9080438 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131566697 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31709739 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12402 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3193700667 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46294 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131566697 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467502237 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27351671 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28189 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 585846018 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 35177304 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3094945067 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15191 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28875434 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2054257390 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3579193509 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3493818421 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 85375087 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1248398015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307930 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.593245 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438388188 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62722157 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 606598506 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9057712 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131631452 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 31714965 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12425 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3194311917 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46335 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131631452 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467678490 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27888697 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27235 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 586017174 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35154967 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3095577928 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15278 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28853292 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2054701915 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3579840201 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3494452831 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 85387369 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 669288320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4234 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109722880 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 743716097 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351305913 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 69009362 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8819654 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2623113984 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 93 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2159995607 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17916537 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 800006156 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 726205656 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 54 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1247472116 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.731498 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.803359 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 669732845 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4230 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109697167 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 743928173 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351370571 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 69056444 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8824928 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2623617017 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2160251370 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17943532 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 800506396 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 726504541 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1248398015 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.730419 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 450995748 36.15% 36.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196797874 15.78% 51.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251286832 20.14% 72.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120757727 9.68% 81.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104717605 8.39% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79196335 6.35% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24309118 1.95% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17642931 1.41% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1767946 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 451794383 36.19% 36.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 196881070 15.77% 51.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251357257 20.13% 72.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120660417 9.67% 81.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104720930 8.39% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79314006 6.35% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24236778 1.94% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17665275 1.42% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1767899 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1247472116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1248398015 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146304 3.11% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146213 3.11% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.11% # attempts to use FU when none available @@ -435,16 +476,16 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.11% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25641829 69.66% 72.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10023004 27.23% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25664248 69.68% 72.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10022787 27.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234267096 57.14% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17095 0.00% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234386708 57.14% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17098 0.00% 57.14% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851364 1.29% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851280 1.29% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254692 0.38% 58.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 7204649 0.33% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued @@ -469,84 +510,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589311123 27.28% 86.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293086828 13.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589426190 27.29% 86.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293107997 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2159995607 # Type of FU issued -system.cpu.iq.rate 1.709173 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36811137 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017042 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5471089482 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3335131409 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1989836434 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151101522 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88062076 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73609987 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2119354134 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449858 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62153092 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2160251370 # Type of FU issued +system.cpu.iq.rate 1.710364 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36833248 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017050 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5472576315 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3336085104 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1990052080 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151101220 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88112403 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73609796 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2119632114 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77449752 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62130294 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 232646071 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31940 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 75814 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140511017 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 232858147 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12904 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76517 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140575675 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4421 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2886 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4420 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2986 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131566697 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13318869 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540046 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2986589244 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 731786 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 743716097 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351305913 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 93 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 134266 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1522 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 75814 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25780444 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 27789 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25808233 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2065907774 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 522750367 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94087833 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131631452 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13854870 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540713 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2987064962 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 734569 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 743928173 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351370571 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 134613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1496 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76517 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25801220 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 30372 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25831592 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2066130188 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 522867337 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94121182 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363475167 # number of nop insts executed -system.cpu.iew.exec_refs 805803501 # number of memory reference insts executed -system.cpu.iew.exec_branches 277598296 # Number of branches executed -system.cpu.iew.exec_stores 283053134 # Number of stores executed -system.cpu.iew.exec_rate 1.634723 # Inst execution rate -system.cpu.iew.wb_sent 2065776472 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2063446421 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1180901001 # num instructions producing a value -system.cpu.iew.wb_consumers 1753223374 # num instructions consuming a value +system.cpu.iew.exec_nop 363447857 # number of nop insts executed +system.cpu.iew.exec_refs 805942372 # number of memory reference insts executed +system.cpu.iew.exec_branches 277625839 # Number of branches executed +system.cpu.iew.exec_stores 283075035 # Number of stores executed +system.cpu.iew.exec_rate 1.635844 # Inst execution rate +system.cpu.iew.wb_sent 2066015512 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2063661876 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1180966909 # num instructions producing a value +system.cpu.iew.wb_consumers 1753315236 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.632775 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673560 # average fanout of values written-back +system.cpu.iew.wb_rate 1.633890 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673562 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 960640976 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 961121272 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25773841 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1115905419 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.800321 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.507651 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25796748 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1116766563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.798932 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.506928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 496848865 44.52% 44.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228666687 20.49% 65.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119877587 10.74% 75.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58838951 5.27% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50501288 4.53% 85.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24162159 2.17% 87.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19119877 1.71% 89.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16606359 1.49% 90.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101283646 9.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 497624739 44.56% 44.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228755329 20.48% 65.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119853189 10.73% 75.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58815833 5.27% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50567042 4.53% 85.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24161277 2.16% 87.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19140455 1.71% 89.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16628477 1.49% 90.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101220222 9.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1115905419 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1116766563 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -557,212 +598,212 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101283646 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101220222 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3978613943 # The number of ROB reads -system.cpu.rob.rob_writes 6070825883 # The number of ROB writes -system.cpu.timesIdled 341889 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16294462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3980018807 # The number of ROB reads +system.cpu.rob.rob_writes 6071851296 # The number of ROB writes +system.cpu.timesIdled 346634 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 14638181 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.693218 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.693218 # CPI: Total CPI of All Threads -system.cpu.ipc 1.442548 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.442548 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2627733458 # number of integer regfile reads -system.cpu.int_regfile_writes 1496469824 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811377 # number of floating regfile reads -system.cpu.fp_regfile_writes 52661114 # number of floating regfile writes +system.cpu.cpi 0.692817 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.692817 # CPI: Total CPI of All Threads +system.cpu.ipc 1.443382 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.443382 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2627972093 # number of integer regfile reads +system.cpu.int_regfile_writes 1496658984 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811105 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661052 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 165896459 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1470295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1470294 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71645 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71645 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20089 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159776 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3179865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104184384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104827200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104827200 # Total data (bytes) +system.cpu.toL2Bus.throughput 165988542 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1470277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1470276 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 71640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 71640 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159755 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3179804 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 641536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104183232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 104824768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 104824768 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914949000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 914915000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15605000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 15531000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2398320750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2359590250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 8334 # number of replacements -system.cpu.icache.tags.tagsinuse 1655.074457 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 394735107 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10044 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 39300.588112 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 8311 # number of replacements +system.cpu.icache.tags.tagsinuse 1658.001589 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 394910394 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10024 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 39396.487829 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1655.074457 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.808142 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.808142 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 394735107 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 394735107 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 394735107 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 394735107 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 394735107 # number of overall hits -system.cpu.icache.overall_hits::total 394735107 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12934 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12934 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12934 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12934 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12934 # number of overall misses -system.cpu.icache.overall_misses::total 12934 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 381722499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 381722499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 381722499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 381722499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 381722499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 381722499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 394748041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 394748041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 394748041 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 394748041 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 394748041 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 394748041 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1658.001589 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.809571 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.809571 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 394910394 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 394910394 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 394910394 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 394910394 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 394910394 # number of overall hits +system.cpu.icache.overall_hits::total 394910394 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12943 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12943 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12943 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12943 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12943 # number of overall misses +system.cpu.icache.overall_misses::total 12943 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 383675499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 383675499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 383675499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 383675499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 383675499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 383675499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394923337 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394923337 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394923337 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394923337 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394923337 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394923337 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29513.104917 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29513.104917 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29513.104917 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29513.104917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29513.104917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29513.104917 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 646 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29643.475160 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29643.475160 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29643.475160 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29643.475160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29643.475160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29643.475160 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.692308 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 54.307692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2889 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2889 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2889 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2889 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2889 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2889 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10045 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10045 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10045 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10045 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10045 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10045 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 280085749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 280085749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 280085749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 280085749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 280085749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 280085749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2918 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2918 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2918 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2918 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2918 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2918 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10025 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10025 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10025 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10025 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10025 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10025 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281680749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281680749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281680749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281680749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281680749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281680749 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27883.100946 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27883.100946 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27883.100946 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27883.100946 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27883.100946 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27883.100946 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28097.830324 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28097.830324 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28097.830324 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28097.830324 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28097.830324 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28097.830324 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 443335 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32690.569488 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1090072 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 476070 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.289731 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 443340 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32689.012035 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1090033 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 476076 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.289620 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1328.456107 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.162790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31326.950592 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.040541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001073 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.956023 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997637 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7293 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1053744 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1061037 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 95986 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 95986 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4789 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4789 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997589 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7273 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1053738 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1061011 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 95971 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 95971 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4787 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4787 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7273 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1058525 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065798 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7273 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1058525 # 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Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 399882250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.613876 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999662 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 458073360 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 458073360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733012 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733012 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 25 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 25 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 667806372 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 667806372 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 44999711104 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121327034104 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121327034104 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121327034104 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121327034104 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 459999146 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 459999146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 1527796 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.588575 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 667945835 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1531892 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 436.026714 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 408904250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.588575 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999655 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999655 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 458212871 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 458212871 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209732941 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209732941 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 23 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 667945812 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 667945812 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 667945812 # number of overall hits +system.cpu.dcache.overall_hits::total 667945812 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925756 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925756 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1061955 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1061955 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2987711 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2987711 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2987711 # number of overall misses +system.cpu.dcache.overall_misses::total 2987711 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77391156750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77391156750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 46191877602 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 46191877602 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 78000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 123583034352 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 123583034352 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 123583034352 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 123583034352 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 460138627 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460138627 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 25 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 25 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 670794042 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 670794042 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 670794042 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 670794042 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004186 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004186 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 670933523 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 670933523 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 670933523 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 670933523 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004185 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004185 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005038 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005038 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004454 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004454 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004454 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004454 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39634.374224 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39634.374224 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42377.238101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42377.238101 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40609.248714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40609.248714 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18768 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.041667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.041667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004453 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004453 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004453 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004453 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.415618 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.415618 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.019744 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.019744 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41363.784634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41363.784634 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17901 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 132 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 338 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.086455 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.961538 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 132 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95986 # number of writebacks -system.cpu.dcache.writebacks::total 95986 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465536 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465536 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990239 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990239 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455775 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455775 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455775 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455775 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460250 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460250 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71645 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71645 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531895 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531895 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531895 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531895 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41766827000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41766827000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5159100250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5159100250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46925927250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46925927250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46925927250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46925927250 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks +system.cpu.dcache.writebacks::total 95971 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465505 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465505 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990315 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990315 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455820 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455820 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455820 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455820 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460251 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460251 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71640 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71640 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531891 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531891 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531891 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531891 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41321289000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41321289000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5347166250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5347166250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 76000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 76000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46668455250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46668455250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46668455250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46668455250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003174 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003174 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28602.518062 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28602.518062 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72009.215577 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72009.215577 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28297.387915 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28297.387915 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74639.394891 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74639.394891 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 76000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 76000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30464.605674 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30464.605674 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30464.605674 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30464.605674 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index d3db51b2e..2fb0bf01c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,105 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.640648 # Number of seconds simulated -sim_ticks 640648369500 # Number of ticks simulated -final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.633885 # Number of seconds simulated +sim_ticks 633884897500 # Number of ticks simulated +final_tick 633884897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92518 # Simulator instruction rate (inst/s) -host_op_rate 125998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42814979 # Simulator tick rate (ticks/s) -host_mem_usage 256100 # Number of bytes of host memory used -host_seconds 14963.18 # Real time elapsed on the host +host_inst_rate 87779 # Simulator instruction rate (inst/s) +host_op_rate 119542 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40192628 # Simulator tick rate (ticks/s) +host_mem_usage 283676 # Number of bytes of host memory used +host_seconds 15771.17 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30243840 # Number of bytes read from this memory -system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155648 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30242944 # Number of bytes read from this memory +system.physmem.bytes_read::total 30398080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472560 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472546 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474970 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 242954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47208174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47451128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 242954 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 242954 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6603111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6603111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6603111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474992 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 66098 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 474992 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 66098 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 30399488 # Total number of bytes read from memory -system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29814 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29838 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29538 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29628 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29804 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4148 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4225 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4174 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 640648293500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 474992 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66098 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407729 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 244738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47710466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47955205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 244738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 244738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6673565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6673565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6673565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 244738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47710466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54628770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474970 # Number of read requests accepted +system.physmem.writeReqs 66098 # Number of write requests accepted +system.physmem.readBursts 474970 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30392000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue +system.physmem.bytesWritten 4230080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30398080 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4324 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 29875 # Per bank write bursts +system.physmem.perBankRdBursts::1 29673 # Per bank write bursts +system.physmem.perBankRdBursts::2 29745 # Per bank write bursts +system.physmem.perBankRdBursts::3 29707 # Per bank write bursts +system.physmem.perBankRdBursts::4 29817 # Per bank write bursts +system.physmem.perBankRdBursts::5 29835 # Per bank write bursts +system.physmem.perBankRdBursts::6 29655 # Per bank write bursts +system.physmem.perBankRdBursts::7 29450 # Per bank write bursts +system.physmem.perBankRdBursts::8 29485 # Per bank write bursts +system.physmem.perBankRdBursts::9 29492 # Per bank write bursts +system.physmem.perBankRdBursts::10 29547 # Per bank write bursts +system.physmem.perBankRdBursts::11 29655 # Per bank write bursts +system.physmem.perBankRdBursts::12 29700 # Per bank write bursts +system.physmem.perBankRdBursts::13 29805 # Per bank write bursts +system.physmem.perBankRdBursts::14 29629 # Per bank write bursts +system.physmem.perBankRdBursts::15 29805 # Per bank write bursts +system.physmem.perBankWrBursts::0 4174 # Per bank write bursts +system.physmem.perBankWrBursts::1 4102 # Per bank write bursts +system.physmem.perBankWrBursts::2 4138 # Per bank write bursts +system.physmem.perBankWrBursts::3 4148 # Per bank write bursts +system.physmem.perBankWrBursts::4 4226 # Per bank write bursts +system.physmem.perBankWrBursts::5 4224 # Per bank write bursts +system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4094 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4140 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 633884833500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 474970 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66098 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -125,29 +127,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -157,113 +159,161 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 173268 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 199.789644 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.514067 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 508.333416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 59669 34.44% 34.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 42666 24.62% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 39942 23.05% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 25325 14.62% 96.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 291 0.17% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 110 0.06% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 103 0.06% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 89 0.05% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 94 0.05% 97.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 79 0.05% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 78 0.05% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 80 0.05% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 70 0.04% 97.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 76 0.04% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 80 0.05% 97.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 77 0.04% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 81 0.05% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 72 0.04% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 72 0.04% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3310 1.91% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 4 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 173268 # Bytes accessed per row activation -system.physmem.totQLat 1888421000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14966831000 # Sum of mem lat for all requests -system.physmem.totBusLat 2374200000 # Total cycles spent in databus access -system.physmem.totBankLat 10704210000 # Total cycles spent in bank access -system.physmem.avgQLat 3976.96 # Average queueing delay per request -system.physmem.avgBankLat 22542.77 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31519.74 # Average memory access latency -system.physmem.avgRdBW 47.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.60 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.60 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.42 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 17.45 # Average write queue length over time -system.physmem.readRowHits 318007 # Number of row buffer hits during reads -system.physmem.writeRowHits 49644 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes -system.physmem.avgGap 1183995.81 # Average gap between requests -system.membus.throughput 54054139 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408917 # Transaction distribution -system.membus.trans_dist::ReadResp 408916 # Transaction distribution +system.physmem.bytesPerActivate::samples 190556 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 181.682403 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 122.345891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 377.529861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 76623 40.21% 40.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 50018 26.25% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 37571 19.72% 86.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 19599 10.29% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 202 0.11% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 233 0.12% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 93 0.05% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 219 0.11% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 79 0.04% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 231 0.12% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 59 0.03% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 225 0.12% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 74 0.04% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 178 0.09% 97.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 61 0.03% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 176 0.09% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 47 0.02% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 188 0.10% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 71 0.04% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 186 0.10% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 71 0.04% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 3176 1.67% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 17 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 14 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 12 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 11 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 7 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 10 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 16 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 14 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 19 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 23 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 18 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 9 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 11 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 13 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 10 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 12 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 24 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 8 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 18 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 22 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 22 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 14 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 12 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 11 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 10 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 8 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 14 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 4 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 19 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 19 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 21 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 17 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 18 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 12 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 19 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 10 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 12 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 10 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 12 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 16 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 16 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 16 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 31 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 17 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 10 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 9 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 11 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 6 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 17 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 12 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 16 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 14 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 19 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 17 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 16 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 3 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 13 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 6 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 7 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 7 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 10 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 14 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 20 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 16 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568 15 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 12 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 34 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 69 0.04% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 58 0.03% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080 8 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 59 0.03% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 190556 # Bytes accessed per row activation +system.physmem.totQLat 3723849000 # Total ticks spent queuing +system.physmem.totMemAccLat 15162897750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2374375000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9064673750 # Total ticks spent accessing banks +system.physmem.avgQLat 7841.75 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 19088.55 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31930.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 47.95 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 47.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.67 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.43 # Data bus utilization in percentage +system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.41 # Average write queue length when enqueuing +system.physmem.readRowHits 301072 # Number of row buffer hits during reads +system.physmem.writeRowHits 49342 # Number of row buffer hits during writes +system.physmem.readRowHitRate 63.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.65 # Row buffer hit rate for writes +system.physmem.avgGap 1171543.75 # Average gap between requests +system.physmem.pageHitRate 64.77 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 24.91 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54628770 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408895 # Transaction distribution +system.membus.trans_dist::ReadResp 408895 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4361 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4324 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4324 # Transaction distribution system.membus.trans_dist::ReadExReq 66075 # Transaction distribution system.membus.trans_dist::ReadExResp 66075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024803 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1024803 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34629696 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34629696 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024686 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1024686 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34628352 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34628352 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34628352 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1216897000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4480877139 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4442648676 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 451070712 # Number of BP lookups -system.cpu.branchPred.condPredicted 361199071 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 31575662 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 266989928 # Number of BTB lookups -system.cpu.branchPred.BTBHits 238695746 # Number of BTB hits +system.cpu.branchPred.lookups 445875274 # Number of BP lookups +system.cpu.branchPred.condPredicted 355714891 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 31013117 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262160312 # Number of BTB lookups +system.cpu.branchPred.BTBHits 234316871 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.402528 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 53258278 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806364 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.379231 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 52540791 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2805997 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -307,100 +357,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1281296740 # number of cpu cycles simulated +system.cpu.numCycles 1267769796 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 365834433 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2312845521 # Number of instructions fetch has processed -system.cpu.fetch.Branches 451070712 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 291954024 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 613483563 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162414515 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 128244265 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11411 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 359604051 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2297734506 # Number of instructions fetch has processed +system.cpu.fetch.Branches 445875274 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 286857662 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 606667357 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 159378109 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 130943287 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11360 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 346004157 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12181247 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1238361342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.567207 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.166964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 340050056 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11891209 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1225539818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.573745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.170795 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 624922537 50.46% 50.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43984122 3.55% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 100783073 8.14% 62.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 58015364 4.68% 66.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 73986941 5.97% 72.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44117238 3.56% 76.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31886448 2.57% 78.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33644071 2.72% 81.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 227021548 18.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 618917347 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42971146 3.51% 54.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 97897325 7.99% 62.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 56071890 4.58% 66.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 75061628 6.12% 72.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45063261 3.68% 76.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31435951 2.57% 78.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31903606 2.60% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226217664 18.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1238361342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.352042 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.805082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 416001710 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101876756 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 574960463 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14748325 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 130774088 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46845433 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13115 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3066767432 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27354 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 130774088 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 450873553 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37362667 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 459915 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 552824643 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 66066476 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2984722482 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 106 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4345913 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 52259250 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12321480350 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90240197 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1225539818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.351701 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.812423 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 410024939 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 104223819 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 567090713 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15899066 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 128301281 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 47087821 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11947 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3044373258 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 26488 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 128301281 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 445072814 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37752394 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 469546 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 545867989 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 68075794 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2962731385 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4402501 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 53439360 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 9 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2946792223 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14100168268 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12232464769 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 87261724 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18729 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 172024073 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 975055963 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 496398991 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36275443 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40590257 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2826416078 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28152 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2457324643 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 15915709 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 928556403 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2380098621 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6768 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1238361342 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.984336 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.868331 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 953652133 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20387 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17854 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 175792199 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 972804227 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 491413736 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36509550 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 42116928 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2808310459 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27673 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2443543142 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13552705 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 910455744 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2345608138 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6289 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1225539818 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.993850 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.871016 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 394006079 31.82% 31.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183256590 14.80% 46.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 205523874 16.60% 63.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 174394872 14.08% 77.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 137878376 11.13% 88.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 90899666 7.34% 95.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 36275985 2.93% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12839255 1.04% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3286645 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 386142313 31.51% 31.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183212489 14.95% 46.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204921233 16.72% 63.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 171581285 14.00% 77.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 134431508 10.97% 88.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92278264 7.53% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37194117 3.03% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12766594 1.04% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3012015 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1238361342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1225539818 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 691696 0.78% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24382 0.03% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 692354 0.79% 0.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24381 0.03% 0.81% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available @@ -428,118 +478,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55024342 62.24% 63.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32666949 36.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55108221 62.64% 63.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 32145057 36.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1118619814 45.52% 45.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11223087 0.46% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 46.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5501669 0.22% 46.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23389012 0.95% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 843037947 34.31% 81.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 447301347 18.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1110380096 45.44% 45.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223911 0.46% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.28% 46.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502670 0.23% 46.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23408416 0.96% 47.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 840781219 34.41% 81.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 443995061 18.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2457324643 # Type of FU issued -system.cpu.iq.rate 1.917842 # Inst issue rate -system.cpu.iq.fu_busy_cnt 88407369 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035977 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6133604202 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3666175191 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2269813505 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 123729504 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88892403 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56421926 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2481804628 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63927384 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 85672552 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2443543142 # Type of FU issued +system.cpu.iq.rate 1.927434 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87970013 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036001 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6090822143 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3633185531 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2257760958 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 123326677 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 85675338 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56498576 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2467787139 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63726016 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 85165626 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 343668782 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 27729 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429255 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 219403694 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 341417046 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 38150 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1428012 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 214418439 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 304 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 322 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 130774088 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15649984 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1558990 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2826456693 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 641968 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 975055963 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 496398991 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18166 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1553675 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429255 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 33789507 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2118647 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 35908154 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2378923796 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 796860173 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 78400847 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 128301281 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16032166 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1560767 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2808350603 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 961806 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 972804227 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 491413736 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 17687 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1557116 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2524 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1428012 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32911757 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1861954 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 34773711 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2367002070 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 794874980 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 76541072 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12463 # number of nop insts executed -system.cpu.iew.exec_refs 1223764024 # number of memory reference insts executed -system.cpu.iew.exec_branches 324680497 # Number of branches executed -system.cpu.iew.exec_stores 426903851 # Number of stores executed -system.cpu.iew.exec_rate 1.856653 # Inst execution rate -system.cpu.iew.wb_sent 2351973532 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2326235431 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1354756756 # num instructions producing a value -system.cpu.iew.wb_consumers 2530303455 # num instructions consuming a value +system.cpu.iew.exec_nop 12471 # number of nop insts executed +system.cpu.iew.exec_refs 1219940656 # number of memory reference insts executed +system.cpu.iew.exec_branches 321608336 # Number of branches executed +system.cpu.iew.exec_stores 425065676 # Number of stores executed +system.cpu.iew.exec_rate 1.867060 # Inst execution rate +system.cpu.iew.wb_sent 2340031230 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2314259534 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1351078205 # num instructions producing a value +system.cpu.iew.wb_consumers 2527156960 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.815532 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535413 # average fanout of values written-back +system.cpu.iew.wb_rate 1.825457 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534624 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 941120455 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 923014366 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 31562826 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1107587254 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.702201 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.378361 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 31001379 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1097238537 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.718256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.389874 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 463154673 41.82% 41.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 291887882 26.35% 68.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 96478924 8.71% 76.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70059146 6.33% 83.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46846853 4.23% 87.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22330225 2.02% 89.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15798039 1.43% 90.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11765677 1.06% 91.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 89265835 8.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 455331878 41.50% 41.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 289999556 26.43% 67.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95581485 8.71% 76.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70096070 6.39% 83.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46571745 4.24% 87.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22195585 2.02% 89.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15856765 1.45% 90.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11363497 1.04% 91.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90241956 8.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1107587254 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1097238537 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -550,222 +600,222 @@ system.cpu.commit.branches 298259106 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 89265835 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90241956 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3844759887 # The number of ROB reads -system.cpu.rob.rob_writes 5783698867 # The number of ROB writes -system.cpu.timesIdled 353367 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42935398 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3815328960 # The number of ROB reads +system.cpu.rob.rob_writes 5745013824 # The number of ROB writes +system.cpu.timesIdled 352945 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42229978 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.925545 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.925545 # CPI: Total CPI of All Threads -system.cpu.ipc 1.080445 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.080445 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11851555490 # number of integer regfile reads -system.cpu.int_regfile_writes 2239006966 # number of integer regfile writes -system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads -system.cpu.fp_regfile_writes 49533000 # number of floating regfile writes -system.cpu.misc_regfile_reads 1371543913 # number of misc regfile reads +system.cpu.cpi 0.915773 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.915773 # CPI: Total CPI of All Threads +system.cpu.ipc 1.091973 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.091973 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11799440532 # number of integer regfile reads +system.cpu.int_regfile_writes 2227507770 # number of integer regfile writes +system.cpu.fp_regfile_reads 68853045 # number of floating regfile reads +system.cpu.fp_regfile_writes 49554235 # number of floating regfile writes +system.cpu.misc_regfile_reads 1367872939 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52387 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3231222 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1536768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104525120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106061888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 167773046 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1492868 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1492867 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96315 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4328 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4328 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72518 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52441 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3231415 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1539648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104532224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 106071872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 106071872 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 276928 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 929329999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 42995247 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2368559798 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 22329 # number of replacements -system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 22373 # number of replacements +system.cpu.icache.tags.tagsinuse 1644.727747 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 340012575 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24056 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14134.210800 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 345973619 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 345973619 # number of overall hits -system.cpu.icache.overall_hits::total 345973619 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30537 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30537 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30537 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30537 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30537 # number of overall misses -system.cpu.icache.overall_misses::total 30537 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 527751245 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 527751245 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 527751245 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 527751245 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 527751245 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 527751245 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 346004156 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 346004156 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 346004156 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 346004156 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 346004156 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 346004156 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17282.354030 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17282.354030 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17282.354030 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17282.354030 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1734 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1644.727747 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.803090 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.803090 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 340019150 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 340019150 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 340019150 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 340019150 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 340019150 # number of overall hits +system.cpu.icache.overall_hits::total 340019150 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 30904 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 30904 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 30904 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 30904 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 30904 # number of overall misses +system.cpu.icache.overall_misses::total 30904 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 530577244 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 530577244 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 530577244 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 530577244 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 530577244 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 530577244 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 340050054 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 340050054 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 340050054 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 340050054 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 340050054 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 340050054 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000091 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000091 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000091 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17168.562128 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17168.562128 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17168.562128 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17168.562128 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1738 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 31 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54.187500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.064516 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2162 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2162 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2162 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2162 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2162 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2162 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28375 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28375 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28375 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28375 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28375 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28375 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 422292499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 422292499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 422292499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 422292499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 422292499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 422292499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14882.555031 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14882.555031 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2520 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2520 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2520 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2520 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2520 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2520 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28384 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28384 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28384 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28384 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28384 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28384 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 424232750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 424232750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 424232750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 424232750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 424232750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 424232750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000083 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000083 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000083 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14946.193278 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14946.193278 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 442208 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 442189 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32678.484609 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1109448 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 474936 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.335995 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.039423 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001529 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.956378 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274695 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999076 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999076 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911153 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911153 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307447 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304261 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307447 # 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Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999606 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999606 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 695310256 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 695310256 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276092959 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276092959 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 972883701 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 972883701 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 972883701 # 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number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 136025973338 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 136025973338 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 136025973338 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 136025973338 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 698744373 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 698744373 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2796855 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2796855 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2796855 # number of overall misses +system.cpu.dcache.overall_misses::total 2796855 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80332980069 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80332980069 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58617620770 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58617620770 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 225000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 138950600839 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 138950600839 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 138950600839 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 138950600839 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 697264392 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 697264392 # 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number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 975680051 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 975680051 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002796 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002796 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003042 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003042 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 974200070 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 974200070 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 974200070 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 974200070 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40521.101930 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40521.101930 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67483.493061 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67483.493061 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 68250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 68250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48644.115843 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48644.115843 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2745 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 62 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.274194 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.584270 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41109.206355 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41109.206355 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69557.730121 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69557.730121 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49681.017013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49681.017013 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2430 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 892 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 86 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.392857 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.372093 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96304 # number of writebacks -system.cpu.dcache.writebacks::total 96304 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489504 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 489504 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765580 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765580 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96315 # number of writebacks +system.cpu.dcache.writebacks::total 96315 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489650 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489650 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765875 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765875 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1255084 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1255084 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1255084 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1255084 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464384 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464384 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76882 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76882 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541266 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541266 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541266 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541266 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42754567776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42754567776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4832230139 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4832230139 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47586797915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47586797915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47586797915 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47586797915 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002096 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002096 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001580 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001580 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29196.281697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29196.281697 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62852.555071 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62852.555071 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1255525 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1255525 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1255525 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1255525 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464486 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464486 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76844 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76844 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541330 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541330 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541330 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541330 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42708562776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42708562776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4994223926 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4994223926 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47702786702 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47702786702 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47702786702 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47702786702 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002100 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002100 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29162.834452 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29162.834452 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64991.722529 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64991.722529 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index c7e2525ee..4f4f69eed 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043769 # Number of seconds simulated -sim_ticks 43769191000 # Number of ticks simulated -final_tick 43769191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043690 # Number of seconds simulated +sim_ticks 43690025000 # Number of ticks simulated +final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69144 # Simulator instruction rate (inst/s) -host_op_rate 69144 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34257993 # Simulator tick rate (ticks/s) -host_mem_usage 232832 # Number of bytes of host memory used -host_seconds 1277.63 # Real time elapsed on the host +host_inst_rate 111109 # Simulator instruction rate (inst/s) +host_op_rate 111109 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54950396 # Simulator tick rate (ticks/s) +host_mem_usage 264576 # Number of bytes of host memory used +host_seconds 795.08 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory @@ -23,81 +23,83 @@ system.physmem.num_reads::cpu.data 158412 # Nu system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10386118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 231632520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242018638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10386118 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10386118 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 166688208 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 166688208 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 166688208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10386118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 231632520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 408706846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165515 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 113997 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 165515 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 113997 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 10592960 # Total number of bytes read from memory -system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10592960 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10015 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10350 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10510 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10480 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10581 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10593 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7259 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6998 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7175 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6769 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6938 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7284 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7283 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43769170000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165515 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 113997 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 72862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 71499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 10404938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 232052236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 242457174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10404938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10404938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166990245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166990245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166990245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10404938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 232052236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 409447420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165515 # Number of read requests accepted +system.physmem.writeReqs 113997 # Number of write requests accepted +system.physmem.readBursts 165515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 113997 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10592832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10592960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7295808 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10379 # Per bank write bursts +system.physmem.perBankRdBursts::1 10437 # Per bank write bursts +system.physmem.perBankRdBursts::2 10256 # Per bank write bursts +system.physmem.perBankRdBursts::3 10015 # Per bank write bursts +system.physmem.perBankRdBursts::4 10350 # Per bank write bursts +system.physmem.perBankRdBursts::5 10362 # Per bank write bursts +system.physmem.perBankRdBursts::6 9796 # Per bank write bursts +system.physmem.perBankRdBursts::7 10273 # Per bank write bursts +system.physmem.perBankRdBursts::8 10509 # Per bank write bursts +system.physmem.perBankRdBursts::9 10590 # Per bank write bursts +system.physmem.perBankRdBursts::10 10479 # Per bank write bursts +system.physmem.perBankRdBursts::11 10188 # Per bank write bursts +system.physmem.perBankRdBursts::12 10237 # Per bank write bursts +system.physmem.perBankRdBursts::13 10581 # Per bank write bursts +system.physmem.perBankRdBursts::14 10468 # Per bank write bursts +system.physmem.perBankRdBursts::15 10593 # Per bank write bursts +system.physmem.perBankWrBursts::0 7081 # Per bank write bursts +system.physmem.perBankWrBursts::1 7259 # Per bank write bursts +system.physmem.perBankWrBursts::2 7255 # Per bank write bursts +system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::4 7125 # Per bank write bursts +system.physmem.perBankWrBursts::5 7173 # Per bank write bursts +system.physmem.perBankWrBursts::6 6769 # Per bank write bursts +system.physmem.perBankWrBursts::7 7091 # Per bank write bursts +system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::9 6938 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6989 # Per bank write bursts +system.physmem.perBankWrBursts::12 6964 # Per bank write bursts +system.physmem.perBankWrBursts::13 7284 # Per bank write bursts +system.physmem.perBankWrBursts::14 7282 # Per bank write bursts +system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 43690004000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 165515 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 113997 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 73680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -125,188 +127,195 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 366.351698 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.645495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 749.158032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 19754 40.46% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7696 15.76% 56.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4247 8.70% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2897 5.93% 70.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2142 4.39% 75.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1740 3.56% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1303 2.67% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1111 2.28% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 826 1.69% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 678 1.39% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 468 0.96% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 525 1.08% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 411 0.84% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 341 0.70% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 262 0.54% 90.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 362 0.74% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 210 0.43% 92.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 226 0.46% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 155 0.32% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 229 0.47% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 390 0.80% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 303 0.62% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 582 1.19% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 207 0.42% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 152 0.31% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 46 0.09% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 145 0.30% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 73 0.15% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 52 0.11% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 28 0.06% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 72 0.15% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 42 0.09% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 42 0.09% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 23 0.05% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 48 0.10% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 25 0.05% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 11 0.02% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 23 0.05% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 7 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 13 0.03% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 21 0.04% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 13 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 14 0.03% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 8 0.02% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 9 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 5 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 8 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 5 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 3 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 7 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 6 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 3 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 6 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 12 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 3 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 6 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 164 0.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48826 # Bytes accessed per row activation -system.physmem.totQLat 6287289000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8773086500 # Sum of mem lat for all requests -system.physmem.totBusLat 827575000 # Total cycles spent in databus access -system.physmem.totBankLat 1658222500 # Total cycles spent in bank access -system.physmem.avgQLat 37986.22 # Average queueing delay per request -system.physmem.avgBankLat 10018.56 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53004.78 # Average memory access latency -system.physmem.avgRdBW 242.02 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 166.69 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 242.02 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 166.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.19 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 10.49 # Average write queue length over time -system.physmem.readRowHits 153779 # Number of row buffer hits during reads -system.physmem.writeRowHits 76898 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.91 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.46 # Row buffer hit rate for writes -system.physmem.avgGap 156591.38 # Average gap between requests -system.membus.throughput 408706846 # Throughput (bytes/s) +system.physmem.bytesPerActivate::samples 51391 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.059076 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.605304 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 670.587406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 21918 42.65% 42.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7689 14.96% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4202 8.18% 65.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3191 6.21% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2222 4.32% 76.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1690 3.29% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1284 2.50% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1159 2.26% 84.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 851 1.66% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 652 1.27% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 530 1.03% 88.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 483 0.94% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 404 0.79% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 335 0.65% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 260 0.51% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 388 0.75% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 222 0.43% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 237 0.46% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 182 0.35% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 255 0.50% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 215 0.42% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 327 0.64% 94.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 148 0.29% 95.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 683 1.33% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 243 0.47% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 177 0.34% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 59 0.11% 97.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 192 0.37% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 83 0.16% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 80 0.16% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 48 0.09% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 87 0.17% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 58 0.11% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 48 0.09% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 40 0.08% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 14 0.03% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 34 0.07% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 26 0.05% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 13 0.03% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 18 0.04% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 12 0.02% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 26 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 7 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 17 0.03% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 6 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 10 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 11 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 13 0.03% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 10 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 6 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 3 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 20 0.04% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 11 0.02% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 15 0.03% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 13 0.03% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 8 0.02% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 4 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 6 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 24 0.05% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 73 0.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 51391 # Bytes accessed per row activation +system.physmem.totQLat 6031819750 # Total ticks spent queuing +system.physmem.totMemAccLat 8481513500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 827565000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1622128750 # Total ticks spent accessing banks +system.physmem.avgQLat 36443.18 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9800.61 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 51243.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 242.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 166.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 242.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 166.99 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.20 # Data bus utilization in percentage +system.physmem.busUtilRead 1.89 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing +system.physmem.readRowHits 151507 # Number of row buffer hits during reads +system.physmem.writeRowHits 76598 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.19 # Row buffer hit rate for writes +system.physmem.avgGap 156308.15 # Average gap between requests +system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 10.59 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 409447420 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 34625 # Transaction distribution system.membus.trans_dist::ReadResp 34625 # Transaction distribution system.membus.trans_dist::Writeback 113997 # Transaction distribution @@ -318,39 +327,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1218896000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1218630500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1522799000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1521664000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) -system.cpu.branchPred.lookups 18742730 # Number of BP lookups -system.cpu.branchPred.condPredicted 12318368 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18742723 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15507340 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4664027 # Number of BTB hits +system.cpu.branchPred.BTBLookups 15507309 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4664026 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.076254 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 30.076308 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277790 # DTB read hits +system.cpu.dtb.read_hits 20277713 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367938 # DTB read accesses -system.cpu.dtb.write_hits 14728966 # DTB write hits +system.cpu.dtb.read_accesses 20367861 # DTB read accesses +system.cpu.dtb.write_hits 14728970 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736218 # DTB write accesses -system.cpu.dtb.data_hits 35006756 # DTB hits +system.cpu.dtb.write_accesses 14736222 # DTB write accesses +system.cpu.dtb.data_hits 35006683 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35104156 # DTB accesses -system.cpu.itb.fetch_hits 12367759 # ITB hits +system.cpu.dtb.data_accesses 35104083 # DTB accesses +system.cpu.itb.fetch_hits 12367758 # ITB hits system.cpu.itb.fetch_misses 11021 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378780 # ITB accesses +system.cpu.itb.fetch_accesses 12378779 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -364,34 +373,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87538383 # number of cpu cycles simulated +system.cpu.numCycles 87380051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8074238 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10668492 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74161920 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8074237 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10668486 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74161830 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126481170 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 126481080 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14174454 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 14174544 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 35060070 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44777931 # Number of Instructions Executed. +system.cpu.execution_unit.executions 44777932 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77194023 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77196543 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 231301 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17962893 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69575490 # Number of cycles cpu stages are processed. -system.cpu.activity 79.479981 # Percentage of cycles cpu is active +system.cpu.timesIdled 232942 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17804423 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69575628 # Number of cycles cpu stages are processed. +system.cpu.activity 79.624156 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -403,157 +412,157 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.990918 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.989126 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.990918 # CPI: Total CPI of All Threads -system.cpu.ipc 1.009165 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.989126 # CPI: Total CPI of All Threads +system.cpu.ipc 1.010994 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.009165 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34882792 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52655591 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.151432 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45083196 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42455187 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.498939 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44507774 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43030609 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.156276 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65417325 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22121058 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.270124 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41496378 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46042005 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.596362 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.010994 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34724442 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52655609 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.260447 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44924893 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42455158 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.586786 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44349560 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43030491 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.245212 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65259184 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120867 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.315695 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41338146 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46041905 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.691552 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 84371 # number of replacements -system.cpu.icache.tags.tagsinuse 1906.602529 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 12250515 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1906.431852 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12250505 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 141.760475 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 141.760360 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1906.602529 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.930958 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.930958 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12250515 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250515 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250515 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250515 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250515 # number of overall hits -system.cpu.icache.overall_hits::total 12250515 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 117235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 117235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 117235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 117235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 117235 # number of overall misses -system.cpu.icache.overall_misses::total 117235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2053420481 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2053420481 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2053420481 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2053420481 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2053420481 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2053420481 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12367750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12367750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12367750 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12367750 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12367750 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12367750 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009479 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009479 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009479 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009479 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009479 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009479 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17515.421854 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17515.421854 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17515.421854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17515.421854 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1906.431852 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.930875 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.930875 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12250505 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250505 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250505 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250505 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250505 # number of overall hits +system.cpu.icache.overall_hits::total 12250505 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117242 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 117242 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 117242 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 117242 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 117242 # number of overall misses +system.cpu.icache.overall_misses::total 117242 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2020332731 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2020332731 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2020332731 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2020332731 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2020332731 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2020332731 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12367747 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12367747 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12367747 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12367747 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12367747 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12367747 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009480 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009480 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009480 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17232.158535 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17232.158535 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17232.158535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17232.158535 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 376 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.812500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.117647 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30818 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30818 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30818 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30818 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30818 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30818 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30825 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30825 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1462353516 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1462353516 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1462353516 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1462353516 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1432321765 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1432321765 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1432321765 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1432321765 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1432321765 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1432321765 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16922.058345 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16922.058345 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16574.537012 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16574.537012 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 671326642 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution +system.cpu.toL2Bus.throughput 672540151 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 146994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 146994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168351 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577043 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 749877 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29383296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29383296 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 397908000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 131178984 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 130875735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 326782984 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 325637219 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.l2cache.tags.replacements 131591 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30902.226523 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 30890.802594 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 151432 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.925335 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27124.475533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1770.311223 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.827773 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061262 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.054026 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.943061 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27098.006137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.747165 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1785.049292 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.826966 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061272 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.054475 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.942712 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # 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number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 125248 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 79314 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 45935 # number of overall hits -system.cpu.l2cache.overall_hits::total 125249 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 45934 # number of overall hits +system.cpu.l2cache.overall_hits::total 125248 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 7103 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 27522 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 34625 # number of ReadReq misses @@ -565,52 +574,52 @@ system.cpu.l2cache.demand_misses::total 165515 # nu system.cpu.l2cache.overall_misses::cpu.inst 7103 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses system.cpu.l2cache.overall_misses::total 165515 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 580141750 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 60578 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 146995 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168352 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168352 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 146994 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168351 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168351 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143769 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143769 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 86417 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 290764 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204346 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290763 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 86417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 290764 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204346 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 290763 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082194 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454331 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235554 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775215 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.569244 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81675.594819 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73190.493060 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74931.133574 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105034.146994 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105034.146994 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98736.730810 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98736.730810 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775215 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.569244 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77449.774743 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74243.223603 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74901.018051 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.814042 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.814042 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 96948.485032 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 96948.485032 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -632,73 +641,73 @@ system.cpu.l2cache.demand_mshr_misses::total 165515 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 490395250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1665695250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156090500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12145170500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12145170500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 490395250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13810865750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14301261000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 490395250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13810865750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14301261000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 460945750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1695556500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156502250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11851363750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11851363750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 460945750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13546920250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14007866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 460945750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13546920250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14007866000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454331 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235554 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569244 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69040.581444 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60522.318509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62269.761733 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92789.139736 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92789.139736 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569244 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64894.516402 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61607.314149 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62281.653430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90544.455268 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90544.455268 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200251 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.642006 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33754840 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.183927 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995274 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995274 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574569 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574569 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33754840 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754840 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754840 # number of overall hits -system.cpu.dcache.overall_hits::total 33754840 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038808 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038808 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135175 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135175 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135175 # number of overall misses -system.cpu.dcache.overall_misses::total 1135175 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5010614984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5010614984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 87491278500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 87491278500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92501893484 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92501893484 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92501893484 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92501893484 # number of overall miss cycles +system.cpu.dcache.tags.replacements 200250 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.382661 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33754883 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204346 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.184946 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 297515000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.382661 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995211 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995211 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180292 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180292 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574591 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574591 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754883 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754883 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754883 # number of overall hits +system.cpu.dcache.overall_hits::total 33754883 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96346 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96346 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038786 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038786 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135132 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135132 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135132 # number of overall misses +system.cpu.dcache.overall_misses::total 1135132 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666734 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5098666734 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765880 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85921765880 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91020432614 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91020432614 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91020432614 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91020432614 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -707,56 +716,56 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071086 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071086 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51995.133023 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51995.133023 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84222.761569 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84222.761569 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81486.901565 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81486.901565 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5878259 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 106 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116796 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.377950 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.377950 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634839 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634839 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80184.888290 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80184.888290 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5745787 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.329284 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 106 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.220352 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks -system.cpu.dcache.writebacks::total 168352 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35600 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35600 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895228 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895228 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930828 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930828 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930828 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930828 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks +system.cpu.dcache.writebacks::total 168351 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35580 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35580 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895206 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895206 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930786 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930786 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930786 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930786 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2409027516 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2409027516 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14018315000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14018315000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16427342516 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16427342516 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16427342516 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16427342516 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2437943016 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2437943016 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723509265 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723509265 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161452281 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16161452281 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161452281 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16161452281 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -765,14 +774,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39643.680221 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39643.680221 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97634.176069 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97634.176069 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40120.182602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40120.182602 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.925373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.925373 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index f889e2dcc..5daeaeb73 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024977 # Number of seconds simulated -sim_ticks 24977022500 # Number of ticks simulated -final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024874 # Number of seconds simulated +sim_ticks 24873813500 # Number of ticks simulated +final_tick 24873813500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179872 # Simulator instruction rate (inst/s) -host_op_rate 179872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56446381 # Simulator tick rate (ticks/s) -host_mem_usage 238148 # Number of bytes of host memory used -host_seconds 442.49 # Real time elapsed on the host +host_inst_rate 165069 # Simulator instruction rate (inst/s) +host_op_rate 165069 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51586823 # Simulator tick rate (ticks/s) +host_mem_usage 265596 # Number of bytes of host memory used +host_seconds 482.17 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 489600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10153536 # Number of bytes read from this memory -system.physmem.bytes_read::total 10643520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 10643136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 489600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 489600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297088 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7650 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158649 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166305 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19617390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 406515068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 426132458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19617390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19617390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 292149475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 292149475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 292149475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166305 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 114016 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 166305 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 114016 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 10643520 # Total number of bytes read from memory -system.physmem.bytesWritten 7297024 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10060 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10430 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9844 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10548 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10226 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10625 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6967 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24976988500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166305 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 114016 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 72274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.num_reads::total 166299 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114017 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114017 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19683351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 408201822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 427885173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19683351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19683351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 293364264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 293364264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 293364264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19683351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 408201822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 721249438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166299 # Number of read requests accepted +system.physmem.writeReqs 114017 # Number of write requests accepted +system.physmem.readBursts 166299 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114017 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10643008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7296896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10643136 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7297088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10432 # Per bank write bursts +system.physmem.perBankRdBursts::1 10453 # Per bank write bursts +system.physmem.perBankRdBursts::2 10310 # Per bank write bursts +system.physmem.perBankRdBursts::3 10056 # Per bank write bursts +system.physmem.perBankRdBursts::4 10431 # Per bank write bursts +system.physmem.perBankRdBursts::5 10400 # Per bank write bursts +system.physmem.perBankRdBursts::6 9846 # Per bank write bursts +system.physmem.perBankRdBursts::7 10320 # Per bank write bursts +system.physmem.perBankRdBursts::8 10615 # Per bank write bursts +system.physmem.perBankRdBursts::9 10642 # Per bank write bursts +system.physmem.perBankRdBursts::10 10549 # Per bank write bursts +system.physmem.perBankRdBursts::11 10234 # Per bank write bursts +system.physmem.perBankRdBursts::12 10280 # Per bank write bursts +system.physmem.perBankRdBursts::13 10614 # Per bank write bursts +system.physmem.perBankRdBursts::14 10489 # Per bank write bursts +system.physmem.perBankRdBursts::15 10626 # Per bank write bursts +system.physmem.perBankWrBursts::0 7083 # Per bank write bursts +system.physmem.perBankWrBursts::1 7257 # Per bank write bursts +system.physmem.perBankWrBursts::2 7256 # Per bank write bursts +system.physmem.perBankWrBursts::3 6997 # Per bank write bursts +system.physmem.perBankWrBursts::4 7126 # Per bank write bursts +system.physmem.perBankWrBursts::5 7177 # Per bank write bursts +system.physmem.perBankWrBursts::6 6772 # Per bank write bursts +system.physmem.perBankWrBursts::7 7093 # Per bank write bursts +system.physmem.perBankWrBursts::8 7227 # Per bank write bursts +system.physmem.perBankWrBursts::9 6941 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::13 7287 # Per bank write bursts +system.physmem.perBankWrBursts::14 7286 # Per bank write bursts +system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 24873779500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 166299 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 114017 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,230 +127,233 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49952 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.130045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.640646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 741.801736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 20814 41.67% 41.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7820 15.66% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4185 8.38% 65.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3013 6.03% 71.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2148 4.30% 76.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1700 3.40% 79.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1301 2.60% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1098 2.20% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 776 1.55% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 657 1.32% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 496 0.99% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 568 1.14% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 406 0.81% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 302 0.60% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 268 0.54% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 357 0.71% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 241 0.48% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 170 0.34% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 145 0.29% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 323 0.65% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 351 0.70% 94.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 146 0.29% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 301 0.60% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 689 1.38% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 236 0.47% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 76 0.15% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 36 0.07% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 184 0.37% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 89 0.18% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 34 0.07% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 40 0.08% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 93 0.19% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 64 0.13% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 19 0.04% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 44 0.09% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 19 0.04% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 19 0.04% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 36 0.07% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 21 0.04% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 12 0.02% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 20 0.04% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 10 0.02% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 10 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 17 0.03% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 15 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 9 0.02% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 8 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 9 0.02% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 10 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 6 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 5 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 11 0.02% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 7 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 169 0.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49952 # Bytes accessed per row activation -system.physmem.totQLat 6557959000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8953517750 # Sum of mem lat for all requests -system.physmem.totBusLat 831510000 # Total cycles spent in databus access -system.physmem.totBankLat 1564048750 # Total cycles spent in bank access -system.physmem.avgQLat 39434.04 # Average queueing delay per request -system.physmem.avgBankLat 9404.87 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53838.91 # Average memory access latency -system.physmem.avgRdBW 426.13 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 292.15 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 426.13 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 292.15 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.61 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.36 # Average read queue length over time -system.physmem.avgWrQLen 9.86 # Average write queue length over time -system.physmem.readRowHits 154145 # Number of row buffer hits during reads -system.physmem.writeRowHits 76216 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.85 # Row buffer hit rate for writes -system.physmem.avgGap 89101.38 # Average gap between requests -system.membus.throughput 718281933 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35508 # Transaction distribution -system.membus.trans_dist::ReadResp 35508 # Transaction distribution -system.membus.trans_dist::Writeback 114016 # Transaction distribution -system.membus.trans_dist::ReadExReq 130797 # Transaction distribution -system.membus.trans_dist::ReadExResp 130797 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446626 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446626 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17940544 # Total data (bytes) +system.physmem.bytesPerActivate::samples 52112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.243169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.634788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 670.449971 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 22509 43.19% 43.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7813 14.99% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4251 8.16% 66.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3108 5.96% 72.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2227 4.27% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1678 3.22% 79.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1376 2.64% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1167 2.24% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 816 1.57% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 658 1.26% 87.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 508 0.97% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 506 0.97% 89.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 390 0.75% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 297 0.57% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 306 0.59% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 440 0.84% 92.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 200 0.38% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 185 0.36% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 164 0.31% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 351 0.67% 93.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 222 0.43% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 266 0.51% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 128 0.25% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 805 1.54% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 220 0.42% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 67 0.13% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 43 0.08% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 225 0.43% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 103 0.20% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 52 0.10% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 34 0.07% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 84 0.16% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 57 0.11% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 36 0.07% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 55 0.11% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 39 0.07% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 21 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 12 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 17 0.03% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 18 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 24 0.05% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 13 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 9 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 11 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 6 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 7 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 11 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.02% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 9 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 13 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 6 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 3 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 10 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 5 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 6 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 8 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 7 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 8 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 15 0.03% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 82 0.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52112 # Bytes accessed per row activation +system.physmem.totQLat 6321612000 # Total ticks spent queuing +system.physmem.totMemAccLat 8667027000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831485000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1513930000 # Total ticks spent accessing banks +system.physmem.avgQLat 38013.99 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9103.77 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 52117.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 427.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 293.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 427.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 293.36 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 5.63 # Data bus utilization in percentage +system.physmem.busUtilRead 3.34 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.29 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.35 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.68 # Average write queue length when enqueuing +system.physmem.readRowHits 152202 # Number of row buffer hits during reads +system.physmem.writeRowHits 75997 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.65 # Row buffer hit rate for writes +system.physmem.avgGap 88734.78 # Average gap between requests +system.physmem.pageHitRate 81.41 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 12.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 721249438 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35493 # Transaction distribution +system.membus.trans_dist::ReadResp 35493 # Transaction distribution +system.membus.trans_dist::Writeback 114017 # Transaction distribution +system.membus.trans_dist::ReadExReq 130806 # Transaction distribution +system.membus.trans_dist::ReadExResp 130806 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446615 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17940224 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940224 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1242127000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1541382250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1539178500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) -system.cpu.branchPred.lookups 16531947 # Number of BP lookups -system.cpu.branchPred.condPredicted 10672978 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 414050 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11481292 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7335496 # Number of BTB hits +system.cpu.branchPred.lookups 16532535 # Number of BP lookups +system.cpu.branchPred.condPredicted 10677865 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 412540 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11187771 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7331268 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.890858 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1991572 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 40927 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.529300 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1986493 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41581 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22403443 # DTB read hits -system.cpu.dtb.read_misses 219972 # DTB read misses -system.cpu.dtb.read_acv 45 # DTB read access violations -system.cpu.dtb.read_accesses 22623415 # DTB read accesses -system.cpu.dtb.write_hits 15699616 # DTB write hits -system.cpu.dtb.write_misses 41064 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15740680 # DTB write accesses -system.cpu.dtb.data_hits 38103059 # DTB hits -system.cpu.dtb.data_misses 261036 # DTB misses -system.cpu.dtb.data_acv 46 # DTB access violations -system.cpu.dtb.data_accesses 38364095 # DTB accesses -system.cpu.itb.fetch_hits 13905618 # ITB hits -system.cpu.itb.fetch_misses 35229 # ITB misses +system.cpu.dtb.read_hits 22399036 # DTB read hits +system.cpu.dtb.read_misses 220951 # DTB read misses +system.cpu.dtb.read_acv 40 # DTB read access violations +system.cpu.dtb.read_accesses 22619987 # DTB read accesses +system.cpu.dtb.write_hits 15703469 # DTB write hits +system.cpu.dtb.write_misses 40937 # DTB write misses +system.cpu.dtb.write_acv 5 # DTB write access violations +system.cpu.dtb.write_accesses 15744406 # DTB write accesses +system.cpu.dtb.data_hits 38102505 # DTB hits +system.cpu.dtb.data_misses 261888 # DTB misses +system.cpu.dtb.data_acv 45 # DTB access violations +system.cpu.dtb.data_accesses 38364393 # DTB accesses +system.cpu.itb.fetch_hits 13899355 # ITB hits +system.cpu.itb.fetch_misses 34906 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13940847 # ITB accesses +system.cpu.itb.fetch_accesses 13934261 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -362,98 +367,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49954048 # number of cpu cycles simulated +system.cpu.numCycles 49747630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15782352 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105305571 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16531947 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9327068 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19535430 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1996105 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7525610 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314470 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13905618 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 207845 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44615196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.360307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15785028 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105317585 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16532535 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9317761 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19533050 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1994568 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7608263 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7898 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 310217 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13899355 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 208294 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44693564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.356437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120216 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25079766 56.21% 56.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1526701 3.42% 59.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1368492 3.07% 62.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1511592 3.39% 66.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4137930 9.27% 75.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1849422 4.15% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 676249 1.52% 81.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069566 2.40% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7395478 16.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25160514 56.30% 56.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1525973 3.41% 59.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1366086 3.06% 62.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1510374 3.38% 66.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4139884 9.26% 75.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1847459 4.13% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 671184 1.50% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1072337 2.40% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7399753 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44615196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.330943 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.108049 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16870832 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7056928 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18547803 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 794977 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1344656 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3743758 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107019 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103586885 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 307942 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1344656 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17339272 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4755583 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85639 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18836599 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2253447 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102335224 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 557 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2492 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2137772 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61631332 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123302278 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122982558 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319719 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44693564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.332328 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.117037 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16872770 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7137515 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18556178 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 782832 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1344269 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3743968 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 106931 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103592319 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 303311 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1344269 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17342531 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4850765 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84983 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18829662 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2241354 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102344042 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 512 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2574 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2122740 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61629886 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123330813 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123015128 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 315684 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9084451 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5532 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5530 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4823408 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23239875 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16264209 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1185310 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 465013 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90722071 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5344 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88415019 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 95015 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10694229 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4666218 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 761 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44615196 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981724 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109954 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9083005 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5524 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5522 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4827061 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23228738 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16269123 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1186061 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 452179 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90719899 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5267 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88414674 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10680066 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4660295 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 684 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44693564 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.978242 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.110252 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16409410 36.78% 36.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6866152 15.39% 52.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5567351 12.48% 64.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4772569 10.70% 75.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4725060 10.59% 85.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2625070 5.88% 91.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1917083 4.30% 96.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1291638 2.90% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 440863 0.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16504766 36.93% 36.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6842289 15.31% 52.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5576642 12.48% 64.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4760179 10.65% 75.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4735432 10.60% 85.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2623142 5.87% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1921443 4.30% 96.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1284900 2.87% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 444771 1.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44615196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44693564 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126842 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126888 6.81% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available @@ -482,19 +487,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 784071 42.12% 48.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 950643 51.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 786366 42.17% 48.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 951332 51.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49344695 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43834 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49347874 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43826 0.05% 55.86% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121349 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121152 0.14% 56.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38963 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 120827 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120926 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 58 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38966 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -516,84 +521,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22855764 25.85% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15889119 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22848043 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15894065 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88415019 # Type of FU issued -system.cpu.iq.rate 1.769927 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1861556 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021055 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222796879 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101023469 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86533748 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 604926 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 415943 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294379 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89974024 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 302551 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1471412 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88414674 # Type of FU issued +system.cpu.iq.rate 1.777264 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1864586 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021089 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222880329 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101013312 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86537625 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 602080 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 409925 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294164 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89978136 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301124 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1470512 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2963237 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4955 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18224 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1650832 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2952100 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4699 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18249 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1655746 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2867 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 96301 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2987 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 95590 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1344656 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3651094 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 72855 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100203758 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 216158 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23239875 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16264209 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5344 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49772 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6561 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18224 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 192723 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161669 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 354392 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87578159 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22626447 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 836860 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1344269 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3728175 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74875 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100203568 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217116 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23228738 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16269123 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5267 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49826 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6538 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18249 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 191969 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160202 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 352171 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87579420 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22623199 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 835254 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9476343 # number of nop insts executed -system.cpu.iew.exec_refs 38367436 # number of memory reference insts executed -system.cpu.iew.exec_branches 15087087 # Number of branches executed -system.cpu.iew.exec_stores 15740989 # Number of stores executed -system.cpu.iew.exec_rate 1.753174 # Inst execution rate -system.cpu.iew.wb_sent 87216851 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86828127 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33345535 # num instructions producing a value -system.cpu.iew.wb_consumers 43468305 # num instructions consuming a value +system.cpu.iew.exec_nop 9478402 # number of nop insts executed +system.cpu.iew.exec_refs 38367932 # number of memory reference insts executed +system.cpu.iew.exec_branches 15082234 # Number of branches executed +system.cpu.iew.exec_stores 15744733 # Number of stores executed +system.cpu.iew.exec_rate 1.760474 # Inst execution rate +system.cpu.iew.wb_sent 87221630 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86831789 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33348400 # num instructions producing a value +system.cpu.iew.wb_consumers 43473071 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.738160 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767123 # average fanout of values written-back +system.cpu.iew.wb_rate 1.745446 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767105 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8869178 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8866636 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 309326 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43270540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.041589 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.791914 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 307777 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43349295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.037880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791190 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20425554 47.20% 47.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7044262 16.28% 63.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3374707 7.80% 71.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2054728 4.75% 76.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2036437 4.71% 80.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1166697 2.70% 83.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1108378 2.56% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 724905 1.68% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5334872 12.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20524240 47.35% 47.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7032147 16.22% 63.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3350548 7.73% 71.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2057076 4.75% 76.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2049777 4.73% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1169910 2.70% 83.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1109421 2.56% 86.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718391 1.66% 87.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5337785 12.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43270540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43349295 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -604,212 +609,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5334872 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5337785 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133828176 # The number of ROB reads -system.cpu.rob.rob_writes 195767077 # The number of ROB writes -system.cpu.timesIdled 83938 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5338852 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133901476 # The number of ROB reads +system.cpu.rob.rob_writes 195761663 # The number of ROB writes +system.cpu.timesIdled 83653 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5054066 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.627628 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.627628 # CPI: Total CPI of All Threads -system.cpu.ipc 1.593299 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.593299 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115893073 # number of integer regfile reads -system.cpu.int_regfile_writes 57500612 # number of integer regfile writes -system.cpu.fp_regfile_reads 249654 # number of floating regfile reads -system.cpu.fp_regfile_writes 240130 # number of floating regfile writes -system.cpu.misc_regfile_reads 38049 # number of misc regfile reads +system.cpu.cpi 0.625035 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625035 # CPI: Total CPI of All Threads +system.cpu.ipc 1.599911 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.599911 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115904116 # number of integer regfile reads +system.cpu.int_regfile_writes 57506232 # number of integer regfile writes +system.cpu.fp_regfile_reads 249599 # number of floating regfile reads +system.cpu.fp_regfile_writes 239957 # number of floating regfile writes +system.cpu.misc_regfile_reads 38110 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1198592827 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155432 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155431 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186551 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580061 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 766612 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5969600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29937280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes) +system.cpu.toL2Bus.throughput 1204474416 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168935 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143420 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187275 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 767312 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5992768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29959872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29959872 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 402997000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 141571734 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141831227 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 327076000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 326236500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91227 # number of replacements -system.cpu.icache.tags.tagsinuse 1926.280031 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13799737 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.946792 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1926.280031 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940566 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940566 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13799737 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13799737 # 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number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2067336982 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2067336982 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2067336982 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13905617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13905617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13905617 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13905617 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13905617 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13905617 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007614 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007614 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007614 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007614 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007614 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007614 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19525.283170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19525.283170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19525.283170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19525.283170 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.icache.tags.replacements 91589 # number of replacements +system.cpu.icache.tags.tagsinuse 1926.117780 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13792950 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93637 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.302348 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20015752250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1926.117780 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940487 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940487 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13792950 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13792950 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13792950 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13792950 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13792950 # number of overall hits +system.cpu.icache.overall_hits::total 13792950 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106403 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106403 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106403 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106403 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106403 # number of overall misses +system.cpu.icache.overall_misses::total 106403 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2026702474 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2026702474 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2026702474 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2026702474 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2026702474 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2026702474 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13899353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13899353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13899353 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13899353 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13899353 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13899353 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007655 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007655 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007655 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007655 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007655 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007655 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19047.418531 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19047.418531 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19047.418531 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19047.418531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19047.418531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19047.418531 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 673 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 35.812500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.866667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12604 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12604 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12604 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12604 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12604 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12604 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93276 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93276 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93276 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93276 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93276 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93276 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1585767766 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1585767766 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1585767766 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1585767766 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1585767766 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1585767766 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006708 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006708 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006708 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006708 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006708 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006708 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17000.812278 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17000.812278 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17000.812278 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17000.812278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17000.812278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17000.812278 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12765 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12765 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12765 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12765 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12765 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12765 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93638 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93638 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93638 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93638 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93638 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93638 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1554482273 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1554482273 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1554482273 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1554482273 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1554482273 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1554482273 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006737 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006737 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006737 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16600.976879 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16600.976879 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16600.976879 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16600.976879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16600.976879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16600.976879 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132400 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30717.176709 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 159637 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164461 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.970668 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132395 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30693.596872 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 159984 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164457 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.972801 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26388.752281 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2106.212865 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2222.211563 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.805321 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064277 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.067817 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.937414 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 85619 # 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number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27852 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35509 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130797 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130797 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7657 # number of demand (read+write) misses +system.cpu.l2cache.tags.occ_blocks::writebacks 26343.566994 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2104.284685 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2245.745192 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.803942 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064218 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.068535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.936694 # 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Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994631 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994631 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20611135 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20611135 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574043 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574043 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 55 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 55 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34185178 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34185178 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34185178 # number of overall hits +system.cpu.dcache.overall_hits::total 34185178 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267491 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105301044001 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105301044001 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105301044001 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20878626 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20878626 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35496749 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35496749 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35496749 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35496749 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012808 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012808 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071118 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071118 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036813 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036813 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036813 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036813 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59595.145382 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59595.145382 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87144.823113 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 87144.823113 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81505.864935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81505.864935 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5253118 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 160 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112229 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35492003 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35492003 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35492003 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35492003 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012812 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012812 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036820 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036820 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036820 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036820 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60927.246150 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60927.246150 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85635.179837 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85635.179837 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80577.769786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80577.769786 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5154697 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112181 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.807135 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 160 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.949822 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks -system.cpu.dcache.writebacks::total 168929 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205307 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205307 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895863 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895863 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1101170 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1101170 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1101170 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1101170 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62160 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62160 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205566 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205566 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205566 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205566 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2516687000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2516687000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14340164994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14340164994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16856851994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16856851994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16856851994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16856851994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002977 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002977 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 168935 # number of writebacks +system.cpu.dcache.writebacks::total 168935 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205357 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205357 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895917 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895917 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101274 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101274 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101274 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101274 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62134 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62134 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143417 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143417 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205551 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205551 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205551 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205551 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523454750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523454750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14076498244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14076498244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16599952994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16599952994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16599952994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16599952994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.242600 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.242600 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99996.966612 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99996.966612 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40613.106351 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40613.106351 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98150.834587 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98150.834587 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 9aa909b09..1084e1661 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026765 # Number of seconds simulated -sim_ticks 26765004500 # Number of ticks simulated -final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026816 # Number of seconds simulated +sim_ticks 26816405500 # Number of ticks simulated +final_tick 26816405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122306 # Simulator instruction rate (inst/s) -host_op_rate 173568 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46166163 # Simulator tick rate (ticks/s) -host_mem_usage 255896 # Number of bytes of host memory used -host_seconds 579.75 # Real time elapsed on the host +host_inst_rate 109329 # Simulator instruction rate (inst/s) +host_op_rate 155152 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41346943 # Simulator tick rate (ticks/s) +host_mem_usage 283460 # Number of bytes of host memory used +host_seconds 648.57 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7944704 # Number of bytes read from this memory -system.physmem.bytes_read::total 8242496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 297792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 297792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372160 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372160 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4653 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124136 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128789 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83940 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83940 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11126170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296831783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307957953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11126170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11126170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200715827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200715827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200715827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128790 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 83940 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 128790 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 83940 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 8242496 # Total number of bytes read from memory -system.physmem.bytesWritten 5372160 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8298 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8449 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8089 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 7883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7888 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7978 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8014 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5206 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5091 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5143 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5342 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5363 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5227 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26764988000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128790 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83940 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 76190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 50560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942848 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372096 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124107 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128770 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83939 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83939 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11128710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296193612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307322322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11128710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11128710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200328713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200328713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200328713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11128710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296193612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 507651035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128770 # Number of read requests accepted +system.physmem.writeReqs 83939 # Number of write requests accepted +system.physmem.readBursts 128770 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83939 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8241152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8241280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 318 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8144 # Per bank write bursts +system.physmem.perBankRdBursts::1 8386 # Per bank write bursts +system.physmem.perBankRdBursts::2 8247 # Per bank write bursts +system.physmem.perBankRdBursts::3 8164 # Per bank write bursts +system.physmem.perBankRdBursts::4 8296 # Per bank write bursts +system.physmem.perBankRdBursts::5 8451 # Per bank write bursts +system.physmem.perBankRdBursts::6 8094 # Per bank write bursts +system.physmem.perBankRdBursts::7 7961 # Per bank write bursts +system.physmem.perBankRdBursts::8 8061 # Per bank write bursts +system.physmem.perBankRdBursts::9 7610 # Per bank write bursts +system.physmem.perBankRdBursts::10 7787 # Per bank write bursts +system.physmem.perBankRdBursts::11 7813 # Per bank write bursts +system.physmem.perBankRdBursts::12 7882 # Per bank write bursts +system.physmem.perBankRdBursts::13 7886 # Per bank write bursts +system.physmem.perBankRdBursts::14 7979 # Per bank write bursts +system.physmem.perBankRdBursts::15 8007 # Per bank write bursts +system.physmem.perBankWrBursts::0 5180 # Per bank write bursts +system.physmem.perBankWrBursts::1 5376 # Per bank write bursts +system.physmem.perBankWrBursts::2 5287 # Per bank write bursts +system.physmem.perBankWrBursts::3 5157 # Per bank write bursts +system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::5 5517 # Per bank write bursts +system.physmem.perBankWrBursts::6 5205 # Per bank write bursts +system.physmem.perBankWrBursts::7 5049 # Per bank write bursts +system.physmem.perBankWrBursts::8 5030 # Per bank write bursts +system.physmem.perBankWrBursts::9 5090 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::11 5144 # Per bank write bursts +system.physmem.perBankWrBursts::12 5342 # Per bank write bursts +system.physmem.perBankWrBursts::13 5363 # Per bank write bursts +system.physmem.perBankWrBursts::14 5451 # Per bank write bursts +system.physmem.perBankWrBursts::15 5223 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 26816294000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 128770 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 83939 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 72833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -125,214 +127,221 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3650 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34959 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 389.285277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.799947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 855.459025 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 13425 38.40% 38.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5427 15.52% 53.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3113 8.90% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2218 6.34% 69.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1684 4.82% 73.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1324 3.79% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1016 2.91% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 832 2.38% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 675 1.93% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 524 1.50% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 431 1.23% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 550 1.57% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 311 0.89% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 325 0.93% 91.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 173 0.49% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 178 0.51% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 117 0.33% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 209 0.60% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 130 0.37% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 238 0.68% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 111 0.32% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 314 0.90% 95.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 120 0.34% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 318 0.91% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 69 0.20% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 140 0.40% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 41 0.12% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 97 0.28% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 65 0.19% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 25 0.07% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 42 0.12% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 12 0.03% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 31 0.09% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.05% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 26 0.07% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 33 0.09% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 11 0.03% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 15 0.04% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 11 0.03% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 8 0.02% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 11 0.03% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 15 0.04% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 9 0.03% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 11 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 6 0.02% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 5 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 3 0.01% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 7 0.02% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 3 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 4 0.01% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 6 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 3 0.01% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 9 0.03% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 3 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 3 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 4 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 3 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 4 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 4 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 5 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 2 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 6 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 239 0.68% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34959 # Bytes accessed per row activation -system.physmem.totQLat 2852295000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4861110000 # Sum of mem lat for all requests -system.physmem.totBusLat 643935000 # Total cycles spent in databus access -system.physmem.totBankLat 1364880000 # Total cycles spent in bank access -system.physmem.avgQLat 22147.38 # Average queueing delay per request -system.physmem.avgBankLat 10597.96 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37745.35 # Average memory access latency -system.physmem.avgRdBW 307.96 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 200.72 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 307.96 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 200.72 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 37861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.431816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.292002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 695.442994 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 15095 39.87% 39.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5646 14.91% 54.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3407 9.00% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2352 6.21% 69.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1734 4.58% 74.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1565 4.13% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1073 2.83% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 929 2.45% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 665 1.76% 85.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 565 1.49% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 384 1.01% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 558 1.47% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 286 0.76% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 361 0.95% 91.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 176 0.46% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 218 0.58% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 133 0.35% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 117 0.31% 93.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 270 0.71% 94.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 104 0.27% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 418 1.10% 95.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 100 0.26% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 243 0.64% 96.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 38 0.10% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 144 0.38% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 38 0.10% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 86 0.23% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 54 0.14% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 16 0.04% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 43 0.11% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 22 0.06% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 34 0.09% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 17 0.04% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 32 0.08% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 11 0.03% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 29 0.08% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 17 0.04% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 31 0.08% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 15 0.04% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 11 0.03% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 11 0.03% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 9 0.02% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 8 0.02% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 21 0.06% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 10 0.03% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 21 0.06% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 6 0.02% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 11 0.03% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 10 0.03% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 7 0.02% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 17 0.04% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 5 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 7 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 6 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 6 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 13 0.03% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 11 0.03% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 8 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 10 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 6 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 7 0.02% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 8 0.02% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 2 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 4 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 2 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 6 0.02% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 3 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 4 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 36 0.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37861 # Bytes accessed per row activation +system.physmem.totQLat 3024623000 # Total ticks spent queuing +system.physmem.totMemAccLat 4968016750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643840000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1299553750 # Total ticks spent accessing banks +system.physmem.avgQLat 23488.93 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10092.21 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 38581.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 307.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 200.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 307.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 200.33 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.97 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 10.24 # Average write queue length over time -system.physmem.readRowHits 120249 # Number of row buffer hits during reads -system.physmem.writeRowHits 57506 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.51 # Row buffer hit rate for writes -system.physmem.avgGap 125816.71 # Average gap between requests -system.membus.throughput 508673780 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26538 # Transaction distribution -system.membus.trans_dist::ReadResp 26537 # Transaction distribution -system.membus.trans_dist::Writeback 83940 # Transaction distribution -system.membus.trans_dist::UpgradeReq 321 # Transaction distribution -system.membus.trans_dist::UpgradeResp 321 # Transaction distribution -system.membus.trans_dist::ReadExReq 102252 # Transaction distribution -system.membus.trans_dist::ReadExResp 102252 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342161 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13614656 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13614656 # Total data (bytes) +system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.56 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.76 # Average write queue length when enqueuing +system.physmem.readRowHits 117866 # Number of row buffer hits during reads +system.physmem.writeRowHits 56971 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.87 # Row buffer hit rate for writes +system.physmem.avgGap 126070.33 # Average gap between requests +system.physmem.pageHitRate 82.20 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.88 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 507651035 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26514 # Transaction distribution +system.membus.trans_dist::ReadResp 26514 # Transaction distribution +system.membus.trans_dist::Writeback 83939 # Transaction distribution +system.membus.trans_dist::UpgradeReq 318 # Transaction distribution +system.membus.trans_dist::UpgradeResp 318 # Transaction distribution +system.membus.trans_dist::ReadExReq 102256 # Transaction distribution +system.membus.trans_dist::ReadExResp 102256 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342115 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342115 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13613376 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13613376 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13613376 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934803500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1207011429 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1203423433 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) -system.cpu.branchPred.lookups 16635237 # Number of BP lookups -system.cpu.branchPred.condPredicted 12768503 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 604840 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10652885 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7773045 # Number of BTB hits +system.cpu.branchPred.lookups 16622919 # Number of BP lookups +system.cpu.branchPred.condPredicted 12749857 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 605504 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10570940 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7775711 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.966572 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1823659 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113448 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.557423 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1829148 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113993 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -376,136 +385,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53530010 # number of cpu cycles simulated +system.cpu.numCycles 53632812 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12549473 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85279503 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16635237 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9596704 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21206249 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2379470 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10773225 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 477 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11686664 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 178212 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46277294 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.580240 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.332526 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12575227 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85200235 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16622919 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9604859 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21200799 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2368859 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10684050 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 493 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11692200 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 184239 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46197272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332808 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25091643 54.22% 54.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2136768 4.62% 58.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1963962 4.24% 63.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2042989 4.41% 67.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1466847 3.17% 70.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1383026 2.99% 73.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 957932 2.07% 75.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1190240 2.57% 78.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10043887 21.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25016575 54.15% 54.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2138831 4.63% 58.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1968354 4.26% 63.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2045405 4.43% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466932 3.18% 70.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1376276 2.98% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 961294 2.08% 75.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1190217 2.58% 78.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10033388 21.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46277294 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310765 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.593116 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14640784 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9115289 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19504792 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1371825 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1644604 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3334519 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105037 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116943845 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363315 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1644604 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16350397 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2675070 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1001661 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19117578 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5487984 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115077475 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 183 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17134 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4627273 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 285 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115384718 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 530174580 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476867094 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3452 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46197272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309939 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.588584 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14661485 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9032065 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19500717 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1369785 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1633220 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3334387 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 105402 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116870755 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 365005 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1633220 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16370455 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2587455 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1031873 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19111398 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5462871 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114984523 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15960 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4602334 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 241 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115277175 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529754178 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476504412 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2548 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16252046 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20256 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20253 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13031784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29643166 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22451729 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3891559 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4392801 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111618845 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35897 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107291250 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 275974 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10887740 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26073816 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2111 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46277294 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.318443 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.990403 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16144503 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20627 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20613 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12986013 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29603679 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22442541 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3905979 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4383979 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111534291 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36144 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107247539 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 279427 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10792871 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25872402 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2358 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46197272 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.321512 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.989577 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11003161 23.78% 23.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8115395 17.54% 41.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7436608 16.07% 57.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7096880 15.34% 72.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5407297 11.68% 84.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3935038 8.50% 92.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1843993 3.98% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 867713 1.88% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571209 1.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10946962 23.70% 23.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8090791 17.51% 41.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7422192 16.07% 57.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7125519 15.42% 72.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5414632 11.72% 84.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3916527 8.48% 92.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1842332 3.99% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 865884 1.87% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 572433 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46277294 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46197272 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 113414 4.57% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1362149 54.91% 59.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1005332 40.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 111334 4.52% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1349070 54.73% 59.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1004381 40.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56660345 52.81% 52.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91595 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56643981 52.82% 52.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91446 0.09% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 269 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 176 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued @@ -531,84 +540,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28911335 26.95% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21627699 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28888115 26.94% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21623814 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107291250 # Type of FU issued -system.cpu.iq.rate 2.004320 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2480897 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023123 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263615967 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122570490 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105600159 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 698 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1174 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 216 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109771796 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 351 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2179165 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107247539 # Type of FU issued +system.cpu.iq.rate 1.999663 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2464786 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022982 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263436010 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122391385 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105557389 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 553 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 926 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109712054 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 271 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2181647 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2336058 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6530 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30281 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1895991 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2296571 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6409 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29938 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1886803 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 805 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1644604 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1147402 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 47438 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111664541 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 286964 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29643166 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22451729 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19977 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6774 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4975 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30281 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393124 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181749 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 574873 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106260947 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28610039 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030303 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1633220 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1092915 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45139 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111580294 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 294739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29603679 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22442541 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20224 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6335 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5295 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29938 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 394730 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181332 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 576062 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106214921 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28587238 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1032618 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9799 # number of nop insts executed -system.cpu.iew.exec_refs 49952901 # number of memory reference insts executed -system.cpu.iew.exec_branches 14605114 # Number of branches executed -system.cpu.iew.exec_stores 21342862 # Number of stores executed -system.cpu.iew.exec_rate 1.985072 # Inst execution rate -system.cpu.iew.wb_sent 105821179 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105600375 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53334269 # num instructions producing a value -system.cpu.iew.wb_consumers 103952809 # num instructions consuming a value +system.cpu.iew.exec_nop 9859 # number of nop insts executed +system.cpu.iew.exec_refs 49925863 # number of memory reference insts executed +system.cpu.iew.exec_branches 14600722 # Number of branches executed +system.cpu.iew.exec_stores 21338625 # Number of stores executed +system.cpu.iew.exec_rate 1.980409 # Inst execution rate +system.cpu.iew.wb_sent 105779922 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105557547 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53302648 # num instructions producing a value +system.cpu.iew.wb_consumers 103946447 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.972732 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.513062 # average fanout of values written-back +system.cpu.iew.wb_rate 1.968152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512790 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11033009 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10948789 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 501673 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44632690 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.254680 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.761954 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 502113 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44564052 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.258153 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.763889 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15532654 34.80% 34.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11684135 26.18% 60.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3462025 7.76% 68.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2877014 6.45% 75.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1854993 4.16% 79.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1951437 4.37% 83.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 690877 1.55% 85.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 565658 1.27% 86.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6013897 13.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15506218 34.80% 34.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11644493 26.13% 60.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3446423 7.73% 68.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2869378 6.44% 75.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1870309 4.20% 79.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1959985 4.40% 83.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685768 1.54% 85.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 560638 1.26% 86.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6020840 13.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44632690 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44564052 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -619,226 +628,226 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6013897 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6020840 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150258931 # The number of ROB reads -system.cpu.rob.rob_writes 224984633 # The number of ROB writes -system.cpu.timesIdled 80350 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7252716 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150099130 # The number of ROB reads +system.cpu.rob.rob_writes 224804524 # The number of ROB writes +system.cpu.timesIdled 76985 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7435540 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.754926 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.754926 # CPI: Total CPI of All Threads -system.cpu.ipc 1.324633 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.324633 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511766096 # number of integer regfile reads -system.cpu.int_regfile_writes 103375635 # number of integer regfile writes -system.cpu.fp_regfile_reads 1160 # number of floating regfile reads -system.cpu.fp_regfile_writes 1012 # number of floating regfile writes -system.cpu.misc_regfile_reads 49188390 # number of misc regfile reads +system.cpu.cpi 0.756376 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.756376 # CPI: Total CPI of All Threads +system.cpu.ipc 1.322094 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.322094 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511539854 # number of integer regfile reads +system.cpu.int_regfile_writes 103334614 # number of integer regfile writes +system.cpu.fp_regfile_reads 734 # number of floating regfile reads +system.cpu.fp_regfile_writes 630 # number of floating regfile writes +system.cpu.misc_regfile_reads 49164319 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 771895107 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 86668 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 86666 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129110 # Transaction distribution +system.cpu.toL2Bus.throughput 775188755 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 88572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 88572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129187 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61963 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454719 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 516682 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1966784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20627776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 107050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107050 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65806 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 520581 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2089088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18665280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20754368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20754368 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 33408 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 291762996 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47827231 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 50495227 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 262412261 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 260303004 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 28871 # number of replacements -system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 30799 # number of replacements +system.cpu.icache.tags.tagsinuse 1804.677341 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11655246 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 32836 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 354.953283 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11651673 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11651673 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11651673 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11651673 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11651673 # number of overall hits -system.cpu.icache.overall_hits::total 11651673 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34991 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34991 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34991 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34991 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34991 # number of overall misses -system.cpu.icache.overall_misses::total 34991 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 840169228 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 840169228 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 840169228 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 840169228 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 840169228 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 840169228 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11686664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11686664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11686664 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11686664 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11686664 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11686664 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002994 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002994 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002994 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002994 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002994 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002994 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24011.009345 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24011.009345 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24011.009345 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24011.009345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24011.009345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24011.009345 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1080 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1804.677341 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.881190 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.881190 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11655255 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11655255 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11655255 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11655255 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11655255 # number of overall hits +system.cpu.icache.overall_hits::total 11655255 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 36945 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 36945 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 36945 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 36945 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 36945 # number of overall misses +system.cpu.icache.overall_misses::total 36945 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 836533724 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 836533724 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 836533724 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 836533724 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 836533724 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 836533724 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11692200 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11692200 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11692200 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11692200 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11692200 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11692200 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003160 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003160 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003160 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003160 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003160 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003160 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22642.677602 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22642.677602 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22642.677602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22642.677602 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 965 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.956522 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 48.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3759 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3759 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3759 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3759 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3759 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3759 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31232 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31232 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31232 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31232 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -847,195 +856,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83940 # number of writebacks -system.cpu.l2cache.writebacks::total 83940 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83939 # number of writebacks +system.cpu.l2cache.writebacks::total 83939 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1590135750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1921896250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3200320 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3200320 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7097849501 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7097849501 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 331760500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8687985251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9019745751 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 331760500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8687985251 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9019745751 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394780 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307980 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.952381 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.952381 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955341 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955341 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764072 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.666617 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764072 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.666617 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71300.343864 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72658.704592 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72420.538473 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69414.584423 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69414.584423 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 78 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4663 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21851 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26514 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 318 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 318 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102256 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102256 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4663 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124107 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128770 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4663 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124107 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128770 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 307037750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1604664499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1911702249 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3189317 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3189317 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7230852500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7230852500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307037750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8835516999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9142554749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307037750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8835516999 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9142554749 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394365 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.301124 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.946429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.946429 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72101.616090 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.298742 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.298742 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70713.234431 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70713.234431 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158372 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44374327 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162468 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 273.126566 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993506 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26075013 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26075013 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266800 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266800 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15987 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15987 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 158362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.865935 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44347537 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 272.978474 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.865935 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993375 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993375 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26048299 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26048299 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18266707 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18266707 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44341813 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44341813 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44341813 # number of overall hits -system.cpu.dcache.overall_hits::total 44341813 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 124981048011 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 861250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 861250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 130180442233 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 130180442233 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 130180442233 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 130180442233 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26200390 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26200390 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44315006 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44315006 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44315006 # number of overall hits +system.cpu.dcache.overall_hits::total 44315006 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125034 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125034 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583194 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583194 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1708228 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1708228 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1708228 # number of overall misses +system.cpu.dcache.overall_misses::total 1708228 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5241649212 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5241649212 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126812367989 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126812367989 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 914750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 914750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 132054017201 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 132054017201 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 132054017201 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 132054017201 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26173333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26173333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46050291 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46050291 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46050291 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46050291 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004785 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004785 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079754 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079754 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002620 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002620 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037100 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037100 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037100 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037100 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41470.080015 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41470.080015 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78946.983175 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 78946.983175 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20505.952381 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20505.952381 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76196.733135 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76196.733135 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9105 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1249 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 129 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.581395 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 78.062500 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46023234 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46023234 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46023234 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46023234 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004777 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004777 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079758 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079758 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037117 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037117 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037117 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037117 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41921.790969 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41921.790969 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80099.070606 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80099.070606 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22310.975610 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22310.975610 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77304.679001 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77304.679001 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4730 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.028777 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 87.428571 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129110 # number of writebacks -system.cpu.dcache.writebacks::total 129110 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69907 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69907 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475766 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475766 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545673 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545673 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545673 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545673 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55470 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55470 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107335 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107335 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162805 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162805 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162805 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162805 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2262652309 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2262652309 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8543267922 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8543267922 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10805920231 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10805920231 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10805920231 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10805920231 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40790.559023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40790.559023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79594.427931 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79594.427931 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129187 # number of writebacks +system.cpu.dcache.writebacks::total 129187 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69592 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69592 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475842 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475842 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1545434 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1545434 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1545434 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1545434 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55442 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55442 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107352 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107352 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162794 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162794 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162794 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162794 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2274282063 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2274282063 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8672803924 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8672803924 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947085987 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10947085987 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947085987 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10947085987 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003537 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003537 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41020.923902 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41020.923902 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80788.470862 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80788.470862 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index b5eeb298e..e22bfa1d8 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,102 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.017017 # Number of seconds simulated -sim_ticks 1017016979500 # Number of ticks simulated -final_tick 1017016979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.009838 # Number of seconds simulated +sim_ticks 1009838214500 # Number of ticks simulated +final_tick 1009838214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89946 # Simulator instruction rate (inst/s) -host_op_rate 89946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50268200 # Simulator tick rate (ticks/s) -host_mem_usage 224748 # Number of bytes of host memory used -host_seconds 20231.82 # Real time elapsed on the host +host_inst_rate 108402 # Simulator instruction rate (inst/s) +host_op_rate 108402 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60154913 # Simulator tick rate (ticks/s) +host_mem_usage 256492 # Number of bytes of host memory used +host_seconds 16787.29 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125365248 # Number of bytes read from this memory -system.physmem.bytes_read::total 125420224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory +system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory -system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory +system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958832 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959691 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 123267606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 123321662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54056 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54056 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 64065511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 64065511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 64065511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 123267606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 187387172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959691 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 1018058 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 1959691 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 1018058 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 125420224 # Total number of bytes read from memory -system.physmem.bytesWritten 65155712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125420224 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 116204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 117699 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 117773 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 117508 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 119859 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 124486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 126961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 130063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 128618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 130264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 125937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 125207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 122563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123183 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 61224 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 61467 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 60558 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 61216 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 61647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63085 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 64137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 65334 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65770 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65297 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 65611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64203 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 64552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64187 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1017016906500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959691 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1018058 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1654293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 205923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 74498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24401 # What read queue length does an incoming req see +system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 54440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 124143704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 124198144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 64520751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 64520751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 64520751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 124143704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 188718895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959688 # Number of read requests accepted +system.physmem.writeReqs 1018055 # Number of write requests accepted +system.physmem.readBursts 1959688 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018055 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125384704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35328 # Total number of bytes read from write queue +system.physmem.bytesWritten 65154176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125420032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65155520 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 552 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 118719 # Per bank write bursts +system.physmem.perBankRdBursts::1 114075 # Per bank write bursts +system.physmem.perBankRdBursts::2 116210 # Per bank write bursts +system.physmem.perBankRdBursts::3 117697 # Per bank write bursts +system.physmem.perBankRdBursts::4 117769 # Per bank write bursts +system.physmem.perBankRdBursts::5 117504 # Per bank write bursts +system.physmem.perBankRdBursts::6 119870 # Per bank write bursts +system.physmem.perBankRdBursts::7 124481 # Per bank write bursts +system.physmem.perBankRdBursts::8 126964 # Per bank write bursts +system.physmem.perBankRdBursts::9 130062 # Per bank write bursts +system.physmem.perBankRdBursts::10 128627 # Per bank write bursts +system.physmem.perBankRdBursts::11 130265 # Per bank write bursts +system.physmem.perBankRdBursts::12 125943 # Per bank write bursts +system.physmem.perBankRdBursts::13 125205 # Per bank write bursts +system.physmem.perBankRdBursts::14 122569 # Per bank write bursts +system.physmem.perBankRdBursts::15 123176 # Per bank write bursts +system.physmem.perBankWrBursts::0 61223 # Per bank write bursts +system.physmem.perBankWrBursts::1 61467 # Per bank write bursts +system.physmem.perBankWrBursts::2 60558 # Per bank write bursts +system.physmem.perBankWrBursts::3 61216 # Per bank write bursts +system.physmem.perBankWrBursts::4 61647 # Per bank write bursts +system.physmem.perBankWrBursts::5 63084 # Per bank write bursts +system.physmem.perBankWrBursts::6 64137 # Per bank write bursts +system.physmem.perBankWrBursts::7 65614 # Per bank write bursts +system.physmem.perBankWrBursts::8 65332 # Per bank write bursts +system.physmem.perBankWrBursts::9 65770 # Per bank write bursts +system.physmem.perBankWrBursts::10 65297 # Per bank write bursts +system.physmem.perBankWrBursts::11 65611 # Per bank write bursts +system.physmem.perBankWrBursts::12 64149 # Per bank write bursts +system.physmem.perBankWrBursts::13 64192 # Per bank write bursts +system.physmem.perBankWrBursts::14 64551 # Per bank write bursts +system.physmem.perBankWrBursts::15 64186 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1009838141500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1959688 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1018055 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1662262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 204907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21383 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -125,237 +127,233 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 45701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 45681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 45688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 46199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 46504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 48930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1724249 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 110.484089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.062986 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.322838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1380983 80.09% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 190835 11.07% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 56645 3.29% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 27563 1.60% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15745 0.91% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10044 0.58% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6630 0.38% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6555 0.38% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3694 0.21% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 2928 0.17% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2668 0.15% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2688 0.16% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1402 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1069 0.06% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1034 0.06% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 922 0.05% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 816 0.05% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 818 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 762 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 561 0.03% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 627 0.04% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 841 0.05% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3636 0.21% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 543 0.03% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 234 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 178 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 137 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 143 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 89 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 86 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 92 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 67 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 60 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 58 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 44 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 52 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 29 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 31 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 19 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 27 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 22 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 16 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 31 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 31 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 24 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 13 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 19 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 18 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 13 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 23 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 24 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 19 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 13 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 10 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 24 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 9 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 18 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 9 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 16 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 19 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 19 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 7 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 9 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 20 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 7 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 13 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 14 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 14 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 18 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 115 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 10 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 19 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 14 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1430 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1724249 # Bytes accessed per row activation -system.physmem.totQLat 33963917000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 98664809500 # Sum of mem lat for all requests -system.physmem.totBusLat 9795575000 # Total cycles spent in databus access -system.physmem.totBankLat 54905317500 # Total cycles spent in bank access -system.physmem.avgQLat 17336.36 # Average queueing delay per request -system.physmem.avgBankLat 28025.57 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50361.93 # Average memory access latency -system.physmem.avgRdBW 123.32 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 64.07 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 123.32 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 64.07 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.46 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.10 # Average read queue length over time -system.physmem.avgWrQLen 10.57 # Average write queue length over time -system.physmem.readRowHits 900981 # Number of row buffer hits during reads -system.physmem.writeRowHits 351934 # Number of row buffer hits during writes -system.physmem.readRowHitRate 45.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.57 # Row buffer hit rate for writes -system.physmem.avgGap 341538.83 # Average gap between requests -system.membus.throughput 187387172 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1178393 # Transaction distribution -system.membus.trans_dist::ReadResp 1178393 # Transaction distribution -system.membus.trans_dist::Writeback 1018058 # Transaction distribution -system.membus.trans_dist::ReadExReq 781298 # Transaction distribution -system.membus.trans_dist::ReadExResp 781298 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937440 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4937440 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575936 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190575936 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190575936 # Total data (bytes) +system.physmem.bytesPerActivate::samples 1862401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 102.289945 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.389421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 186.671108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1500565 80.57% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 201454 10.82% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 59784 3.21% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 29274 1.57% 96.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16603 0.89% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10401 0.56% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7224 0.39% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6892 0.37% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4048 0.22% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3343 0.18% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3041 0.16% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2820 0.15% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1620 0.09% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1539 0.08% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1515 0.08% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1490 0.08% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1330 0.07% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1308 0.07% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 968 0.05% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1341 0.07% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 595 0.03% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2192 0.12% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 189 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 700 0.04% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 112 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 81 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 79 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 79 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 66 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 52 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 55 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 71 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 36 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 40 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 43 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 52 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 33 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 31 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 35 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 28 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 29 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 30 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 34 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 33 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 22 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 20 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 22 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 24 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 16 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 19 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 21 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 28 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 15 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 19 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 14 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 18 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 13 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 16 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 25 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 18 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 21 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 22 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 12 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 13 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 14 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 106 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 10 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 8 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 6 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 15 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 13 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 11 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 12 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 4 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 11 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 11 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 5 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 5 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 14 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 9 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 13 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 64 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 154 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1862401 # Bytes accessed per row activation +system.physmem.totQLat 23049370500 # Total ticks spent queuing +system.physmem.totMemAccLat 84969994250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9795680000 # Total ticks spent in databus transfers +system.physmem.totBankLat 52124943750 # Total ticks spent accessing banks +system.physmem.avgQLat 11765.07 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26606.09 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 43371.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 124.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 64.52 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 124.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 64.52 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.47 # Data bus utilization in percentage +system.physmem.busUtilRead 0.97 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.50 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.29 # Average write queue length when enqueuing +system.physmem.readRowHits 771404 # Number of row buffer hits during reads +system.physmem.writeRowHits 343365 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.73 # Row buffer hit rate for writes +system.physmem.avgGap 339128.71 # Average gap between requests +system.physmem.pageHitRate 37.44 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 12.16 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 188718895 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1178392 # Transaction distribution +system.membus.trans_dist::ReadResp 1178392 # Transaction distribution +system.membus.trans_dist::Writeback 1018055 # Transaction distribution +system.membus.trans_dist::ReadExReq 781296 # Transaction distribution +system.membus.trans_dist::ReadExResp 781296 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937431 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4937431 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190575552 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190575552 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11803876500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11787413500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 18471159750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18365913000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu.branchPred.lookups 326564713 # Number of BP lookups -system.cpu.branchPred.condPredicted 252601424 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138218301 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 218593713 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135545625 # Number of BTB hits +system.cpu.branchPred.lookups 326538195 # Number of BP lookups +system.cpu.branchPred.condPredicted 252572806 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138234365 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 220428693 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135446272 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.008016 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.446752 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444840309 # DTB read hits +system.cpu.dtb.read_hits 444831815 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449737387 # DTB read accesses -system.cpu.dtb.write_hits 160847153 # DTB write hits +system.cpu.dtb.read_accesses 449728893 # DTB read accesses +system.cpu.dtb.write_hits 160846718 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162548457 # DTB write accesses -system.cpu.dtb.data_hits 605687462 # DTB hits +system.cpu.dtb.write_accesses 162548022 # DTB write accesses +system.cpu.dtb.data_hits 605678533 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612285844 # DTB accesses -system.cpu.itb.fetch_hits 231947501 # ITB hits +system.cpu.dtb.data_accesses 612276915 # DTB accesses +system.cpu.itb.fetch_hits 231928866 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231947523 # ITB accesses +system.cpu.itb.fetch_accesses 231928888 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -369,34 +367,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2034033960 # number of cpu cycles simulated +system.cpu.numCycles 2019676430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172359749 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154204964 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667587623 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172263192 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154275003 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667627607 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043790240 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043830224 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651716905 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884714 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120522396 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11097447 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131619843 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83580106 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.161652 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139337588 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651720859 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884928 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120516333 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11119574 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131635907 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83564055 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.169113 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139356886 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1742086287 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742059065 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7521644 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 462344107 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571689853 # Number of cycles cpu stages are processed. -system.cpu.activity 77.269597 # Percentage of cycles cpu is active +system.cpu.timesIdled 7515569 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 447943127 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571733303 # Number of cycles cpu stages are processed. +system.cpu.activity 77.821045 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -408,72 +406,72 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.117736 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.109846 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.117736 # CPI: Total CPI of All Threads -system.cpu.ipc 0.894666 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.109846 # CPI: Total CPI of All Threads +system.cpu.ipc 0.901026 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.894666 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 847369948 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186664012 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.340423 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1100283558 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933750402 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.906333 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1061657822 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972376138 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 47.805305 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1624406509 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409627451 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.138673 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 1012697898 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021336062 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.212341 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.901026 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 833031471 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186644959 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.754211 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1085876245 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933800185 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.235138 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1047285366 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972391064 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.145884 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1610051905 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409624525 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.281691 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 998329603 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021346827 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.569825 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 668.751330 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 231946364 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 668.332859 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 231927727 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 270019.050058 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 269997.353900 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 668.751330 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.326539 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.326539 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231946364 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231946364 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231946364 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231946364 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231946364 # number of overall hits -system.cpu.icache.overall_hits::total 231946364 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1137 # number of overall misses -system.cpu.icache.overall_misses::total 1137 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82490250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82490250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82490250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82490250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82490250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82490250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231947501 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231947501 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231947501 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231947501 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231947501 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231947501 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 668.332859 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.326334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.326334 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231927727 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231927727 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231927727 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231927727 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231927727 # number of overall hits +system.cpu.icache.overall_hits::total 231927727 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses +system.cpu.icache.overall_misses::total 1139 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 82717000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 82717000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 82717000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 82717000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 82717000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 82717000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231928866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231928866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231928866 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231928866 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231928866 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231928866 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72550.791557 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72550.791557 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72550.791557 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72550.791557 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.475856 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72622.475856 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72622.475856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72622.475856 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -482,137 +480,137 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 162 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 278 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 278 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 278 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 278 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 278 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 65194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 65194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65194000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 65194000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 65136750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 65136750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 65136750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75895.227008 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75895.227008 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75895.227008 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75895.227008 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75895.227008 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75895.227008 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75828.579744 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75828.579744 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 805844654 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7222689 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7222689 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3693279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889621 # Transaction distribution +system.cpu.toL2Bus.throughput 811573074 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7222683 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7222683 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3693280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889623 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916181 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21917899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916174 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21917892 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819502720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 819557696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 819557696 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819502528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 819557504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 819557504 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10096073500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10096073000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1466500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1445250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14100129000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13991720500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 1926960 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30930.857959 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8958684 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1956753 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.578342 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 67691760750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14923.938165 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.347502 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15972.572292 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455442 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001048 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.487444 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.943935 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6044296 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044296 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693279 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693279 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108323 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108323 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7152619 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7152619 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7152619 # number of overall hits -system.cpu.l2cache.overall_hits::total 7152619 # number of overall hits +system.cpu.l2cache.tags.replacements 1926957 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30919.698652 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8958682 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1956750 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 169373942000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221830 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222689 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3693279 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3693279 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889621 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889621 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221824 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222683 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3693280 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111447 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112306 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.163152 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413468 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.413468 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413467 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413467 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.214986 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.215060 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215060 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74890.570431 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88394.302840 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 88384.459174 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101327.212856 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101327.212856 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74890.570431 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93552.711897 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 93544.531638 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74890.570431 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93552.711897 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 93544.531638 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.923166 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83367.057654 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.830055 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91056.663224 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91056.663224 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86429.034622 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86429.034622 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -621,86 +619,86 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1018058 # number of writebacks -system.cpu.l2cache.writebacks::total 1018058 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks +system.cpu.l2cache.writebacks::total 1018055 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177534 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1178393 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781298 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 781298 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177533 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178392 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83392423000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83445915750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61355655750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61355655750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53492750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144748078750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 144801571500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53492750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144748078750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 144801571500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413468 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413468 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413467 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62298.020955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62273.282887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70819.605905 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70813.375982 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.615477 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.615477 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62273.282887 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73895.209204 # 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Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4082.476561 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996698 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437268765 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268765 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156028804 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156028804 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593297569 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593297569 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593297569 # number of overall hits -system.cpu.dcache.overall_hits::total 593297569 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7326898 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7326898 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4699698 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4699698 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 12026596 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12026596 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12026596 # number of overall misses -system.cpu.dcache.overall_misses::total 12026596 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 189082879500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 189082879500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 263051310000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 263051310000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 452134189500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 452134189500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 452134189500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 452134189500 # number of overall miss cycles +system.cpu.dcache.tags.replacements 9107351 # number of replacements +system.cpu.dcache.tags.tagsinuse 4082.357931 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 593283203 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111447 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.114049 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 12709353000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4082.357931 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996669 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268777 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268777 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156014426 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156014426 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593283203 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593283203 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593283203 # number of overall hits +system.cpu.dcache.overall_hits::total 593283203 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326886 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326886 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4714076 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4714076 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12040962 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12040962 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12040962 # number of overall misses +system.cpu.dcache.overall_misses::total 12040962 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066802000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183066802000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 258282974250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 258282974250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 441349776250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 441349776250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 441349776250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 441349776250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -711,54 +709,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029240 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029240 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019868 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019868 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019868 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019868 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25806.675554 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25806.675554 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55971.960326 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55971.960326 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37594.527121 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37594.527121 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15699726 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7389800 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 434712 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 73152 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.115235 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 101.019794 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029329 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029329 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019892 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019892 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019892 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019892 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.621723 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.621723 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54789.734881 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54789.734881 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36654.029491 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36654.029491 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12098438 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7855784 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 422645 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 73423 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625532 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 106.993503 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693279 # number of writebacks -system.cpu.dcache.writebacks::total 3693279 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104626 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104626 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2810519 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2810519 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2915145 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2915145 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2915145 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2915145 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222272 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222272 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889179 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889179 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111451 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111451 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111451 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111451 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171880361750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171880361750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92301345750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92301345750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264181707500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 264181707500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264181707500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 264181707500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3693280 # number of writebacks +system.cpu.dcache.writebacks::total 3693280 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104620 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104620 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824895 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2824895 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2929515 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2929515 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2929515 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2929515 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222266 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222266 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889181 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889181 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111447 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111447 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111447 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111447 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165960748500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 165960748500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84277565500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84277565500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250238314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 250238314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250238314000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 250238314000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -767,14 +765,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23798.655292 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23798.655292 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48857.914337 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48857.914337 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22979.041273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22979.041273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.635773 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.635773 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index d01882912..fbdbcc030 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,105 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.694171 # Number of seconds simulated -sim_ticks 694171131000 # Number of ticks simulated -final_tick 694171131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.685488 # Number of seconds simulated +sim_ticks 685488076000 # Number of ticks simulated +final_tick 685488076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145628 # Simulator instruction rate (inst/s) -host_op_rate 145628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58230614 # Simulator tick rate (ticks/s) -host_mem_usage 230068 # Number of bytes of host memory used -host_seconds 11921.07 # Real time elapsed on the host +host_inst_rate 134484 # Simulator instruction rate (inst/s) +host_op_rate 134484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53101916 # Simulator tick rate (ticks/s) +host_mem_usage 257516 # Number of bytes of host memory used +host_seconds 12908.91 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125790400 # Number of bytes read from this memory -system.physmem.bytes_read::total 125852032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65261440 # Number of bytes written to this memory -system.physmem.bytes_written::total 65261440 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965475 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019710 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019710 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 88785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 181209495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 181298280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 88785 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 88785 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 94013475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 94013475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 94013475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 88785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 181209495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 275311755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966438 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 1019710 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 1966438 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 1019710 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 125852032 # Total number of bytes read from memory -system.physmem.bytesWritten 65261440 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125852032 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65261440 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 561 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 119011 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 114417 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 116554 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 118021 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 118126 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 117795 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 120229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 124937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 127536 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 130495 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 129073 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 130794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 126583 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 125666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 122963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123677 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 61282 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 61566 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 60662 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 61309 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 61746 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 64226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 65470 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65888 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65399 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 65733 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64314 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 64641 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64291 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry -system.physmem.totGap 694171008500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966438 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1019710 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1645970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 229492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125793664 # Number of bytes read from this memory +system.physmem.bytes_read::total 125855616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65265536 # Number of bytes written to this memory +system.physmem.bytes_written::total 65265536 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965526 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966494 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019774 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019774 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 183509631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 183600008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95210316 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95210316 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95210316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 183509631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 278810323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966494 # Number of read requests accepted +system.physmem.writeReqs 1019774 # Number of write requests accepted +system.physmem.readBursts 1966494 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1019774 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125820608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35008 # Total number of bytes read from write queue +system.physmem.bytesWritten 65264256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125855616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65265536 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 547 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 119024 # Per bank write bursts +system.physmem.perBankRdBursts::1 114431 # Per bank write bursts +system.physmem.perBankRdBursts::2 116551 # Per bank write bursts +system.physmem.perBankRdBursts::3 118044 # Per bank write bursts +system.physmem.perBankRdBursts::4 118169 # Per bank write bursts +system.physmem.perBankRdBursts::5 117821 # Per bank write bursts +system.physmem.perBankRdBursts::6 120193 # Per bank write bursts +system.physmem.perBankRdBursts::7 124929 # Per bank write bursts +system.physmem.perBankRdBursts::8 127563 # Per bank write bursts +system.physmem.perBankRdBursts::9 130460 # Per bank write bursts +system.physmem.perBankRdBursts::10 129120 # Per bank write bursts +system.physmem.perBankRdBursts::11 130791 # Per bank write bursts +system.physmem.perBankRdBursts::12 126621 # Per bank write bursts +system.physmem.perBankRdBursts::13 125625 # Per bank write bursts +system.physmem.perBankRdBursts::14 122955 # Per bank write bursts +system.physmem.perBankRdBursts::15 123650 # Per bank write bursts +system.physmem.perBankWrBursts::0 61294 # Per bank write bursts +system.physmem.perBankWrBursts::1 61576 # Per bank write bursts +system.physmem.perBankWrBursts::2 60653 # Per bank write bursts +system.physmem.perBankWrBursts::3 61320 # Per bank write bursts +system.physmem.perBankWrBursts::4 61767 # Per bank write bursts +system.physmem.perBankWrBursts::5 63184 # Per bank write bursts +system.physmem.perBankWrBursts::6 64210 # Per bank write bursts +system.physmem.perBankWrBursts::7 65704 # Per bank write bursts +system.physmem.perBankWrBursts::8 65475 # Per bank write bursts +system.physmem.perBankWrBursts::9 65876 # Per bank write bursts +system.physmem.perBankWrBursts::10 65422 # Per bank write bursts +system.physmem.perBankWrBursts::11 65733 # Per bank write bursts +system.physmem.perBankWrBursts::12 64307 # Per bank write bursts +system.physmem.perBankWrBursts::13 64297 # Per bank write bursts +system.physmem.perBankWrBursts::14 64633 # Per bank write bursts +system.physmem.perBankWrBursts::15 64303 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 685487953500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1966494 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1019774 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1645141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 231582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -125,237 +127,235 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1724767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 110.763752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.212194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.511378 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1378543 79.93% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 191920 11.13% 91.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 57620 3.34% 94.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 28373 1.65% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15698 0.91% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 9692 0.56% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6693 0.39% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6792 0.39% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3776 0.22% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 2960 0.17% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2630 0.15% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2677 0.16% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1390 0.08% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1126 0.07% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1092 0.06% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 878 0.05% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 859 0.05% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 813 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 757 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 627 0.04% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 709 0.04% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 705 0.04% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3570 0.21% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 579 0.03% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 253 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 194 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 146 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 142 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 94 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 85 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 102 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 71 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 61 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 59 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 49 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 59 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 39 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 46 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 34 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 39 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 28 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 48 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 43 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 24 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 22 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 32 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 25 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 21 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 25 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 26 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 19 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 25 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 13 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 27 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 21 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 6 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 16 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 14 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 28 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 7 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 10 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 9 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 6 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 14 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 10 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 9 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 12 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 10 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 21 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 7 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 7 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 19 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 17 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 11 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 123 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 12 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 18 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 15 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1429 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1724767 # Bytes accessed per row activation -system.physmem.totQLat 33917679750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 98022206000 # Sum of mem lat for all requests -system.physmem.totBusLat 9829385000 # Total cycles spent in databus access -system.physmem.totBankLat 54275141250 # Total cycles spent in bank access -system.physmem.avgQLat 17253.21 # Average queueing delay per request -system.physmem.avgBankLat 27608.62 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 49861.82 # Average memory access latency -system.physmem.avgRdBW 181.30 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 94.01 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 181.30 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 94.01 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 10.67 # Average write queue length over time -system.physmem.readRowHits 908058 # Number of row buffer hits during reads -system.physmem.writeRowHits 352757 # Number of row buffer hits during writes -system.physmem.readRowHitRate 46.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.59 # Row buffer hit rate for writes -system.physmem.avgGap 232463.70 # Average gap between requests -system.membus.throughput 275311755 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191259 # Transaction distribution -system.membus.trans_dist::ReadResp 1191259 # Transaction distribution -system.membus.trans_dist::Writeback 1019710 # Transaction distribution -system.membus.trans_dist::ReadExReq 775179 # Transaction distribution -system.membus.trans_dist::ReadExResp 775179 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4952586 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191113472 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191113472 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191113472 # Total data (bytes) +system.physmem.wrQLenPdf::0 45485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 45669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 45674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 45709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 46118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 46280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 49534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 48711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1822247 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.837037 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.099826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 197.854977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1460763 80.16% 80.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 186024 10.21% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 72307 3.97% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 32393 1.78% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16822 0.92% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10551 0.58% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6953 0.38% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6800 0.37% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3880 0.21% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3184 0.17% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2717 0.15% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2015 0.11% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1651 0.09% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1492 0.08% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1271 0.07% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1102 0.06% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 982 0.05% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1041 0.06% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 864 0.05% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 817 0.04% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 719 0.04% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2906 0.16% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 391 0.02% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 753 0.04% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 249 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 220 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 185 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 207 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 171 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 149 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 132 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 171 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 381 0.02% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 117 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 95 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 87 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 78 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 78 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 61 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 72 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 41 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 45 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 36 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 35 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 29 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 23 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 45 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 24 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 26 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 27 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 27 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 22 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 20 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 15 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 11 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 17 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 14 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 14 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 21 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 10 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 22 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 13 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 13 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 8 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 11 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 13 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 23 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 10 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 16 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 13 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 21 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 18 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 18 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 13 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 16 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 17 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 16 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 13 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 12 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 85 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 29 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 125 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1822247 # Bytes accessed per row activation +system.physmem.totQLat 24360796250 # Total ticks spent queuing +system.physmem.totMemAccLat 84735751250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9829735000 # Total ticks spent in databus transfers +system.physmem.totBankLat 50545220000 # Total ticks spent accessing banks +system.physmem.avgQLat 12391.38 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 25710.37 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 43101.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 183.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.21 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 183.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.21 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.18 # Data bus utilization in percentage +system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.12 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.63 # Average write queue length when enqueuing +system.physmem.readRowHits 818889 # Number of row buffer hits during reads +system.physmem.writeRowHits 344565 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.79 # Row buffer hit rate for writes +system.physmem.avgGap 229546.70 # Average gap between requests +system.physmem.pageHitRate 38.97 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 7.09 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 278810323 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191305 # Transaction distribution +system.membus.trans_dist::ReadResp 1191305 # Transaction distribution +system.membus.trans_dist::Writeback 1019774 # Transaction distribution +system.membus.trans_dist::ReadExReq 775189 # Transaction distribution +system.membus.trans_dist::ReadExResp 775189 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4952762 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191121152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191121152 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191121152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11881655250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11874044250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18594236500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18494220250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.branchPred.lookups 381853679 # Number of BP lookups -system.cpu.branchPred.condPredicted 296812462 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16082560 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 263010897 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259938392 # Number of BTB hits +system.cpu.branchPred.lookups 381678235 # Number of BP lookups +system.cpu.branchPred.condPredicted 296637110 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16088915 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262749250 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259783318 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.831796 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24703686 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3043 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.871193 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24705471 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613967200 # DTB read hits -system.cpu.dtb.read_misses 11252585 # DTB read misses +system.cpu.dtb.read_hits 613987676 # DTB read hits +system.cpu.dtb.read_misses 11260420 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625219785 # DTB read accesses -system.cpu.dtb.write_hits 212300531 # DTB write hits -system.cpu.dtb.write_misses 7117395 # DTB write misses +system.cpu.dtb.read_accesses 625248096 # DTB read accesses +system.cpu.dtb.write_hits 212348403 # DTB write hits +system.cpu.dtb.write_misses 7134109 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219417926 # DTB write accesses -system.cpu.dtb.data_hits 826267731 # DTB hits -system.cpu.dtb.data_misses 18369980 # DTB misses +system.cpu.dtb.write_accesses 219482512 # DTB write accesses +system.cpu.dtb.data_hits 826336079 # DTB hits +system.cpu.dtb.data_misses 18394529 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844637711 # DTB accesses -system.cpu.itb.fetch_hits 391085180 # ITB hits -system.cpu.itb.fetch_misses 51 # ITB misses +system.cpu.dtb.data_accesses 844730608 # DTB accesses +system.cpu.itb.fetch_hits 391118478 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391085231 # ITB accesses +system.cpu.itb.fetch_accesses 391118522 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -369,238 +369,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1388342263 # number of cpu cycles simulated +system.cpu.numCycles 1370976153 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402551684 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3162454030 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381853679 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284642078 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574754052 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140783496 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 197047269 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1488 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 391085180 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8065065 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1291251504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.449139 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.141692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402585457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3161328538 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381678235 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284488789 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574592396 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140681937 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 190961804 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1466 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 391118478 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8069239 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1284965558 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.460244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.144346 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 716497452 55.49% 55.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42682670 3.31% 58.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21784053 1.69% 60.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39696423 3.07% 63.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129425846 10.02% 73.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61545626 4.77% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38574460 2.99% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28124081 2.18% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212920893 16.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 710373162 55.28% 55.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42677954 3.32% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21796461 1.70% 60.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39706509 3.09% 63.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129357441 10.07% 73.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61547596 4.79% 78.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38577258 3.00% 81.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28126573 2.19% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212802604 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1291251504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275043 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.277863 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434540420 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 178303124 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542717448 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18794331 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116896181 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58354479 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 840 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3089587827 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116896181 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457532531 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 123212849 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5836 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535730171 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 57873936 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3007379456 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 610253 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1826446 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51579864 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2248363732 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3900421320 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3900278198 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 143121 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1284965558 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.278399 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.305896 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434593706 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 172173126 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542518914 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18856302 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116823510 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58351123 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 876 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3088655283 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2048 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116823510 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457554918 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116845929 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6766 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535622730 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 58111705 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3006575354 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 610156 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1852925 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51779132 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2247748999 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3899198212 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3899055356 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 142855 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 872160769 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 168 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 168 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123444205 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679751883 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255539846 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68026727 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37555626 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2725485841 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 123 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509620077 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3191439 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 980254556 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 417071077 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 94 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1291251504 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.943556 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971187 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 871546036 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 162 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 160 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123661161 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679705832 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255482967 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67737746 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37011786 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2724988246 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509612209 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3204133 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 979747229 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416253397 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1284965558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.953058 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971218 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 449456095 34.81% 34.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203314241 15.75% 50.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185688017 14.38% 64.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153487226 11.89% 76.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133078124 10.31% 87.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80722513 6.25% 93.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65115490 5.04% 98.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15268261 1.18% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5121537 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 442955350 34.47% 34.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203613373 15.85% 50.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185757734 14.46% 64.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153374382 11.94% 76.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133013671 10.35% 87.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80752885 6.28% 93.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65067569 5.06% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15309053 1.19% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5121541 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1291251504 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1284965558 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2192750 11.84% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11923038 64.36% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4410634 23.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2189478 11.81% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11923612 64.31% 76.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4426862 23.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643953882 65.51% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 103 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 266 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 157 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 35 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641631628 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224033966 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643894908 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 110 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 256 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641620248 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224096461 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509620077 # Type of FU issued -system.cpu.iq.rate 1.807638 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18526422 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007382 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6330307505 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3704630064 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413135648 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1902014 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1217951 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 852306 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527206104 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 940395 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62612888 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509612209 # Type of FU issued +system.cpu.iq.rate 1.830529 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18539952 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007388 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6324036158 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3703625637 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413191204 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1897903 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1215976 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 850771 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527214134 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 938027 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62593572 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235156220 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263801 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 109236 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94811344 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235110169 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263246 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107760 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94754465 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 161 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1579414 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 95 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1543010 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116896181 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 59627165 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1293281 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2867673451 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8945086 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679751883 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255539846 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 123 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 277586 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17880 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 109236 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10358298 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8554506 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18912804 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462213177 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625220360 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47406900 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116823510 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 56431673 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1297935 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2867161807 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8942583 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679705832 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255482967 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 282108 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18553 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107760 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10367292 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8554999 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18922291 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462270338 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625248683 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47341871 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142187487 # number of nop insts executed -system.cpu.iew.exec_refs 844638305 # number of memory reference insts executed -system.cpu.iew.exec_branches 300894564 # Number of branches executed -system.cpu.iew.exec_stores 219417945 # Number of stores executed -system.cpu.iew.exec_rate 1.773491 # Inst execution rate -system.cpu.iew.wb_sent 2441919357 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413987954 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388436926 # num instructions producing a value -system.cpu.iew.wb_consumers 1764428707 # num instructions consuming a value +system.cpu.iew.exec_nop 142173439 # number of nop insts executed +system.cpu.iew.exec_refs 844731223 # number of memory reference insts executed +system.cpu.iew.exec_branches 300901770 # Number of branches executed +system.cpu.iew.exec_stores 219482540 # Number of stores executed +system.cpu.iew.exec_rate 1.795998 # Inst execution rate +system.cpu.iew.wb_sent 2441991151 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2414041975 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388322535 # num instructions producing a value +system.cpu.iew.wb_consumers 1764247998 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.738756 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786905 # average fanout of values written-back +system.cpu.iew.wb_rate 1.760820 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786920 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 827192555 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 826708029 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16081773 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1174355323 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.549599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.495377 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16088134 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1168142048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.557841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.499033 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 660542597 56.25% 56.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174710504 14.88% 71.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86129545 7.33% 78.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53592661 4.56% 83.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34688707 2.95% 85.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26049111 2.22% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21601989 1.84% 90.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22901440 1.95% 91.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94138769 8.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 654070645 55.99% 55.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174984637 14.98% 70.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86150926 7.38% 78.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53558629 4.58% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34734385 2.97% 85.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26071538 2.23% 88.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21585678 1.85% 89.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22876428 1.96% 91.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94109182 8.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1174355323 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1168142048 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -611,209 +611,209 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94138769 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94109182 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3641410035 # The number of ROB reads -system.cpu.rob.rob_writes 5410940495 # The number of ROB writes -system.cpu.timesIdled 938493 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 97090759 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3634741821 # The number of ROB reads +system.cpu.rob.rob_writes 5409898345 # The number of ROB writes +system.cpu.timesIdled 948322 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 86010595 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.799716 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.799716 # CPI: Total CPI of All Threads -system.cpu.ipc 1.250444 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.250444 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318091757 # number of integer regfile reads -system.cpu.int_regfile_writes 1932096202 # number of integer regfile writes -system.cpu.fp_regfile_reads 30725 # number of floating regfile reads -system.cpu.fp_regfile_writes 534 # number of floating regfile writes +system.cpu.cpi 0.789713 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.789713 # CPI: Total CPI of All Threads +system.cpu.ipc 1.266283 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.266283 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318184796 # number of integer regfile reads +system.cpu.int_regfile_writes 1932088897 # number of integer regfile writes +system.cpu.fp_regfile_reads 30223 # number of floating regfile reads +system.cpu.fp_regfile_writes 511 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1189905456 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297551 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297551 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3725037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883631 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085475 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22087401 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825936384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 825998016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 825998016 # Total data (bytes) +system.cpu.toL2Bus.throughput 1204982897 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3725040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883606 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085568 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22087504 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825939456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 826001408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 826001408 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178230165 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10178244432 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1633750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1613250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14189007000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14084473000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 770.551884 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 391083687 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 406109.747664 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 776.507603 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391116973 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 968 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 404046.459711 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 770.551884 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376246 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376246 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 391083687 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391083687 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391083687 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391083687 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391083687 # number of overall hits -system.cpu.icache.overall_hits::total 391083687 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1493 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1493 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1493 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1493 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1493 # number of overall misses -system.cpu.icache.overall_misses::total 1493 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 108163750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 108163750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 108163750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 108163750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 108163750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 108163750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391085180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391085180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391085180 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391085180 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391085180 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391085180 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 776.507603 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.379154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.379154 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 391116973 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391116973 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391116973 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391116973 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391116973 # number of overall hits +system.cpu.icache.overall_hits::total 391116973 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1504 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1504 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1504 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1504 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1504 # number of overall misses +system.cpu.icache.overall_misses::total 1504 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108221250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108221250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108221250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108221250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108221250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108221250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391118477 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391118477 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391118477 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391118477 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391118477 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391118477 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72447.253851 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72447.253851 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72447.253851 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72447.253851 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72447.253851 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72447.253851 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 340 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71955.618351 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71955.618351 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71955.618351 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71955.618351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71955.618351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71955.618351 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 344 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 114.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 530 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 530 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 530 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 530 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 530 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 530 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 963 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 963 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 963 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75133750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75133750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75133750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75133750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75133750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75133750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 536 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 536 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 536 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 968 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75754750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75754750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75754750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75754750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75754750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75754750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78020.508827 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78020.508827 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78020.508827 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78020.508827 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78020.508827 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78020.508827 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78259.039256 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78259.039256 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78259.039256 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78259.039256 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78259.039256 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78259.039256 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1933728 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31435.165334 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9058547 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1963512 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.613441 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28123107250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14593.465528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.016964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16815.682842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.445357 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000794 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513174 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71882646250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 71882646250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 74164750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 183422419250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 183496584000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 74164750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 183422419250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 183496584000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 963 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296588 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297551 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3725037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3725037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883631 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883631 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 963 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180219 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181182 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 963 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180219 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181182 # number of overall (read+write) accesses +system.cpu.l2cache.tags.replacements 1933792 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31423.528987 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9058568 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1963567 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.613323 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28354220250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14586.952110 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.526107 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.050770 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.445158 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.513002 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73861.549275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73857.021557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64663.481405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73861.549275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73857.021557 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9176123 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.719090 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694209653 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9180219 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 75.620163 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5145271250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.719090 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997978 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997978 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538667558 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538667558 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155542093 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155542093 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694209651 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694209651 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 296662127899 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 461500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 461500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 651255459149 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 651255459149 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 651255459149 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 651255459149 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550051070 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550051070 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16575954 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16575954 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16575954 # number of overall misses +system.cpu.dcache.overall_misses::total 16575954 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 342766302500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 342766302500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 296010973410 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 296010973410 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 274500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 274500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 638777275910 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 638777275910 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 638777275910 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 638777275910 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550126892 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550126892 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710779572 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710779572 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710779572 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710779572 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020695 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020695 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032268 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032268 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023312 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023312 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023312 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023312 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31149.730527 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31149.730527 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57199.909976 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57199.909976 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 461500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 461500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39303.473997 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39303.473997 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39303.473997 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39303.473997 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13761211 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8306103 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 744858 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.474946 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 127.521348 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710855394 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710855394 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710855394 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710855394 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020700 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020700 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032282 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032282 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023318 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023318 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023318 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023318 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30100.538702 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30100.538702 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57050.555791 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57050.555791 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 274500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 274500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38536.380827 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38536.380827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38536.380827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38536.380827 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12380978 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8648655 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 745505 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.607505 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 132.782495 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725037 # number of writebacks -system.cpu.dcache.writebacks::total 3725037 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4086921 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4086921 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302782 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3302782 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7389703 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7389703 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7389703 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7389703 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296591 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296591 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883627 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883627 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725040 # number of writebacks +system.cpu.dcache.writebacks::total 3725040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4090717 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4090717 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3304974 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3304974 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7395691 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7395691 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7395691 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7395691 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296664 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296664 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883599 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883599 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180218 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180218 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180218 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180218 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180738700500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 180738700500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85282559486 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85282559486 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 459500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 459500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 266021259986 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 266021259986 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 266021259986 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 266021259986 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013265 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013265 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180263 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180263 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180263 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180263 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171778792500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171778792500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80694684874 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 80694684874 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 272500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 272500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252473477374 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 252473477374 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252473477374 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 252473477374 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012916 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012916 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012916 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012916 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24770.293484 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24770.293484 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45275.715142 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45275.715142 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 459500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 459500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28977.662620 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28977.662620 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28977.662620 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28977.662620 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012914 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012914 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23542.099855 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23542.099855 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42840.692140 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42840.692140 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 272500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 272500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.769543 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.769543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27501.769543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27501.769543 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 3c2739180..7989e6703 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,104 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.541686 # Number of seconds simulated -sim_ticks 541686426500 # Number of ticks simulated -final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.533691 # Number of seconds simulated +sim_ticks 533690503000 # Number of ticks simulated +final_tick 533690503000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133850 # Simulator instruction rate (inst/s) -host_op_rate 149320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46941984 # Simulator tick rate (ticks/s) -host_mem_usage 248124 # Number of bytes of host memory used -host_seconds 11539.49 # Real time elapsed on the host +host_inst_rate 128085 # Simulator instruction rate (inst/s) +host_op_rate 142888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44256929 # Simulator tick rate (ticks/s) +host_mem_usage 275676 # Number of bytes of host memory used +host_seconds 12058.91 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143725568 # Number of bytes read from this memory -system.physmem.bytes_read::total 143773696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70430528 # Number of bytes written to this memory -system.physmem.bytes_written::total 70430528 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 752 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245712 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246464 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100477 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100477 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 88848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 265329831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 265418679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 88848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 88848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 130020847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 130020847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 130020847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 88848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 265329831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 395439526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246464 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 1100477 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 2246464 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 1100477 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 143773696 # Total number of bytes read from memory -system.physmem.bytesWritten 70430528 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143773696 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70430528 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 599 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 139699 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 136238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 133756 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 136368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 134718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 135333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 136160 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 136095 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 143598 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 146293 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 144461 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 146176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 145883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 146345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 142220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 142522 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69143 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 67428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 65656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 66333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 66095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 66425 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 67930 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68755 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 70311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 70943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 70521 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 70921 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 70374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70896 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69672 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69074 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry -system.physmem.totGap 541686363500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246464 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1100477 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1615292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 444627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 139018 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 46909 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143713600 # Number of bytes read from this memory +system.physmem.bytes_read::total 143761344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70434112 # Number of bytes written to this memory +system.physmem.bytes_written::total 70434112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 746 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245525 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246271 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100533 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 269282663 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 269372123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 131975577 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 131975577 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 131975577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 269282663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401347700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246271 # Number of read requests accepted +system.physmem.writeReqs 1100533 # Number of write requests accepted +system.physmem.readBursts 2246271 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100533 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143722048 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 39296 # Total number of bytes read from write queue +system.physmem.bytesWritten 70432960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143761344 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70434112 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 614 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 139609 # Per bank write bursts +system.physmem.perBankRdBursts::1 136206 # Per bank write bursts +system.physmem.perBankRdBursts::2 133832 # Per bank write bursts +system.physmem.perBankRdBursts::3 136344 # Per bank write bursts +system.physmem.perBankRdBursts::4 135019 # Per bank write bursts +system.physmem.perBankRdBursts::5 135288 # Per bank write bursts +system.physmem.perBankRdBursts::6 136231 # Per bank write bursts +system.physmem.perBankRdBursts::7 136121 # Per bank write bursts +system.physmem.perBankRdBursts::8 143692 # Per bank write bursts +system.physmem.perBankRdBursts::9 146373 # Per bank write bursts +system.physmem.perBankRdBursts::10 144432 # Per bank write bursts +system.physmem.perBankRdBursts::11 146294 # Per bank write bursts +system.physmem.perBankRdBursts::12 145666 # Per bank write bursts +system.physmem.perBankRdBursts::13 146070 # Per bank write bursts +system.physmem.perBankRdBursts::14 142065 # Per bank write bursts +system.physmem.perBankRdBursts::15 142415 # Per bank write bursts +system.physmem.perBankWrBursts::0 69121 # Per bank write bursts +system.physmem.perBankWrBursts::1 67439 # Per bank write bursts +system.physmem.perBankWrBursts::2 65729 # Per bank write bursts +system.physmem.perBankWrBursts::3 66294 # Per bank write bursts +system.physmem.perBankWrBursts::4 66241 # Per bank write bursts +system.physmem.perBankWrBursts::5 66403 # Per bank write bursts +system.physmem.perBankWrBursts::6 67965 # Per bank write bursts +system.physmem.perBankWrBursts::7 68773 # Per bank write bursts +system.physmem.perBankWrBursts::8 70328 # Per bank write bursts +system.physmem.perBankWrBursts::9 70962 # Per bank write bursts +system.physmem.perBankWrBursts::10 70540 # Per bank write bursts +system.physmem.perBankWrBursts::11 70927 # Per bank write bursts +system.physmem.perBankWrBursts::12 70302 # Per bank write bursts +system.physmem.perBankWrBursts::13 70806 # Per bank write bursts +system.physmem.perBankWrBursts::14 69598 # Per bank write bursts +system.physmem.perBankWrBursts::15 69087 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 533690432500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 2246271 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1100533 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1620463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 446151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 135620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,217 +127,217 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1997603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.193624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.812437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 283.653287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1593724 79.78% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 230021 11.51% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 68328 3.42% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 32466 1.63% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 17759 0.89% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 11013 0.55% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7534 0.38% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 7551 0.38% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3933 0.20% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3162 0.16% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2715 0.14% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2783 0.14% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1408 0.07% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1190 0.06% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1060 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 829 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 802 0.04% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 757 0.04% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 590 0.03% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 531 0.03% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 601 0.03% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 798 0.04% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3587 0.18% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 465 0.02% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 167 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 158 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 120 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 86 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 82 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 107 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 81 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 77 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 52 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 39 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 40 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 36 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 29 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 41 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 32 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 31 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 29 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 27 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 27 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 30 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 18 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 33 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 19 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 18 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 11 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 17 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 17 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 21 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 17 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 17 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 31 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 28 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 33 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 14 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 16 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 15 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 12 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 17 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 17 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 11 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 10 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 15 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 14 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 8 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 7 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 7 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 122 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 15 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 8 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 6 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 8 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 8 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 20 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1459 0.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1997603 # Bytes accessed per row activation -system.physmem.totQLat 50283923250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 124431529500 # Sum of mem lat for all requests -system.physmem.totBusLat 11229325000 # Total cycles spent in databus access -system.physmem.totBankLat 62918281250 # Total cycles spent in bank access -system.physmem.avgQLat 22389.56 # Average queueing delay per request -system.physmem.avgBankLat 28015.17 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55404.72 # Average memory access latency -system.physmem.avgRdBW 265.42 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 130.02 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 265.42 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 130.02 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.09 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.23 # Average read queue length over time -system.physmem.avgWrQLen 10.65 # Average write queue length over time -system.physmem.readRowHits 1005654 # Number of row buffer hits during reads -system.physmem.writeRowHits 343066 # Number of row buffer hits during writes -system.physmem.readRowHitRate 44.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 31.17 # Row buffer hit rate for writes -system.physmem.avgGap 161845.21 # Average gap between requests -system.membus.throughput 395439408 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1420071 # Transaction distribution -system.membus.trans_dist::ReadResp 1420070 # Transaction distribution -system.membus.trans_dist::Writeback 1100477 # Transaction distribution -system.membus.trans_dist::ReadExReq 826393 # Transaction distribution -system.membus.trans_dist::ReadExResp 826393 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593404 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5593404 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214204160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214204160 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214204160 # Total data (bytes) +system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 49049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 49091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 49066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 49073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 49089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 49084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 49051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 49094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 49119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 49113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 49182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 49203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 49260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 49489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 49964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 50324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 52085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 51901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 51517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 52174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 2077885 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.053834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.951836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 184.653120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1660855 79.93% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 226890 10.92% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 69105 3.33% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 37676 1.81% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 25011 1.20% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 12112 0.58% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 8272 0.40% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 8103 0.39% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4494 0.22% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3425 0.16% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2747 0.13% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2032 0.10% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1669 0.08% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1441 0.07% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1240 0.06% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1051 0.05% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 987 0.05% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 902 0.04% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 711 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 682 0.03% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 694 0.03% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3096 0.15% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 406 0.02% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 291 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 190 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 185 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 205 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 473 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 132 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 131 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 122 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 122 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 103 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 129 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 90 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 83 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 94 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 68 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 57 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 64 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 70 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 60 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 55 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 48 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 43 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 58 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 55 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 43 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 33 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 30 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 32 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 24 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 28 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 19 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 34 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 24 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 26 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 14 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 24 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 24 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 21 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 13 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 15 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 21 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 20 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 13 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 16 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 16 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 27 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 36 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 16 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 187 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 12 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 9 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 9 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 34 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 26 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 4 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 4 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 83 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2077885 # Bytes accessed per row activation +system.physmem.totQLat 32824703500 # Total ticks spent queuing +system.physmem.totMemAccLat 104040704750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11228285000 # Total ticks spent in databus transfers +system.physmem.totBankLat 59987716250 # Total ticks spent accessing banks +system.physmem.avgQLat 14616.97 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26712.77 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 46329.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 269.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 131.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 269.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 131.98 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.08 # Average write queue length when enqueuing +system.physmem.readRowHits 931610 # Number of row buffer hits during reads +system.physmem.writeRowHits 336677 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes +system.physmem.avgGap 159462.71 # Average gap between requests +system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.89 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 401347580 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1419678 # Transaction distribution +system.membus.trans_dist::ReadResp 1419677 # Transaction distribution +system.membus.trans_dist::Writeback 1100533 # Transaction distribution +system.membus.trans_dist::ReadExReq 826593 # Transaction distribution +system.membus.trans_dist::ReadExResp 826593 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5593074 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214195392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214195392 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214195392 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12928469250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12924294750 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21152142500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 21079818750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.9 # Layer utilization (%) -system.cpu.branchPred.lookups 304298989 # Number of BP lookups -system.cpu.branchPred.condPredicted 250519406 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15198708 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 177303182 # Number of BTB lookups -system.cpu.branchPred.BTBHits 162516904 # Number of BTB hits +system.cpu.branchPred.lookups 303467870 # Number of BP lookups +system.cpu.branchPred.condPredicted 249715061 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15195903 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 175178105 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161776963 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.660455 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17540360 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 213 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.349990 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17540871 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 204 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -379,98 +381,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1083372854 # number of cpu cycles simulated +system.cpu.numCycles 1067381007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 300343787 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2195221955 # Number of instructions fetch has processed -system.cpu.fetch.Branches 304298989 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 180057264 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 436998042 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88977352 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 165479201 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 101 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 290623561 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6109702 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 973376815 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494162 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.204787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 299148062 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2189533318 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303467870 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179317834 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435752088 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88086251 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 164106751 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 339 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 289566494 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5997594 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 968963067 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.499628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.206367 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536378856 55.10% 55.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25841118 2.65% 57.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39079231 4.01% 61.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48353852 4.97% 66.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43959831 4.52% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46474608 4.77% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38397974 3.94% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19032697 1.96% 81.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175858648 18.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 533211067 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25485631 2.63% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39032754 4.03% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48282665 4.98% 66.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43767932 4.52% 71.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46382840 4.79% 75.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38389210 3.96% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18960850 1.96% 81.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175450118 18.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 973376815 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.280881 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.026285 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 332723748 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 143314435 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 406466996 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20316722 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70554914 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46046806 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 803 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2374638821 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2490 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70554914 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 356505375 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 71902909 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22171 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 401350772 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73040674 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2310606044 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 153145 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5003938 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60088597 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2286724696 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10669719595 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9782199775 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 333 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 968963067 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.284311 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.051314 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 331377153 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 141962670 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405350137 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20317948 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69955159 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46017147 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 694 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2369104960 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2426 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69955159 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354884990 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 70530339 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17935 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400511119 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73063525 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2306250708 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 150920 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5011927 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60136403 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282159345 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10649371145 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9763416611 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 460 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 580404766 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 862 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 859 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 161072397 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 625574992 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 221105439 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85703818 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70396970 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2205173654 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 876 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2020003765 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4023223 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 477517821 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1138229874 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 973376815 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.075254 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906645 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 575839415 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 404 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 401 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160989021 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624749088 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220784728 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85932352 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70842412 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2202316968 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 440 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018777354 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4015619 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 474672323 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1127531541 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 270 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 968963067 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.083441 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906294 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 290079957 29.80% 29.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153607537 15.78% 45.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161004232 16.54% 62.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120476061 12.38% 74.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123716545 12.71% 87.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73794754 7.58% 94.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38284776 3.93% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9892649 1.02% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2520304 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 286087063 29.53% 29.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153648666 15.86% 45.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160841319 16.60% 61.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120316001 12.42% 74.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123517924 12.75% 87.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73816539 7.62% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38325528 3.96% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9889728 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2520299 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 973376815 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 968963067 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 894925 3.74% 3.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5467 0.02% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 895423 3.74% 3.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5601 0.02% 3.76% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available @@ -498,118 +501,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18249723 76.22% 79.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4791929 20.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18274862 76.27% 80.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4786167 19.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1237561423 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 924895 0.05% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 588422338 29.13% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193095054 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236899038 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 924736 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 48 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587872837 29.12% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193080663 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2020003765 # Type of FU issued -system.cpu.iq.rate 1.864551 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23942044 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011852 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5041349349 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2682881596 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957831333 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 100 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2043945677 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64652125 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018777354 # Type of FU issued +system.cpu.iq.rate 1.891337 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23962053 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011870 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5034495136 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2677178912 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957310102 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 311 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 694 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 129 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042739250 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 157 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64569425 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 139648223 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 271348 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192348 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46258394 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138822319 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 268987 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192391 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45937683 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5367173 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4778132 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70554914 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 34630118 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1599053 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2205174629 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7647376 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 625574992 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 221105439 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 814 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 476287 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 97145 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192348 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8141918 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9600574 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17742492 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1989129664 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574576777 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30874101 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69955159 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33483642 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1603224 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2202317539 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7879544 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624749088 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220784728 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 378 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 478707 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97428 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192391 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8138332 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9600465 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17738797 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988042975 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574015030 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30734379 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 99 # number of nop insts executed -system.cpu.iew.exec_refs 764789002 # number of memory reference insts executed -system.cpu.iew.exec_branches 238317780 # Number of branches executed -system.cpu.iew.exec_stores 190212225 # Number of stores executed -system.cpu.iew.exec_rate 1.836053 # Inst execution rate -system.cpu.iew.wb_sent 1966244201 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957831433 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295814578 # num instructions producing a value -system.cpu.iew.wb_consumers 2059506895 # num instructions consuming a value +system.cpu.iew.exec_nop 131 # number of nop insts executed +system.cpu.iew.exec_refs 764217607 # number of memory reference insts executed +system.cpu.iew.exec_branches 238311346 # Number of branches executed +system.cpu.iew.exec_stores 190202577 # Number of stores executed +system.cpu.iew.exec_rate 1.862543 # Inst execution rate +system.cpu.iew.wb_sent 1965731650 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957310231 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295404026 # num instructions producing a value +system.cpu.iew.wb_consumers 2059270839 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.807163 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629187 # average fanout of values written-back +system.cpu.iew.wb_rate 1.833750 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629060 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 482200307 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 479343339 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15197938 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 902821901 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.908542 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.715709 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15195240 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 899007908 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.916639 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718451 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 414368116 45.90% 45.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193212165 21.40% 67.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72772864 8.06% 75.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35254508 3.90% 79.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18855841 2.09% 81.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30818249 3.41% 84.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19938130 2.21% 86.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11407177 1.26% 88.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106194851 11.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 410513863 45.66% 45.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193235979 21.49% 67.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72768373 8.09% 75.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35278706 3.92% 79.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18862057 2.10% 81.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30820454 3.43% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19957331 2.22% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11398634 1.27% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106172511 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 902821901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 899007908 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -620,212 +623,212 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106194851 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106172511 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3001900611 # The number of ROB reads -system.cpu.rob.rob_writes 4481254115 # The number of ROB writes -system.cpu.timesIdled 1150610 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 109996039 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2995251990 # The number of ROB reads +system.cpu.rob.rob_writes 4474939624 # The number of ROB writes +system.cpu.timesIdled 1152982 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 98417940 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.701411 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.701411 # CPI: Total CPI of All Threads -system.cpu.ipc 1.425698 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.425698 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9960721721 # number of integer regfile reads -system.cpu.int_regfile_writes 1937694107 # number of integer regfile writes -system.cpu.fp_regfile_reads 91 # number of floating regfile reads -system.cpu.fp_regfile_writes 89 # number of floating regfile writes -system.cpu.misc_regfile_reads 737621013 # number of misc regfile reads +system.cpu.cpi 0.691057 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.691057 # CPI: Total CPI of All Threads +system.cpu.ipc 1.447059 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.447059 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956212388 # number of integer regfile reads +system.cpu.int_regfile_writes 1937181821 # number of integer regfile writes +system.cpu.fp_regfile_reads 130 # number of floating regfile reads +system.cpu.fp_regfile_writes 139 # number of floating regfile writes +system.cpu.misc_regfile_reads 737624314 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1581534685 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7709688 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7709687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3782769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893417 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22987414 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22988978 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856645824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856695872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856695872 # Total data (bytes) +system.cpu.toL2Bus.throughput 1605146644 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7709082 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7709081 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3782685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893414 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22987676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856601984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856651520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856651520 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10475876330 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1321749 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10475431595 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1294249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14846430743 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14768966243 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) system.cpu.icache.tags.replacements 22 # number of replacements -system.cpu.icache.tags.tagsinuse 629.635316 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 290622345 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 371639.827366 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 628.527972 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289565308 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 774 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 374115.385013 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 629.635316 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.307439 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.307439 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 290622345 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 290622345 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 290622345 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 290622345 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 290622345 # number of overall hits -system.cpu.icache.overall_hits::total 290622345 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1216 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1216 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1216 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1216 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1216 # number of overall misses -system.cpu.icache.overall_misses::total 1216 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 85849749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 85849749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 85849749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 85849749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 85849749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 85849749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 290623561 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 290623561 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 290623561 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 290623561 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 290623561 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 290623561 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 628.527972 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306898 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306898 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 289565308 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289565308 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289565308 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289565308 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289565308 # number of overall hits +system.cpu.icache.overall_hits::total 289565308 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1186 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9602496 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965116 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184079 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184158 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965116 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.233868 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233927 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965116 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233868 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233927 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74940.763052 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88491.146378 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88484.016536 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92445.316498 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92445.316498 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89941.708488 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89941.708488 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -834,8 +837,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1100477 # number of writebacks -system.cpu.l2cache.writebacks::total 1100477 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1100533 # number of writebacks +system.cpu.l2cache.writebacks::total 1100533 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2246464 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 752 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2245712 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2246464 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48787000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 120499016750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120547803750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73852563750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73852563750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48787000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 194351580500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 194400367500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48787000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 194351580500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 194400367500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184114 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184193 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436456 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436456 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961637 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418932 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1419678 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826593 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 66030369000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46519250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173796976500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 173843495750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46519250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173796976500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 173843495750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184078 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184157 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233867 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233926 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233867 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233926 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62358.243968 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75949.099393 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75941.957789 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79882.564938 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79882.564938 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62358.243968 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77397.034769 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77392.040297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62358.243968 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77397.034769 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77392.040297 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9598226 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.205485 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 655929620 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9602322 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 68.309480 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3516509250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.205485 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998097 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998097 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 488969047 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 488969047 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166960447 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166960447 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 9597625 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.040332 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 656028832 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9601721 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 68.324088 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3547188250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.040332 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 489072771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489072771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166955934 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166955934 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 66 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 66 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 655929494 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 655929494 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 655929494 # number of overall hits -system.cpu.dcache.overall_hits::total 655929494 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11507818 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11507818 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5625600 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5625600 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656028705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656028705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656028705 # number of overall hits +system.cpu.dcache.overall_hits::total 656028705 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11514039 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11514039 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5630113 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5630113 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17133418 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17133418 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17133418 # number of overall misses -system.cpu.dcache.overall_misses::total 17133418 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 381897864985 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 381897864985 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 310946372440 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 310946372440 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 692844237425 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 692844237425 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 692844237425 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 692844237425 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500476865 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500476865 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17144152 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17144152 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17144152 # number of overall misses +system.cpu.dcache.overall_misses::total 17144152 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 363445631238 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 363445631238 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 307798034677 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 307798034677 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 225500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 671243665915 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 671243665915 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 671243665915 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 671243665915 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500586810 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500586810 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 69 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 69 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673062912 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673062912 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673062912 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673062912 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022994 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022994 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032596 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032596 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025456 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025456 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025456 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025456 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33185.949325 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33185.949325 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55273.459265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55273.459265 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40438.179786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40438.179786 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29551948 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3560628 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1217583 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.270993 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 54.667874 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673172857 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673172857 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673172857 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673172857 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023001 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023001 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032622 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032622 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025468 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025468 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025468 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025468 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31565.433402 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31565.433402 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54669.956833 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54669.956833 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39152.923161 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39152.923161 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24614592 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3988980 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1212230 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65133 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.305216 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.243609 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3782769 # number of writebacks -system.cpu.dcache.writebacks::total 3782769 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798912 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3798912 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732183 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3732183 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3782685 # number of writebacks +system.cpu.dcache.writebacks::total 3782685 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3805731 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3805731 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736699 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3736699 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7531095 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7531095 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7531095 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7531095 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708906 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708906 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893417 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893417 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9602323 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9602323 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9602323 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9602323 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210908812007 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 210908812007 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97317389015 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 97317389015 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308226201022 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 308226201022 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308226201022 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 308226201022 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7542430 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7542430 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7542430 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7542430 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708308 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708308 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893414 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893414 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601722 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601722 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601722 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601722 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198054864257 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 198054864257 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89469568032 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 89469568032 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287524432289 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 287524432289 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287524432289 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 287524432289 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014267 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014267 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27359.110619 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27359.110619 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51397.758135 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51397.758135 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25693.688454 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25693.688454 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47253.040292 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47253.040292 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 5350fe782..d049654a9 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041672 # Number of seconds simulated -sim_ticks 41671895000 # Number of ticks simulated -final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041680 # Number of seconds simulated +sim_ticks 41680207000 # Number of ticks simulated +final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101828 # Simulator instruction rate (inst/s) -host_op_rate 101828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46172411 # Simulator tick rate (ticks/s) -host_mem_usage 228672 # Number of bytes of host memory used -host_seconds 902.53 # Real time elapsed on the host +host_inst_rate 118687 # Simulator instruction rate (inst/s) +host_op_rate 118687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53827332 # Simulator tick rate (ticks/s) +host_mem_usage 260144 # Number of bytes of host memory used +host_seconds 774.33 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4291046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3292771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7583816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4291046 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4291046 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4938 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 4938 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 316032 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 499 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 209 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 212 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 265 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 423 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41671821000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 4938 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 4290190 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3292114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7582304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4290190 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4290190 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4290190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3292114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7582304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4938 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 316032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 316032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 443 # Per bank write bursts +system.physmem.perBankRdBursts::1 270 # Per bank write bursts +system.physmem.perBankRdBursts::2 295 # Per bank write bursts +system.physmem.perBankRdBursts::3 499 # Per bank write bursts +system.physmem.perBankRdBursts::4 209 # Per bank write bursts +system.physmem.perBankRdBursts::5 212 # Per bank write bursts +system.physmem.perBankRdBursts::6 207 # Per bank write bursts +system.physmem.perBankRdBursts::7 265 # Per bank write bursts +system.physmem.perBankRdBursts::8 219 # Per bank write bursts +system.physmem.perBankRdBursts::9 249 # Per bank write bursts +system.physmem.perBankRdBursts::10 238 # Per bank write bursts +system.physmem.perBankRdBursts::11 236 # Per bank write bursts +system.physmem.perBankRdBursts::12 379 # Per bank write bursts +system.physmem.perBankRdBursts::13 325 # Per bank write bursts +system.physmem.perBankRdBursts::14 469 # Per bank write bursts +system.physmem.perBankRdBursts::15 423 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 41680133000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 4938 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,92 +152,83 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 858.311111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 328.631203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1420.533351 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 87 24.17% 24.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 46 12.78% 36.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 36 10.00% 46.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 14 3.89% 50.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 20 5.56% 56.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 14 3.89% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 9 2.50% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 7 1.94% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 8 2.22% 66.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3 0.83% 67.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 8 2.22% 70.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 5 1.39% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 1.67% 73.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 7 1.94% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 1.11% 76.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 2 0.56% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 1.39% 78.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.28% 78.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.83% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 5 1.39% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.28% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.83% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 1.11% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.56% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.83% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.83% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.56% 85.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 4 1.11% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.28% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 4 1.11% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.56% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.83% 89.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.28% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.28% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.83% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 2 0.56% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.28% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.56% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.28% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 2 0.56% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.28% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.28% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.28% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.56% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.28% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.28% 95.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.28% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.28% 95.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.28% 95.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.56% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.28% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.28% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.28% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.28% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.28% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.28% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation -system.physmem.totQLat 20561250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 109587500 # Sum of mem lat for all requests -system.physmem.totBusLat 24690000 # Total cycles spent in databus access -system.physmem.totBankLat 64336250 # Total cycles spent in bank access -system.physmem.avgQLat 4163.88 # Average queueing delay per request -system.physmem.avgBankLat 13028.81 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22192.69 # Average memory access latency -system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 743 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 421.641992 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.527903 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 761.351186 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 254 34.19% 34.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 96 12.92% 47.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 62 8.34% 55.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 50 6.73% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 29 3.90% 66.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 32 4.31% 70.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 22 2.96% 73.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 25 3.36% 76.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 15 2.02% 78.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 12 1.62% 80.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 14 1.88% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 16 2.15% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 32 4.31% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 17 2.29% 90.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.67% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.67% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 8 1.08% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 5 0.67% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 6 0.81% 94.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 6 0.81% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.27% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.13% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.13% 96.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.40% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 2 0.27% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.13% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.27% 97.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.27% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.13% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.13% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.13% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.13% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.13% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.13% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.13% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.13% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.13% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.13% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.13% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.13% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.13% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation +system.physmem.totQLat 34068750 # Total ticks spent queuing +system.physmem.totMemAccLat 126422500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers +system.physmem.totBankLat 67663750 # Total ticks spent accessing banks +system.physmem.avgQLat 6899.30 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25601.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4578 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4195 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.95 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8439007.90 # Average gap between requests -system.membus.throughput 7583816 # Throughput (bytes/s) +system.physmem.avgGap 8440691.17 # Average gap between requests +system.physmem.pageHitRate 84.95 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.90 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 7582304 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution @@ -246,9 +239,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46068500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 45976500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.branchPred.lookups 13412627 # Number of BP lookups system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted @@ -263,22 +256,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996270 # DTB read hits +system.cpu.dtb.read_hits 19996265 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996280 # DTB read accesses -system.cpu.dtb.write_hits 6501863 # DTB write hits +system.cpu.dtb.read_accesses 19996275 # DTB read accesses +system.cpu.dtb.write_hits 6501862 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501886 # DTB write accesses -system.cpu.dtb.data_hits 26498133 # DTB hits +system.cpu.dtb.write_accesses 6501885 # DTB write accesses +system.cpu.dtb.data_hits 26498127 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498166 # DTB accesses -system.cpu.itb.fetch_hits 9956949 # ITB hits +system.cpu.dtb.data_accesses 26498160 # DTB accesses +system.cpu.itb.fetch_hits 9956950 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9956998 # ITB accesses +system.cpu.itb.fetch_accesses 9956999 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,17 +285,17 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83343791 # number of cpu cycles simulated +system.cpu.numCycles 83360415 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570550 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 73570552 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146022 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206131 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136146024 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058019 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 26722393 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. @@ -310,16 +303,16 @@ system.cpu.execution_unit.predictedNotTakenIncorrect 799060 system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57404028 # Number of Instructions Executed. +system.cpu.execution_unit.executions 57404027 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82970405 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10389 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7736037 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607754 # Number of cycles cpu stages are processed. -system.cpu.activity 90.717920 # Percentage of cycles cpu is active +system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7752656 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607759 # Number of cycles cpu stages are processed. +system.cpu.activity 90.699835 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -331,72 +324,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.906866 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.907047 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.906866 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102698 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.907047 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102478 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.102698 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27663446 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680345 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.808030 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34092107 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.094605 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33492443 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.102478 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27680069 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680346 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.794708 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34108732 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251683 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.082819 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33509067 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.814111 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65317278 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026513 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.629101 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29484037 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859754 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.623595 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.utilization 59.802183 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29500659 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859756 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.610710 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 7635 # number of replacements -system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.182806 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728605 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits system.cpu.icache.overall_hits::total 9945551 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11398 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11398 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11398 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11398 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11398 # number of overall misses -system.cpu.icache.overall_misses::total 11398 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 318279500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 318279500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 318279500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 318279500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 318279500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 318279500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9956949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9956949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9956949 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9956949 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9956949 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9956949 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 11399 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11399 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11399 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses +system.cpu.icache.overall_misses::total 11399 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 325867750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 325867750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 325867750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 325867750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 325867750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 325867750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9956950 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27924.153360 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27924.153360 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27924.153360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27924.153360 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.398017 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28587.398017 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28587.398017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28587.398017 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -405,38 +398,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1878 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1878 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1878 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1878 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1878 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1878 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 259449500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 259449500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 259449500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 259449500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 259449500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 259449500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266340500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 266340500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266340500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 266340500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266340500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 266340500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27253.098739 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27253.098739 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.943277 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.943277 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 18199316 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -452,23 +445,23 @@ system.cpu.toL2Bus.data_through_bus 758400 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 14868500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 14812000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3600000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3559500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2189.714615 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2189.577948 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.843770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.865070 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.005775 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.842967 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.748644 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986337 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.066825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.066821 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits @@ -493,17 +486,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 182392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29940500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 212332500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 115205000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 182392000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 145145500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 327537500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 182392000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 145145500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 327537500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189283000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 221678250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122427250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 122427250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 189283000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 154822500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 344105500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 189283000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 154822500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 344105500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -528,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65279.885469 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70949.052133 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66023.787313 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66901.858304 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66901.858304 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66329.991900 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66329.991900 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67746.241947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.804104 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.963995 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.963995 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69685.196436 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69685.196436 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -558,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 147140500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24615500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171756000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94045000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94045000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 147140500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118660500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 265801000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 147140500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118660500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 265801000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 282558000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282558000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -580,51 +573,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52663.027917 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58330.568720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53406.716418 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.821138 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.821138 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.702671 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.702671 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1441.367779 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492886 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492886 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488508 # number of overall hits -system.cpu.dcache.overall_hits::total 26488508 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 576 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 576 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8217 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8217 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8793 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8793 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8793 # number of overall misses -system.cpu.dcache.overall_misses::total 8793 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38176750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38176750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 468176250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 468176250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 506353000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 506353000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 506353000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 506353000 # number of overall miss cycles +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367779 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492829 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492829 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488450 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488450 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488450 # number of overall hits +system.cpu.dcache.overall_hits::total 26488450 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8274 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8274 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8851 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses +system.cpu.dcache.overall_misses::total 8851 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41022750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41022750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 492651500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 492651500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 533674250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 533674250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 533674250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 533674250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -635,38 +628,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001264 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001264 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000332 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000332 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000332 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000332 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66279.079861 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66279.079861 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56976.542534 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56976.542534 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57585.920619 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57585.920619 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22475 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001273 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001273 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71096.620451 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71096.620451 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59542.119894 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59542.119894 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60295.362106 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60295.362106 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23885 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 847 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.534829 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.400713 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6570 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6570 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6570 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6570 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6526 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6526 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6628 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6628 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6628 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6628 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -675,14 +668,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117222500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 117222500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 148186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 148186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 148186500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 148186500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124444750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 124444750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157863500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 157863500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157863500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 157863500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -691,14 +684,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65187.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65187.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67060.926773 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67060.926773 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71192.648741 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71192.648741 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 758c8228e..1aa820757 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,96 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023492 # Number of seconds simulated -sim_ticks 23492267500 # Number of ticks simulated -final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023462 # Number of seconds simulated +sim_ticks 23461709500 # Number of ticks simulated +final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158745 # Simulator instruction rate (inst/s) -host_op_rate 158745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44301493 # Simulator tick rate (ticks/s) -host_mem_usage 233720 # Number of bytes of host memory used -host_seconds 530.28 # Real time elapsed on the host +host_inst_rate 165875 # Simulator instruction rate (inst/s) +host_op_rate 165875 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46230980 # Simulator tick rate (ticks/s) +host_mem_usage 261164 # Number of bytes of host memory used +host_seconds 507.49 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 334464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8339084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5898111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14237195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8339084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8339084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8339084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5898111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14237195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5226 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 5226 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 334464 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 334464 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 252 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 398 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 491 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 446 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23492140500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5226 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory +system.physmem.bytes_read::total 334592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8352674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5908521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14261194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8352674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8352674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8352674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5908521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14261194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5228 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 466 # Per bank write bursts +system.physmem.perBankRdBursts::1 290 # Per bank write bursts +system.physmem.perBankRdBursts::2 300 # Per bank write bursts +system.physmem.perBankRdBursts::3 524 # Per bank write bursts +system.physmem.perBankRdBursts::4 220 # Per bank write bursts +system.physmem.perBankRdBursts::5 226 # Per bank write bursts +system.physmem.perBankRdBursts::6 219 # Per bank write bursts +system.physmem.perBankRdBursts::7 288 # Per bank write bursts +system.physmem.perBankRdBursts::8 240 # Per bank write bursts +system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::10 248 # Per bank write bursts +system.physmem.perBankRdBursts::11 254 # Per bank write bursts +system.physmem.perBankRdBursts::12 400 # Per bank write bursts +system.physmem.perBankRdBursts::13 336 # Per bank write bursts +system.physmem.perBankRdBursts::14 491 # Per bank write bursts +system.physmem.perBankRdBursts::15 447 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 23461582500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5228 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,135 +152,127 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 780.923077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 283.989164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1375.157964 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 120 28.85% 28.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 59 14.18% 43.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 37 8.89% 51.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 19 4.57% 56.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16 3.85% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 20 4.81% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8 1.92% 67.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 8 1.92% 68.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 1.20% 70.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 5 1.20% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 6 1.44% 72.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 8 1.92% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 1.44% 76.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 4 0.96% 77.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.96% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 2 0.48% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 1.20% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 4 0.96% 83.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.72% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.72% 85.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.96% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 4 0.96% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.48% 90.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.24% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.48% 91.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.24% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.48% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.24% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.24% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 5 1.20% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.24% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.24% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.24% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.48% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 4 0.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 416 # Bytes accessed per row activation -system.physmem.totQLat 21308250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 115583250 # Sum of mem lat for all requests -system.physmem.totBusLat 26130000 # Total cycles spent in databus access -system.physmem.totBankLat 68145000 # Total cycles spent in bank access -system.physmem.avgQLat 4077.35 # Average queueing delay per request -system.physmem.avgBankLat 13039.61 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22116.96 # Average memory access latency -system.physmem.avgRdBW 14.24 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.24 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 750 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 442.026667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 206.409345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 807.667918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 266 35.47% 35.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 111 14.80% 50.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 59 7.87% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 40 5.33% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 26 3.47% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 30 4.00% 70.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 24 3.20% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 16 2.13% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.20% 77.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 13 1.73% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 15 2.00% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 13 1.73% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 37 4.93% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 11 1.47% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 0.80% 90.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.40% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 7 0.93% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 7 0.93% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.40% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.40% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 8 1.07% 94.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.13% 94.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3 0.40% 94.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.27% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 4 0.53% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 2 0.27% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.13% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.13% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.40% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.40% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.40% 97.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.13% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.13% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 3 0.40% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.13% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 2 0.27% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.13% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.13% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.13% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.13% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.13% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.13% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.13% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.27% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 750 # Bytes accessed per row activation +system.physmem.totQLat 37518250 # Total ticks spent queuing +system.physmem.totMemAccLat 134402000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers +system.physmem.totBankLat 70743750 # Total ticks spent accessing banks +system.physmem.avgQLat 7176.41 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13531.70 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25708.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.11 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4810 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4478 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.04 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4495243.11 # Average gap between requests -system.membus.throughput 14237195 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3520 # Transaction distribution -system.membus.trans_dist::ReadResp 3520 # Transaction distribution -system.membus.trans_dist::ReadExReq 1706 # Transaction distribution -system.membus.trans_dist::ReadExResp 1706 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334464 # Total data (bytes) +system.physmem.avgGap 4487678.37 # Average gap between requests +system.physmem.pageHitRate 85.65 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.19 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 14261194 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3523 # Transaction distribution +system.membus.trans_dist::ReadResp 3523 # Transaction distribution +system.membus.trans_dist::ReadExReq 1705 # Transaction distribution +system.membus.trans_dist::ReadExResp 1705 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6824500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49069500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49013750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.branchPred.lookups 14868892 # Number of BP lookups -system.cpu.branchPred.condPredicted 10787177 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 926932 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8430316 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6969924 # Number of BTB hits +system.cpu.branchPred.lookups 14847721 # Number of BP lookups +system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8301784 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6957683 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.676901 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1469870 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3126 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.809492 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1467978 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3097 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23134581 # DTB read hits -system.cpu.dtb.read_misses 192685 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23327266 # DTB read accesses -system.cpu.dtb.write_hits 7072669 # DTB write hits -system.cpu.dtb.write_misses 1128 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 7073797 # DTB write accesses -system.cpu.dtb.data_hits 30207250 # DTB hits -system.cpu.dtb.data_misses 193813 # DTB misses -system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 30401063 # DTB accesses -system.cpu.itb.fetch_hits 14756036 # ITB hits -system.cpu.itb.fetch_misses 101 # ITB misses +system.cpu.dtb.read_hits 23117785 # DTB read hits +system.cpu.dtb.read_misses 192281 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 23310066 # DTB read accesses +system.cpu.dtb.write_hits 7068175 # DTB write hits +system.cpu.dtb.write_misses 1137 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7069312 # DTB write accesses +system.cpu.dtb.data_hits 30185960 # DTB hits +system.cpu.dtb.data_misses 193418 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 30379378 # DTB accesses +system.cpu.itb.fetch_hits 14734161 # ITB hits +system.cpu.itb.fetch_misses 103 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14756137 # ITB accesses +system.cpu.itb.fetch_accesses 14734264 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,237 +286,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46984536 # number of cpu cycles simulated +system.cpu.numCycles 46923420 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15488073 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127117981 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14868892 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8439794 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22159630 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4494895 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5563054 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2312 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14756036 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 325999 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46746670 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.719295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.375691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15463377 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 126961895 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14847721 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8425661 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22130057 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4473004 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5559399 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2205 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14734161 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 324640 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.720324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376096 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24587040 52.60% 52.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2365337 5.06% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1191741 2.55% 60.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1747442 3.74% 63.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2760154 5.90% 69.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1154764 2.47% 72.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1218466 2.61% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 772204 1.65% 76.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10949522 23.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24541545 52.58% 52.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2361252 5.06% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1192515 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1742111 3.73% 63.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2755702 5.90% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1149393 2.46% 72.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1220691 2.62% 74.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 771783 1.65% 76.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10936610 23.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46746670 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705528 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17316199 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4260248 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20549941 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1098483 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3521799 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2517933 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12169 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 124122749 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32253 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3521799 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18461305 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 962240 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7648 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20480612 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3313066 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121283530 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 398899 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2436739 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89066471 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157595093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150534218 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7060874 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316425 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.705726 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17289391 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4257221 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20524695 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1095542 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3504753 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2511898 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12165 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123979131 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31595 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3504753 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18431775 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 963421 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7928 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20455401 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3308324 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121154586 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 400162 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2430153 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 88974234 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157440436 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 150394666 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7045769 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20639110 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 733 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 729 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8785388 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25392018 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8252125 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2596537 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 925406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105547434 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2098 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96644788 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 177437 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20878127 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15672265 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1709 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46746670 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.067415 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876261 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20546873 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 749 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 744 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8783261 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25363135 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8241350 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2569635 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 893782 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105438340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 961 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96565073 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178504 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20784584 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15622472 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46671602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.069033 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876517 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12170136 26.03% 26.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9358863 20.02% 46.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8416132 18.00% 64.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6289434 13.45% 77.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4916374 10.52% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2864607 6.13% 94.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1727461 3.70% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 797242 1.71% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 206421 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12133901 26.00% 26.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9340973 20.01% 46.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8404137 18.01% 64.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6285068 13.47% 77.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4921134 10.54% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2853572 6.11% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1727806 3.70% 97.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 798698 1.71% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 206313 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46746670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46671602 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 188535 12.02% 12.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 207 0.01% 12.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7191 0.46% 12.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5653 0.36% 12.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842893 53.74% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 446132 28.45% 95.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77750 4.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 187905 11.99% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 198 0.01% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7114 0.45% 12.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5683 0.36% 12.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843073 53.81% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 444038 28.34% 94.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78699 5.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58781922 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479844 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58732394 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479878 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2799901 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115380 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387749 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311051 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760106 0.79% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23852037 24.68% 92.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7156472 7.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2798409 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115272 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387143 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 310920 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760028 0.79% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23829441 24.68% 92.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7151262 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96644788 # Type of FU issued -system.cpu.iq.rate 2.056949 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568361 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016228 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226659796 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117693658 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87130802 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15122248 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8768674 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7065649 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90221948 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7991194 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1517986 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96565073 # Type of FU issued +system.cpu.iq.rate 2.057929 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1566710 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016224 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226434514 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117518312 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87069210 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15112448 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8740080 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7062492 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90145383 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7986393 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1518186 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5395820 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18680 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34810 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1751022 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5366937 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18425 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34629 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1740247 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10535 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1932 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10551 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2023 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3521799 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133427 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18321 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115791419 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 375079 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25392018 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8252125 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2098 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2892 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34810 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 537595 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 497018 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034613 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95405393 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23327731 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1239395 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3504753 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133474 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18356 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115674273 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 366324 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25363135 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8241350 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 961 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34629 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 535207 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 494157 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1029364 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95337689 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23310553 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1227384 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10241887 # number of nop insts executed -system.cpu.iew.exec_refs 30401730 # number of memory reference insts executed -system.cpu.iew.exec_branches 12031007 # Number of branches executed -system.cpu.iew.exec_stores 7073999 # Number of stores executed -system.cpu.iew.exec_rate 2.030570 # Inst execution rate -system.cpu.iew.wb_sent 94717591 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94196451 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64508240 # num instructions producing a value -system.cpu.iew.wb_consumers 89892394 # num instructions consuming a value +system.cpu.iew.exec_nop 10234972 # number of nop insts executed +system.cpu.iew.exec_refs 30380075 # number of memory reference insts executed +system.cpu.iew.exec_branches 12022158 # Number of branches executed +system.cpu.iew.exec_stores 7069522 # Number of stores executed +system.cpu.iew.exec_rate 2.031772 # Inst execution rate +system.cpu.iew.wb_sent 94652013 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94131702 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64474348 # num instructions producing a value +system.cpu.iew.wb_consumers 89850693 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.004839 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717616 # average fanout of values written-back +system.cpu.iew.wb_rate 2.006071 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717572 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23889448 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23772324 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 915179 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43224871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.126161 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.744271 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 910471 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43166849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.129019 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.746086 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16760873 38.78% 38.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9929358 22.97% 61.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4485318 10.38% 72.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2262602 5.23% 77.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1610546 3.73% 81.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1125217 2.60% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 721883 1.67% 85.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 816904 1.89% 87.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5512170 12.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16723467 38.74% 38.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9908467 22.95% 61.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4486822 10.39% 72.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2263317 5.24% 77.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1605459 3.72% 81.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1122723 2.60% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 719573 1.67% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818064 1.90% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5518957 12.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43224871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43166849 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -533,212 +528,212 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5512170 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5518957 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153504164 # The number of ROB reads -system.cpu.rob.rob_writes 235130535 # The number of ROB writes -system.cpu.timesIdled 5262 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 237866 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153322231 # The number of ROB reads +system.cpu.rob.rob_writes 234879486 # The number of ROB writes +system.cpu.timesIdled 5401 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 251818 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.558146 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.558146 # CPI: Total CPI of All Threads -system.cpu.ipc 1.791647 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.791647 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129142322 # number of integer regfile reads -system.cpu.int_regfile_writes 70569523 # number of integer regfile writes -system.cpu.fp_regfile_reads 6189856 # number of floating regfile reads -system.cpu.fp_regfile_writes 6047601 # number of floating regfile writes -system.cpu.misc_regfile_reads 714537 # number of misc regfile reads +system.cpu.cpi 0.557420 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.557420 # CPI: Total CPI of All Threads +system.cpu.ipc 1.793981 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.793981 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129048096 # number of integer regfile reads +system.cpu.int_regfile_writes 70519804 # number of integer regfile writes +system.cpu.fp_regfile_reads 6188545 # number of floating regfile reads +system.cpu.fp_regfile_writes 6044303 # number of floating regfile writes +system.cpu.misc_regfile_reads 714547 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37717943 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 12006 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12006 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution +system.cpu.toL2Bus.throughput 37824354 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12026 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12026 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4598 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 735488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 886080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 886080 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27623 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 736640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7030500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 7042000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17871250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17847250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3590750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3547000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9559 # number of replacements -system.cpu.icache.tags.tagsinuse 1595.799290 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14741729 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11492 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1282.781848 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9576 # number of replacements +system.cpu.icache.tags.tagsinuse 1596.482982 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14719875 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1278.877063 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1595.799290 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.779199 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.779199 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14741729 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14741729 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14741729 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14741729 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14741729 # number of overall hits -system.cpu.icache.overall_hits::total 14741729 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14307 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14307 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14307 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14307 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14307 # number of overall misses -system.cpu.icache.overall_misses::total 14307 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 399491250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 399491250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 399491250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 399491250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 399491250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 399491250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14756036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14756036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14756036 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14756036 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14756036 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14756036 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482982 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14719875 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14719875 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14719875 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14719875 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14719875 # number of overall hits +system.cpu.icache.overall_hits::total 14719875 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14285 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14285 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14285 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14285 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14285 # number of overall misses +system.cpu.icache.overall_misses::total 14285 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413142250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413142250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413142250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413142250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413142250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413142250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14734160 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14734160 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14734160 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14734160 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14734160 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14734160 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000970 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000970 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27922.782554 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27922.782554 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27922.782554 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27922.782554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27922.782554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27922.782554 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28921.403570 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28921.403570 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28921.403570 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28921.403570 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2815 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2815 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2815 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2815 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2815 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2815 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11492 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11492 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11492 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11492 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11492 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11492 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 295512250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 295512250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 295512250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 295512250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 295512250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 295512250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000779 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000779 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25714.605813 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25714.605813 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25714.605813 # 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number of replacements -system.cpu.dcache.tags.tagsinuse 1457.925933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28096273 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12515.043653 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 159 # number of replacements +system.cpu.dcache.tags.tagsinuse 1459.152637 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28079168 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12496.291945 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.925933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355939 # 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average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58069.964321 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58069.964321 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 265 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 265 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28088112 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28088112 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28088112 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28088112 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001267 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001267 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003774 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003774 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.739220 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.739220 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.142701 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.142701 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58371.852935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58371.852935 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21919 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61262.548328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61262.548328 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.235119 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.583333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108 # number of writebacks -system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 475 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 475 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6481 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6481 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6956 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6956 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6956 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6956 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 109 # number of writebacks +system.cpu.dcache.writebacks::total 109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 459 # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151285747 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161992997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161992997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161992997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161992997 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004219 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003774 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003774 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68259.746589 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68259.746589 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67168.398036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67168.398036 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.980583 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.980583 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73044.770075 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73044.770075 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a815317b1..4425c72f1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,96 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074201 # Number of seconds simulated -sim_ticks 74201024500 # Number of ticks simulated -final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074220 # Number of seconds simulated +sim_ticks 74219948500 # Number of ticks simulated +final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115322 # Simulator instruction rate (inst/s) -host_op_rate 126267 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49662501 # Simulator tick rate (ticks/s) -host_mem_usage 251448 # Number of bytes of host memory used -host_seconds 1494.11 # Real time elapsed on the host +host_inst_rate 110839 # Simulator instruction rate (inst/s) +host_op_rate 121359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47744278 # Simulator tick rate (ticks/s) +host_mem_usage 278976 # Number of bytes of host memory used +host_seconds 1554.53 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111872 # Number of bytes read from this memory -system.physmem.bytes_read::total 243200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131328 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1748 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3800 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1769895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1507688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3277583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1769895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1769895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3801 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 3801 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 243200 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 298 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 261 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 216 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 191 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 200 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74201006000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3801 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory +system.physmem.bytes_read::total 242752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1765994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3270711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1765994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1765994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1765994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3270711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3794 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 242816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 242816 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 306 # Per bank write bursts +system.physmem.perBankRdBursts::1 215 # Per bank write bursts +system.physmem.perBankRdBursts::2 133 # Per bank write bursts +system.physmem.perBankRdBursts::3 308 # Per bank write bursts +system.physmem.perBankRdBursts::4 298 # Per bank write bursts +system.physmem.perBankRdBursts::5 299 # Per bank write bursts +system.physmem.perBankRdBursts::6 264 # Per bank write bursts +system.physmem.perBankRdBursts::7 216 # Per bank write bursts +system.physmem.perBankRdBursts::8 246 # Per bank write bursts +system.physmem.perBankRdBursts::9 215 # Per bank write bursts +system.physmem.perBankRdBursts::10 289 # Per bank write bursts +system.physmem.perBankRdBursts::11 193 # Per bank write bursts +system.physmem.perBankRdBursts::12 189 # Per bank write bursts +system.physmem.perBankRdBursts::13 206 # Per bank write bursts +system.physmem.perBankRdBursts::14 217 # Per bank write bursts +system.physmem.perBankRdBursts::15 200 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 74219930000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 3794 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,114 +152,100 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 389 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 616.966581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.267348 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1216.553816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 139 35.73% 35.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 59 15.17% 50.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 33 8.48% 59.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 24 6.17% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15 3.86% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 13 3.34% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 4 1.03% 73.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 7 1.80% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 1.29% 76.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 8 2.06% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 1.03% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 1.03% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.77% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 3 0.77% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 1.29% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 4 1.03% 84.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 1.03% 85.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.26% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 1 0.26% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.77% 87.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.77% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.77% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 2 0.51% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.26% 89.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.77% 90.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.77% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.26% 91.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.26% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.26% 91.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.26% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.51% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.26% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.26% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.26% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.26% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.26% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.26% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.26% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.26% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.26% 94.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.26% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.26% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 4 1.03% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.26% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.26% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.26% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.26% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.26% 97.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.26% 97.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 1 0.26% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.26% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.26% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.26% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.26% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.26% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 389 # Bytes accessed per row activation -system.physmem.totQLat 12962000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 86183250 # Sum of mem lat for all requests -system.physmem.totBusLat 19005000 # Total cycles spent in databus access -system.physmem.totBankLat 54216250 # Total cycles spent in bank access -system.physmem.avgQLat 3410.16 # Average queueing delay per request -system.physmem.avgBankLat 14263.68 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22673.84 # Average memory access latency -system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 334.192469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.652659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 576.534776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 257 35.84% 35.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 120 16.74% 52.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 71 9.90% 62.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 49 6.83% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 19 2.65% 71.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 26 3.63% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 20 2.79% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 17 2.37% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 17 2.37% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 40 5.58% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 17 2.37% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 0.84% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 0.84% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 1.12% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 0.84% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.70% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 4 0.56% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1 0.14% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.28% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.28% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.28% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2 0.28% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.14% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.14% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.14% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.14% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.14% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.28% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.14% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.28% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.14% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.14% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.14% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation +system.physmem.totQLat 25205500 # Total ticks spent queuing +system.physmem.totMemAccLat 100715500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers +system.physmem.totBankLat 56540000 # Total ticks spent accessing banks +system.physmem.avgQLat 6643.52 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26545.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3412 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 3077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19521443.30 # Average gap between requests -system.membus.throughput 3277583 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2726 # Transaction distribution -system.membus.trans_dist::ReadResp 2725 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 1075 # Transaction distribution -system.membus.trans_dist::ReadExResp 1075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7605 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 243200 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 243200 # Total data (bytes) +system.physmem.avgGap 19562448.60 # Average gap between requests +system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 3270711 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2723 # Transaction distribution +system.membus.trans_dist::ReadResp 2722 # Transaction distribution +system.membus.trans_dist::ReadExReq 1071 # Transaction distribution +system.membus.trans_dist::ReadExResp 1071 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 242752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4683500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35707998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35533250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 94803777 # Number of BP lookups -system.cpu.branchPred.condPredicted 74793629 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6279390 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44652033 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43049215 # Number of BTB hits +system.cpu.branchPred.lookups 94784279 # Number of BP lookups +system.cpu.branchPred.condPredicted 74784012 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44678427 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.410425 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4355984 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88442 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.355268 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4356637 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -301,135 +289,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148402050 # number of cpu cycles simulated +system.cpu.numCycles 148439898 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39645282 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380210735 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94803777 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47405199 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80366135 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27283939 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7211893 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5835 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39656913 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380179952 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94784279 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47406655 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80370667 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27283129 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7220970 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 74 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36839707 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1829204 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148218142 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36850892 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68020669 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5263809 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10529342 7.10% 56.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10284383 6.94% 63.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8663442 5.85% 69.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6544357 4.42% 73.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6237651 4.21% 77.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8018779 5.41% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24655710 16.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68038754 45.90% 45.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10540667 7.11% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6545128 4.42% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8002829 5.40% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24655178 16.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148218142 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638831 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.562032 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45496346 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5881053 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74801402 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1203851 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20835490 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14335605 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164633 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392823460 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 736203 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20835490 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50883815 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 724795 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 600466 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70555670 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4617906 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371356593 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 28 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 342994 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3662384 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631760398 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581883462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1507069248 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3196133 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45513789 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5886753 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74804125 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20832415 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14327913 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392779898 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20832415 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50900742 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 603190 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70558310 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4615219 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371308094 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 339277 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631703486 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581699955 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506871299 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333716259 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25188 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25185 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13032916 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43019038 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16425001 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5693552 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3686945 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329243417 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249464214 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 795417 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139561180 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362246737 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148218142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683088 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761802 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 333659347 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43012685 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329190158 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249456619 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 789371 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139503403 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362002811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148240575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56048230 37.81% 37.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22642926 15.28% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24814212 16.74% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20312337 13.70% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12552656 8.47% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6518158 4.40% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4033272 2.72% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1116001 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 180350 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56059831 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24824163 16.75% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12534795 8.46% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4026097 2.72% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148218142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148240575 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 965237 38.47% 38.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5595 0.22% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1168121 46.56% 85.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 370007 14.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1158967 46.31% 85.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194903493 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979289 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194899965 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued @@ -448,93 +436,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33083 0.01% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164442 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254821 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76413 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465720 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33082 0.01% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164367 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255141 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76420 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38359883 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13948512 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249464214 # Type of FU issued -system.cpu.iq.rate 1.681002 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2509108 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010058 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646714008 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466681926 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237887502 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3737087 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2188015 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1841410 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250098110 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1875212 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2005238 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249456619 # Type of FU issued +system.cpu.iq.rate 1.680523 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646705831 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466563436 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250082854 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13169554 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11470 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18663 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3780367 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13163201 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 113 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20835490 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18710 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 879 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329307607 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 785363 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43019038 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16425001 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 275 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18663 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3889158 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3759638 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7648796 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242968769 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36856935 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6495445 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20832415 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329254508 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43012685 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3889958 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3760086 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6496100 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 16987 # number of nop insts executed -system.cpu.iew.exec_refs 50502724 # number of memory reference insts executed -system.cpu.iew.exec_branches 53433142 # Number of branches executed -system.cpu.iew.exec_stores 13645789 # Number of stores executed -system.cpu.iew.exec_rate 1.637233 # Inst execution rate -system.cpu.iew.wb_sent 240789077 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239728912 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148477198 # num instructions producing a value -system.cpu.iew.wb_consumers 267296630 # num instructions consuming a value +system.cpu.iew.exec_nop 17196 # number of nop insts executed +system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed +system.cpu.iew.exec_branches 53426072 # Number of branches executed +system.cpu.iew.exec_stores 13648456 # Number of stores executed +system.cpu.iew.exec_rate 1.636760 # Inst execution rate +system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148474079 # num instructions producing a value +system.cpu.iew.wb_consumers 267261472 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615402 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555477 # average fanout of values written-back +system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140636703 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140583620 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6125970 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127382652 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481135 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.185870 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127408160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57681624 45.28% 45.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31696418 24.88% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13781439 10.82% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7634613 5.99% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4380226 3.44% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1319827 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1706186 1.34% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1307951 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7874368 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57701826 45.29% 45.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31696936 24.88% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13777779 10.81% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7640619 6.00% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1308014 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127382652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127408160 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -545,220 +533,212 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7874368 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448810677 # The number of ROB reads -system.cpu.rob.rob_writes 679560182 # The number of ROB writes -system.cpu.timesIdled 2800 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 183908 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448787441 # The number of ROB reads +system.cpu.rob.rob_writes 679451137 # The number of ROB writes +system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199323 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.861285 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861285 # CPI: Total CPI of All Threads -system.cpu.ipc 1.161056 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.161056 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079439367 # number of integer regfile reads -system.cpu.int_regfile_writes 384873719 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913212 # number of floating regfile reads -system.cpu.fp_regfile_writes 2497494 # number of floating regfile writes -system.cpu.misc_regfile_reads 54494427 # number of misc regfile reads +system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads +system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079417004 # number of integer regfile reads +system.cpu.int_regfile_writes 384871783 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads +system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes +system.cpu.misc_regfile_reads 54501288 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5172543 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4897 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4896 # Transaction distribution +system.cpu.toL2Bus.throughput 5169500 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4898 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8247 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3732 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11979 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8251 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11973 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3016000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6609745 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6552496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3106490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3047739 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2391 # number of replacements -system.cpu.icache.tags.tagsinuse 1346.456608 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36834377 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2394 # number of replacements +system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36845555 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8932.255758 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.657450 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36834377 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36834377 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36834377 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36834377 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36834377 # number of overall hits -system.cpu.icache.overall_hits::total 36834377 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5330 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5330 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5330 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5330 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5330 # number of overall misses -system.cpu.icache.overall_misses::total 5330 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 215954243 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 215954243 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 215954243 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 215954243 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 215954243 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 215954243 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36839707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36839707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36839707 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36839707 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36839707 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36839707 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36845555 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36845555 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36845555 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36845555 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36845555 # number of overall hits +system.cpu.icache.overall_hits::total 36845555 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses +system.cpu.icache.overall_misses::total 5337 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 225944745 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 225944745 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 225944745 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 225944745 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 225944745 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 225944745 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36850892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36850892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36850892 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36850892 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36850892 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36850892 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40516.743527 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40516.743527 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40516.743527 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40516.743527 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1739 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42335.534008 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42335.534008 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42335.534008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42335.534008 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 82.809524 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1205 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1205 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1205 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1205 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1205 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1205 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4125 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4125 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4125 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4125 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4125 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4125 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 162387254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 162387254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 162387254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 162387254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 162387254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 162387254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4126 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4126 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4126 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168091004 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168091004 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168091004 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168091004 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168091004 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168091004 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39366.607030 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39366.607030 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40739.458071 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40739.458071 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1961.044100 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2153 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2735 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.787203 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1967.449765 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4.994051 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1423.034105 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 533.015945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569688 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043428 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.059846 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2065 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2152 # number of ReadReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.060042 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2073 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 88 # 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average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1404.261851 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46798452 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1855 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25228.276011 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46786156 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25262.503240 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1404.261851 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.342837 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34397014 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34397014 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22472 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22472 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34384711 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34384711 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46753571 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46753571 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46753571 # number of overall hits -system.cpu.dcache.overall_hits::total 46753571 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1913 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1913 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46741275 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46741275 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46741275 # number of overall hits +system.cpu.dcache.overall_hits::total 46741275 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1902 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1902 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9643 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9643 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9643 # number of overall misses -system.cpu.dcache.overall_misses::total 9643 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114314976 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114314976 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 447415748 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 447415748 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9625 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses +system.cpu.dcache.overall_misses::total 9625 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 121870727 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 121870727 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623246 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 465623246 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 561730724 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 561730724 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 561730724 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 561730724 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34398927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34398927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 587493973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 587493973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 587493973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 587493973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22474 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46763214 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46763214 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46763214 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46763214 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 46750900 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46750900 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46750900 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46750900 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses @@ -892,68 +864,68 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59756.913748 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59756.913748 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57880.433118 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57880.433118 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64075.040484 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64075.040484 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.463033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.463033 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58252.693560 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58252.693560 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 154 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61038.334857 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61038.334857 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.272727 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1140 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6646 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6646 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7786 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7786 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7786 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7786 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 773 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 773 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1084 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1084 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48960262 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 48960262 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69313496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 69313496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118273758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 118273758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118273758 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 118273758 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7773 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7773 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7773 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7773 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53114761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53114761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73392998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73392998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507759 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126507759 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507759 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126507759 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63337.984476 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63337.984476 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63942.339483 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63942.339483 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68623.722222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68623.722222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68082.558442 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68082.558442 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 06f12379e..003c2ae7a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,97 +1,99 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144337 # Number of seconds simulated -sim_ticks 144337151000 # Number of ticks simulated -final_tick 144337151000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144463 # Number of seconds simulated +sim_ticks 144463317000 # Number of ticks simulated +final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71990 # Simulator instruction rate (inst/s) -host_op_rate 120663 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78676444 # Simulator tick rate (ticks/s) -host_mem_usage 280564 # Number of bytes of host memory used -host_seconds 1834.57 # Real time elapsed on the host +host_inst_rate 66822 # Simulator instruction rate (inst/s) +host_op_rate 111999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73091533 # Simulator tick rate (ticks/s) +host_mem_usage 308580 # Number of bytes of host memory used +host_seconds 1976.47 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125184 # Number of bytes read from this memory -system.physmem.bytes_read::total 343168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1956 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5362 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1510242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 867303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2377545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1510242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1510242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1510242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 867303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2377545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5363 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 5363 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 343168 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 343168 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 155 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 287 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 360 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 206 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 285 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 144337117000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5363 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory +system.physmem.bytes_read::total 342656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217088 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3392 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1962 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1502721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 869203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2371924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1502721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1502721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1502721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 869203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2371924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5354 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5354 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 342656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 342656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 163 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 289 # Per bank write bursts +system.physmem.perBankRdBursts::1 357 # Per bank write bursts +system.physmem.perBankRdBursts::2 453 # Per bank write bursts +system.physmem.perBankRdBursts::3 356 # Per bank write bursts +system.physmem.perBankRdBursts::4 332 # Per bank write bursts +system.physmem.perBankRdBursts::5 326 # Per bank write bursts +system.physmem.perBankRdBursts::6 402 # Per bank write bursts +system.physmem.perBankRdBursts::7 377 # Per bank write bursts +system.physmem.perBankRdBursts::8 341 # Per bank write bursts +system.physmem.perBankRdBursts::9 276 # Per bank write bursts +system.physmem.perBankRdBursts::10 232 # Per bank write bursts +system.physmem.perBankRdBursts::11 277 # Per bank write bursts +system.physmem.perBankRdBursts::12 205 # Per bank write bursts +system.physmem.perBankRdBursts::13 465 # Per bank write bursts +system.physmem.perBankRdBursts::14 384 # Per bank write bursts +system.physmem.perBankRdBursts::15 282 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 144463266500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5354 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,350 +152,344 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 502 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 668.557769 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 237.238454 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1295.396575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 170 33.86% 33.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 76 15.14% 49.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 42 8.37% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 23 4.58% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 26 5.18% 67.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 11 2.19% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 16 3.19% 72.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 9 1.79% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.79% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 7 1.39% 77.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3 0.60% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 8 1.59% 79.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 1.00% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 3 0.60% 81.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.80% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 1.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 0.80% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 1.00% 84.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.40% 85.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.40% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.60% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 5 1.00% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3 0.60% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.20% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.40% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.20% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.20% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.40% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 4 0.80% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 4 0.80% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.20% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.40% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 4 0.80% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.20% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 2 0.40% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 2 0.40% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.20% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 5 1.00% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.20% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.20% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.20% 95.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.20% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.20% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.40% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.20% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.20% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 2 0.40% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.20% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.20% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 1 0.20% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 5 1.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 502 # Bytes accessed per row activation -system.physmem.totQLat 12694000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 119204000 # Sum of mem lat for all requests -system.physmem.totBusLat 26815000 # Total cycles spent in databus access -system.physmem.totBankLat 79695000 # Total cycles spent in bank access -system.physmem.avgQLat 2366.96 # Average queueing delay per request -system.physmem.avgBankLat 14860.15 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22227.11 # Average memory access latency -system.physmem.avgRdBW 2.38 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.38 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.103448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.307957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 612.115437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 385 40.23% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 164 17.14% 57.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 81 8.46% 65.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 46 4.81% 70.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 43 4.49% 75.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 20 2.09% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 26 2.72% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 19 1.99% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 17 1.78% 83.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 26 2.72% 86.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 27 2.82% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 7 0.73% 89.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 7 0.73% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 7 0.73% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 3 0.31% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 5 0.52% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 6 0.63% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 6 0.63% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 4 0.42% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 2 0.21% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 2 0.21% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 3 0.31% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 7 0.73% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 0.10% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 5 0.52% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 4 0.42% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 2 0.21% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 2 0.21% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 0.21% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 3 0.31% 97.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 2 0.21% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 1 0.10% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 1 0.10% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 0.10% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 0.10% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.10% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 2 0.21% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 1 0.10% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 2 0.21% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 3 0.31% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 1 0.10% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 1 0.10% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 1 0.10% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 1 0.10% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 1 0.10% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 1 0.10% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 1 0.10% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation +system.physmem.totQLat 28805000 # Total ticks spent queuing +system.physmem.totMemAccLat 137868750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers +system.physmem.totBankLat 82293750 # Total ticks spent accessing banks +system.physmem.avgQLat 5380.09 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25750.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4861 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4397 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.64 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26913503.08 # Average gap between requests -system.membus.throughput 2376658 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3834 # Transaction distribution -system.membus.trans_dist::ReadResp 3831 # Transaction distribution -system.membus.trans_dist::UpgradeReq 155 # Transaction distribution -system.membus.trans_dist::UpgradeResp 155 # Transaction distribution -system.membus.trans_dist::ReadExReq 1529 # Transaction distribution -system.membus.trans_dist::ReadExResp 1529 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11033 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11033 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11033 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 343040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 343040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 343040 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 343040 # Total data (bytes) +system.physmem.avgGap 26982306.03 # Average gap between requests +system.physmem.pageHitRate 82.13 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 2371924 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3822 # Transaction distribution +system.membus.trans_dist::ReadResp 3822 # Transaction distribution +system.membus.trans_dist::UpgradeReq 163 # Transaction distribution +system.membus.trans_dist::UpgradeResp 163 # Transaction distribution +system.membus.trans_dist::ReadExReq 1532 # Transaction distribution +system.membus.trans_dist::ReadExResp 1532 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11034 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11034 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11034 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 342656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6990500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6948500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50919845 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 18643050 # Number of BP lookups -system.cpu.branchPred.condPredicted 18643050 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1490032 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11410312 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10785938 # Number of BTB hits +system.cpu.branchPred.lookups 18648234 # Number of BP lookups +system.cpu.branchPred.condPredicted 18648234 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.527985 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1319504 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 23183 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 288958646 # number of cpu cycles simulated +system.cpu.numCycles 289221873 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23449793 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206693394 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18643050 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12105442 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54202287 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15520872 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 177854529 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10399 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22344441 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 223502 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269290652 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.269559 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.757534 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23458037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206724223 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18648234 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54209099 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15518775 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22353213 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 224062 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216527015 80.41% 80.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2848467 1.06% 81.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2311919 0.86% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2635920 0.98% 83.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3216253 1.19% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3385278 1.26% 85.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3830479 1.42% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2556488 0.95% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31978833 11.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216842558 80.43% 80.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2312056 0.86% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31977576 11.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269290652 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064518 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.715304 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36876732 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 166835033 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41579230 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10227851 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13771806 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 335978387 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13771806 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44930878 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116570981 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 32723 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42705730 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51278534 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329616672 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10920 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26000838 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22678371 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382329896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917574751 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 605864950 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4114395 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36899349 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167130008 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41545231 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13773251 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336001478 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13773251 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44972476 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116686700 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42701692 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51445802 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329633797 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22730551 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382342114 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917586762 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 605878307 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122900446 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2069 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104883314 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84491871 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30099442 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58238426 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18921052 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322680314 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4268 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260554870 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118520 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100937084 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 209936848 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3023 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269290652 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.967560 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.344979 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 122912664 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105140053 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84507278 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322730912 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260501997 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 100987198 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 210203666 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269612466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143216818 53.18% 53.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55391998 20.57% 73.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34136198 12.68% 86.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19056794 7.08% 93.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10890991 4.04% 97.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4174838 1.55% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1812713 0.67% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476754 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 133548 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143429906 53.20% 53.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55567349 20.61% 73.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34108146 12.65% 86.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19044984 7.06% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10887633 4.04% 97.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4152281 1.54% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1816698 0.67% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269290652 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269612466 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 129591 4.77% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2286947 84.14% 88.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 301448 11.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2279077 84.03% 88.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210947 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162062878 62.20% 62.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788601 0.30% 62.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035610 2.70% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1446949 0.56% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65458486 25.12% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22551399 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162055945 62.21% 62.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65414515 25.11% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260554870 # Type of FU issued -system.cpu.iq.rate 0.901703 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2717986 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010432 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788349666 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420314195 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255192215 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4887232 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3589351 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2349681 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259602195 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2459714 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18922795 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260501997 # Type of FU issued +system.cpu.iq.rate 0.900700 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 788557581 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420384882 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255147074 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259544029 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18903383 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27842284 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26598 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 287421 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9583725 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27857691 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25993 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13771806 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85094278 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5458618 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322684582 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 133416 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84491871 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30099442 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2045 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2689502 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13828 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 287421 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 641114 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 899581 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1540695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258780631 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64687698 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1774239 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13773251 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85040641 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322734981 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84507278 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 901241 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1540639 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1769566 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87035316 # number of memory reference insts executed -system.cpu.iew.exec_branches 14266808 # Number of branches executed -system.cpu.iew.exec_stores 22347618 # Number of stores executed -system.cpu.iew.exec_rate 0.895563 # Inst execution rate -system.cpu.iew.wb_sent 258140972 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257541896 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206006775 # num instructions producing a value -system.cpu.iew.wb_consumers 369206880 # num instructions consuming a value +system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed +system.cpu.iew.exec_branches 14265860 # Number of branches executed +system.cpu.iew.exec_stores 22347175 # Number of stores executed +system.cpu.iew.exec_rate 0.894581 # Inst execution rate +system.cpu.iew.wb_sent 258096694 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257496638 # cumulative count of insts written-back +system.cpu.iew.wb_producers 205928299 # num instructions producing a value +system.cpu.iew.wb_consumers 369130532 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.891276 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557971 # average fanout of values written-back +system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101393363 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101448847 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1491544 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255518846 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.866329 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.656611 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255839215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156315405 61.18% 61.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57071451 22.34% 83.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14008929 5.48% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12048531 4.72% 93.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4172668 1.63% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2970306 1.16% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 908783 0.36% 96.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1048602 0.41% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6974171 2.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156486613 61.17% 61.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12054069 4.71% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4176262 1.63% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2944385 1.15% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 904563 0.35% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1049057 0.41% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6958755 2.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255518846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255839215 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -504,224 +500,222 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6974171 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6958755 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571301422 # The number of ROB reads -system.cpu.rob.rob_writes 659310799 # The number of ROB writes -system.cpu.timesIdled 5931788 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19667994 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571692691 # The number of ROB reads +system.cpu.rob.rob_writes 659422929 # The number of ROB writes +system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19609407 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.187901 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.187901 # CPI: Total CPI of All Threads -system.cpu.ipc 0.457059 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.457059 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451358394 # number of integer regfile reads -system.cpu.int_regfile_writes 233998694 # number of integer regfile writes -system.cpu.fp_regfile_reads 3217923 # number of floating regfile reads -system.cpu.fp_regfile_writes 2009376 # number of floating regfile writes -system.cpu.cc_regfile_reads 102822009 # number of cc regfile reads -system.cpu.cc_regfile_writes 59823089 # number of cc regfile writes -system.cpu.misc_regfile_reads 133360573 # number of misc regfile reads +system.cpu.cpi 2.189894 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 451224157 # number of integer regfile reads +system.cpu.int_regfile_writes 233957254 # number of integer regfile writes +system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads +system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes +system.cpu.cc_regfile_reads 102809518 # number of cc regfile reads +system.cpu.cc_regfile_writes 59799385 # number of cc regfile writes +system.cpu.misc_regfile_reads 133324418 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3892220 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7233 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7229 # Transaction distribution +system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7248 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1536 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1536 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13381 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4322 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17703 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 551808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 551808 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 9984 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4482000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeReq 163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13403 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17751 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 552704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 552704 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 10496 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4495500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10834750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10760250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3517155 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3467413 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4647 # number of replacements -system.cpu.icache.tags.tagsinuse 1626.526476 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22335618 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6612 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3378.042650 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4653 # number of replacements +system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22344301 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3375.272054 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526476 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.794202 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.794202 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22335618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22335618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22335618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22335618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22335618 # number of overall hits -system.cpu.icache.overall_hits::total 22335618 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8823 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8823 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8823 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8823 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8823 # number of overall misses -system.cpu.icache.overall_misses::total 8823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 352032500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 352032500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 352032500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 352032500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 352032500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 352032500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22344441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22344441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22344441 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22344441 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22344441 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22344441 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000395 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000395 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000395 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000395 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000395 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000395 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39899.410631 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39899.410631 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39899.410631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39899.410631 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 978 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 22344301 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22344301 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22344301 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22344301 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22344301 # number of overall hits +system.cpu.icache.overall_hits::total 22344301 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8911 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8911 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8911 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8911 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8911 # number of overall misses +system.cpu.icache.overall_misses::total 8911 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 368225749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 368225749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 368225749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 368225749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 368225749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 368225749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22353212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22353212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22353212 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22353212 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22353212 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22353212 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41322.606778 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41322.606778 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41322.606778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41322.606778 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.529412 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2054 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2054 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2054 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2054 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2054 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2054 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6769 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6769 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6769 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6769 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6769 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6769 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262819250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 262819250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262819250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 262819250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262819250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 262819250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2127 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2127 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2127 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2127 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2127 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2127 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271661249 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 271661249 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271661249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 271661249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271661249 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 271661249 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38826.894667 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38826.894667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.405808 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40044.405808 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2554.251018 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3246 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3834 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.846635 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2543.926921 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3826 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334816 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009517 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.077634 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3227 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 36 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3242 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3263 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 13 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 54 # number of replacements -system.cpu.dcache.tags.tagsinuse 1431.071380 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66125331 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33112.334001 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 57 # number of replacements +system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66102355 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32985.207086 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071380 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349383 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349383 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45611085 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45611085 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514038 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514038 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66125123 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66125123 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66125123 # number of overall hits -system.cpu.dcache.overall_hits::total 66125123 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 915 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 915 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1693 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1693 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2608 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2608 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2608 # number of overall misses -system.cpu.dcache.overall_misses::total 2608 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55175302 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55175302 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 106081155 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 106081155 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 161256457 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 161256457 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 161256457 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 161256457 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45612000 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45612000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 45588096 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45588096 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66102125 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66102125 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66102125 # number of overall hits +system.cpu.dcache.overall_hits::total 66102125 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1702 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2637 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2637 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2637 # number of overall misses +system.cpu.dcache.overall_misses::total 2637 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 62763567 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 62763567 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 113907163 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 113907163 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 176670730 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45589031 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45589031 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66127731 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66127731 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66127731 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66127731 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 66104762 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66104762 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66104762 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66104762 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60300.876503 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60300.876503 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62658.685765 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62658.685765 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61831.463574 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61831.463574 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67126.809626 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67126.809626 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66925.477673 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66925.477673 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66996.863860 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66996.863860 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 450 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 450 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 452 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 452 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 452 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 452 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 465 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 465 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1691 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1691 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2156 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2156 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2156 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2156 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31924750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31924750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101851095 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101851095 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133775845 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 133775845 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133775845 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 133775845 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 468 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109769587 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 109769587 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143360087 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 143360087 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143360087 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 143360087 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68655.376344 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68655.376344 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60231.280308 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60231.280308 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71928.265525 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71928.265525 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64532.385068 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64532.385068 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |