diff options
Diffstat (limited to 'tests/long/se')
8 files changed, 2443 insertions, 2443 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 83f6a1bd8..f6859d15c 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.199930 # Number of seconds simulated -sim_ticks 199930442500 # Number of ticks simulated -final_tick 199930442500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.199979 # Number of seconds simulated +sim_ticks 199978768500 # Number of ticks simulated +final_tick 199978768500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127290 # Simulator instruction rate (inst/s) -host_op_rate 143512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50370674 # Simulator tick rate (ticks/s) -host_mem_usage 265580 # Number of bytes of host memory used -host_seconds 3969.18 # Real time elapsed on the host +host_inst_rate 109627 # Simulator instruction rate (inst/s) +host_op_rate 123597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43391530 # Simulator tick rate (ticks/s) +host_mem_usage 297064 # Number of bytes of host memory used +host_seconds 4608.71 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9265152 # Number of bytes read from this memory -system.physmem.bytes_read::total 9481344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6247552 # Number of bytes written to this memory -system.physmem.bytes_written::total 6247552 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3378 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144768 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148146 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97618 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97618 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1081336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 46341877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47423213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1081336 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1081336 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31248628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31248628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31248628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1081336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 46341877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 78671841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148147 # Total number of read requests seen -system.physmem.writeReqs 97618 # Total number of write requests seen -system.physmem.cpureqs 247832 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9481344 # Total number of bytes read from memory -system.physmem.bytesWritten 6247552 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9481344 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6247552 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9166 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9182 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9622 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 9866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9514 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9403 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9092 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9052 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 9254 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8851 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9034 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9025 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9210 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5950 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 216704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9257984 # Number of bytes read from this memory +system.physmem.bytes_read::total 9474688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216704 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6246208 # Number of bytes written to this memory +system.physmem.bytes_written::total 6246208 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144656 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148042 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97597 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97597 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1083635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 46294835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47378470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1083635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1083635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31234356 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31234356 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31234356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1083635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 46294835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 78612825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148043 # Total number of read requests seen +system.physmem.writeReqs 97597 # Total number of write requests seen +system.physmem.cpureqs 245655 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9474688 # Total number of bytes read from memory +system.physmem.bytesWritten 6246208 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9474688 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6246208 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 8 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9178 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 9858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9513 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9082 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9057 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 9249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8856 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9050 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9211 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9024 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9010 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9201 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5953 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 5982 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6482 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6271 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6483 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 6170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6223 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6032 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5908 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6109 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6062 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6237 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6224 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6034 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5978 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5903 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6100 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5948 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6051 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6106 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2058 # Number of times wr buffer was full causing retry -system.physmem.totGap 199930425500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry +system.physmem.totGap 199978745500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148147 # Categorize read packet sizes +system.physmem.readPktSize::6 148043 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 97618 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 137980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97597 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 138031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -124,68 +124,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4226 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 34 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.totQLat 1712037750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4981606500 # Sum of mem lat for all requests -system.physmem.totBusLat 740435000 # Total cycles spent in databus access -system.physmem.totBankLat 2529133750 # Total cycles spent in bank access -system.physmem.avgQLat 11561.03 # Average queueing delay per request -system.physmem.avgBankLat 17078.70 # Average bank access latency per request +system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.totQLat 1694406500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4963552750 # Sum of mem lat for all requests +system.physmem.totBusLat 739875000 # Total cycles spent in databus access +system.physmem.totBankLat 2529271250 # Total cycles spent in bank access +system.physmem.avgQLat 11450.63 # Average queueing delay per request +system.physmem.avgBankLat 17092.56 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33639.73 # Average memory access latency -system.physmem.avgRdBW 47.42 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.42 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 33543.18 # Average memory access latency +system.physmem.avgRdBW 47.38 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 31.23 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 31.23 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.71 # Average write queue length over time -system.physmem.readRowHits 125393 # Number of row buffer hits during reads -system.physmem.writeRowHits 52794 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.08 # Row buffer hit rate for writes -system.physmem.avgGap 813502.43 # Average gap between requests -system.cpu.branchPred.lookups 182807672 # Number of BP lookups -system.cpu.branchPred.condPredicted 143119940 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7265200 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 92612738 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87226650 # Number of BTB hits +system.physmem.avgWrQLen 8.16 # Average write queue length over time +system.physmem.readRowHits 125326 # Number of row buffer hits during reads +system.physmem.writeRowHits 52813 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 54.11 # Row buffer hit rate for writes +system.physmem.avgGap 814113.11 # Average gap between requests +system.cpu.branchPred.lookups 182790798 # Number of BP lookups +system.cpu.branchPred.condPredicted 143104560 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7266331 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93146978 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87211884 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.184290 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12677704 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116304 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.628248 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12679404 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 115837 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,136 +229,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 399860886 # number of cpu cycles simulated +system.cpu.numCycles 399957538 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119358222 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761608008 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182807672 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99904354 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170147877 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35680811 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75396284 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 468 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 45 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114514342 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2439022 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 392517505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.176152 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.990501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119379666 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761592104 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182790798 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99891288 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170154666 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35685574 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 75463742 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 612 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114537866 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2438685 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 392618085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.175656 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.990351 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222382247 56.66% 56.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14190044 3.62% 60.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22888927 5.83% 66.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22740218 5.79% 71.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20908888 5.33% 77.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11594217 2.95% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13063164 3.33% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11994936 3.06% 86.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52754864 13.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222476087 56.66% 56.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14184800 3.61% 60.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22904886 5.83% 66.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22739285 5.79% 71.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20904776 5.32% 77.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11596191 2.95% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13057185 3.33% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11992863 3.05% 86.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52762012 13.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 392517505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.457178 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.904682 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129005298 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 70927026 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158858538 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6186097 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27540546 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26127343 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76683 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825553021 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 296390 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27540546 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135586345 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9628782 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46469860 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158285767 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15006205 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800628342 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1130 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3045894 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8758928 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 294 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954382842 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500628672 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500627387 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1285 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 392618085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457026 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.904182 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129039701 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 70981785 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158852483 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6198857 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27545259 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26125355 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76645 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825586648 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 296519 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27545259 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135624497 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9643215 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46459353 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158288427 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15057334 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800646746 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1025 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3043913 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8811846 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 273 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954314143 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500751257 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3500749947 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1310 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288130551 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292970 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292967 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41448640 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170247105 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73473871 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28488219 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15923707 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755060750 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775315 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665323167 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1373619 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187375419 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479909972 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797683 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 392517505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.695015 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.735938 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288061852 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2293040 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2293037 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41604001 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170281813 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73487632 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28633593 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 16029977 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755108515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775393 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665313430 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1367099 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187428477 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 480217782 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797761 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 392618085 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.694556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735285 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 137188203 34.95% 34.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69757763 17.77% 52.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71444239 18.20% 70.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53382766 13.60% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31199092 7.95% 92.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16084863 4.10% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8731670 2.22% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2913347 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1815562 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 137184245 34.94% 34.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69848764 17.79% 52.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71484982 18.21% 70.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53385142 13.60% 84.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31215558 7.95% 92.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16050252 4.09% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8736886 2.23% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2893580 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1818676 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 392517505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 392618085 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 478854 5.03% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6518035 68.44% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2526744 26.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 479033 5.02% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6517674 68.35% 73.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2539591 26.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447790300 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383235 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447798832 67.31% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383465 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -384,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153391187 23.06% 90.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63758352 9.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153381199 23.05% 90.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63749839 9.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665323167 # Type of FU issued -system.cpu.iq.rate 1.663887 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9523633 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014314 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1734060876 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947018314 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646045006 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665313430 # Type of FU issued +system.cpu.iq.rate 1.663460 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9536298 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014334 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1734148123 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947118126 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646033691 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674846691 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8570702 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674849617 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8562339 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44217550 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 42225 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810789 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16613394 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44252258 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 42000 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 809672 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16627155 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19530 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4440 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19517 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4404 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27540546 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5027645 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 374127 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760395240 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1110246 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170247105 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73473871 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286773 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 218357 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11618 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810789 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4336068 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4004006 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8340074 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655902697 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150107572 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9420470 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27545259 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5023337 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 374520 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760443219 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1117317 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170281813 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73487632 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286851 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 218824 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12460 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 809672 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4339991 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4001230 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8341221 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655886711 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150097752 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9426719 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1559175 # number of nop insts executed -system.cpu.iew.exec_refs 212574642 # number of memory reference insts executed -system.cpu.iew.exec_branches 138502057 # Number of branches executed -system.cpu.iew.exec_stores 62467070 # Number of stores executed -system.cpu.iew.exec_rate 1.640327 # Inst execution rate -system.cpu.iew.wb_sent 651021062 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646045022 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374765758 # num instructions producing a value -system.cpu.iew.wb_consumers 646459860 # num instructions consuming a value +system.cpu.iew.exec_nop 1559311 # number of nop insts executed +system.cpu.iew.exec_refs 212556043 # number of memory reference insts executed +system.cpu.iew.exec_branches 138504207 # Number of branches executed +system.cpu.iew.exec_stores 62458291 # Number of stores executed +system.cpu.iew.exec_rate 1.639891 # Inst execution rate +system.cpu.iew.wb_sent 651006973 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646033707 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374766500 # num instructions producing a value +system.cpu.iew.wb_consumers 646470459 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615674 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579720 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615256 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579712 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189453742 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189501793 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7191165 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 364976959 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.564395 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233817 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7192333 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 365072826 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.563984 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233117 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 157310366 43.10% 43.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98490082 26.99% 70.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33805907 9.26% 79.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18787402 5.15% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16180614 4.43% 88.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7431287 2.04% 90.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6987633 1.91% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3169968 0.87% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22813700 6.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 157316892 43.09% 43.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98576092 27.00% 70.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33819222 9.26% 79.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18783601 5.15% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16197747 4.44% 88.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7430684 2.04% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6971298 1.91% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3187688 0.87% 93.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22789602 6.24% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 364976959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 365072826 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,199 +472,199 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22813700 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22789602 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1102578030 # The number of ROB reads -system.cpu.rob.rob_writes 1548505178 # The number of ROB writes -system.cpu.timesIdled 308567 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7343381 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1102746046 # The number of ROB reads +system.cpu.rob.rob_writes 1548606173 # The number of ROB writes +system.cpu.timesIdled 308814 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7339453 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.791431 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.791431 # CPI: Total CPI of All Threads -system.cpu.ipc 1.263534 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.263534 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058706465 # number of integer regfile reads -system.cpu.int_regfile_writes 752037507 # number of integer regfile writes +system.cpu.cpi 0.791622 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.791622 # CPI: Total CPI of All Threads +system.cpu.ipc 1.263228 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.263228 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058599019 # number of integer regfile reads +system.cpu.int_regfile_writes 752005627 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210820275 # number of misc regfile reads +system.cpu.misc_regfile_reads 210805238 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.icache.replacements 15019 # number of replacements -system.cpu.icache.tagsinuse 1100.569602 # Cycle average of tags in use -system.cpu.icache.total_refs 114493231 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16877 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6783.980032 # Average number of references to valid blocks. +system.cpu.icache.replacements 14802 # number of replacements +system.cpu.icache.tagsinuse 1101.055470 # Cycle average of tags in use +system.cpu.icache.total_refs 114516987 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16660 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6873.768727 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1100.569602 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537388 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537388 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114493231 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114493231 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114493231 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114493231 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114493231 # number of overall hits -system.cpu.icache.overall_hits::total 114493231 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21111 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21111 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21111 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21111 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21111 # number of overall misses -system.cpu.icache.overall_misses::total 21111 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 514757500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 514757500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 514757500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 514757500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 514757500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 514757500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114514342 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114514342 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114514342 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114514342 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114514342 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114514342 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24383.378334 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24383.378334 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24383.378334 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24383.378334 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1152 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1101.055470 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537625 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537625 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114516991 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114516991 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114516991 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114516991 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114516991 # number of overall hits +system.cpu.icache.overall_hits::total 114516991 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 20874 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 20874 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 20874 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 20874 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 20874 # number of overall misses +system.cpu.icache.overall_misses::total 20874 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 507579000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 507579000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 507579000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 507579000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 507579000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 507579000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114537865 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114537865 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114537865 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114537865 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114537865 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114537865 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000182 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000182 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000182 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000182 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000182 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000182 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24316.326531 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24316.326531 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24316.326531 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24316.326531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24316.326531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24316.326531 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 485 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.615385 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 37.307692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4153 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4153 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4153 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4153 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4153 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4153 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16958 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16958 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16958 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16958 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16958 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16958 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375680500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 375680500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375680500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 375680500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375680500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 375680500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22153.585328 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22153.585328 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22153.585328 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22153.585328 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22153.585328 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22153.585328 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4132 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4132 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4132 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4132 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4132 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144769 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148147 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180723170 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2376770410 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2557493580 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3952267092 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3952267092 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180723170 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6329037502 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6509760672 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180723170 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6329037502 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6509760672 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051252 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054158 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.109756 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.109756 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290422 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290422 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122073 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122073 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53500.050326 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54694.981245 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.792518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3386 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43376 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46762 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101281 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101281 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3386 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144657 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148043 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3386 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144657 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148043 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 178901170 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2348139621 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2527040791 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 80008 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 80008 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3963100640 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3963100640 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178901170 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6311240261 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6490141431 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178901170 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6311240261 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6490141431 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.203376 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051154 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054085 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.094118 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.094118 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290345 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290345 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.203376 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122004 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.203376 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122004 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52835.549321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54134.535711 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54040.477118 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39010.078489 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39010.078489 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39129.754248 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39129.754248 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52835.549321 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43629.000055 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43839.569794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52835.549321 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43629.000055 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43839.569794 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192631 # number of replacements -system.cpu.dcache.tagsinuse 4058.209057 # Cycle average of tags in use -system.cpu.dcache.total_refs 190187917 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196727 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.923394 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1192680 # number of replacements +system.cpu.dcache.tagsinuse 4058.218189 # Cycle average of tags in use +system.cpu.dcache.total_refs 190190086 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196776 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 158.918700 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 4133508000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4058.209057 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990774 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990774 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136218647 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136218647 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50991635 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50991635 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488827 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488827 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 4058.218189 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990776 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990776 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136220587 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136220587 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50991825 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50991825 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488806 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488806 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187210282 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187210282 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187210282 # number of overall hits -system.cpu.dcache.overall_hits::total 187210282 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1699163 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1699163 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3247671 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3247671 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 187212412 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187212412 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187212412 # number of overall hits +system.cpu.dcache.overall_hits::total 187212412 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1696903 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1696903 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3247481 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3247481 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4946834 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4946834 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4946834 # number of overall misses -system.cpu.dcache.overall_misses::total 4946834 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26685574500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26685574500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57046648448 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57046648448 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 615500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 615500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83732222948 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83732222948 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83732222948 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83732222948 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137917810 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137917810 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4944384 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4944384 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4944384 # number of overall misses +system.cpu.dcache.overall_misses::total 4944384 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26525701000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26525701000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57242727951 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57242727951 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1087000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1087000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83768428951 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83768428951 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83768428951 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83768428951 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137917490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137917490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488868 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488868 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488847 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488847 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192157116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192157116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192157116 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192157116 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012320 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012320 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059877 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059877 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 192156796 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192156796 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192156796 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192156796 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012304 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012304 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059873 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059873 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025744 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025744 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025744 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025744 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15705.129231 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15705.129231 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17565.402545 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17565.402545 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15012.195122 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15012.195122 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16926.426670 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16926.426670 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18054 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15751 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1658 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 601 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.889023 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26.207987 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.025731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15631.831048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15631.831048 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17626.809195 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17626.809195 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26512.195122 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26512.195122 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16942.136564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16942.136564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16942.136564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16942.136564 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18871 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17919 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1660 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 609 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.368072 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 29.423645 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110977 # number of writebacks -system.cpu.dcache.writebacks::total 1110977 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850754 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 850754 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899270 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2899270 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1111118 # number of writebacks +system.cpu.dcache.writebacks::total 1111118 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 848410 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 848410 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899112 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2899112 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3750024 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3750024 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3750024 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3750024 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848409 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848409 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348401 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348401 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196810 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196810 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196810 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11849237000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11849237000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8091181496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8091181496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19940418496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19940418496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19940418496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19940418496 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 3747522 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3747522 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3747522 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3747522 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848493 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848493 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348369 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348369 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196862 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196862 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196862 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196862 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11822842000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11822842000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8101779997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8101779997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19924621997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19924621997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19924621997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19924621997 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13966.420677 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13966.420677 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23223.760827 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23223.760827 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13933.929920 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13933.929920 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23256.317287 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23256.317287 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16647.384575 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16647.384575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16647.384575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16647.384575 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 44aca7e96..412eefc9d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.434779 # Nu sim_ticks 434778577000 # Number of ticks simulated final_tick 434778577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65958 # Simulator instruction rate (inst/s) -host_op_rate 121963 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34681028 # Simulator tick rate (ticks/s) -host_mem_usage 469672 # Number of bytes of host memory used -host_seconds 12536.50 # Real time elapsed on the host +host_inst_rate 92341 # Simulator instruction rate (inst/s) +host_op_rate 170748 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48553388 # Simulator tick rate (ticks/s) +host_mem_usage 422424 # Number of bytes of host memory used +host_seconds 8954.65 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 207616 # Number of bytes read from this memory @@ -36,7 +36,7 @@ system.physmem.bw_total::cpu.data 56304964 # To system.physmem.bw_total::total 100008607 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 385749 # Total number of read requests seen system.physmem.writeReqs 293653 # Total number of write requests seen -system.physmem.cpureqs 898439 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 895346 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 24687808 # Total number of bytes read from memory system.physmem.bytesWritten 18793792 # Total number of bytes written to memory system.physmem.bytesConsumedRd 24687808 # bytesRead derated as per pkt->getSize() @@ -76,7 +76,7 @@ system.physmem.perBankWrReqs::13 17888 # Tr system.physmem.perBankWrReqs::14 18802 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 18117 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3123 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry system.physmem.totGap 434778560000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 37 # Wh system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32 # What write queue length does an incoming req see -system.physmem.totQLat 3433767500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12026720000 # Sum of mem lat for all requests +system.physmem.totQLat 3433770500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12026723000 # Sum of mem lat for all requests system.physmem.totBusLat 1927915000 # Total cycles spent in databus access system.physmem.totBankLat 6665037500 # Total cycles spent in bank access -system.physmem.avgQLat 8905.39 # Average queueing delay per request +system.physmem.avgQLat 8905.40 # Average queueing delay per request system.physmem.avgBankLat 17285.61 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31191.00 # Average memory access latency +system.physmem.avgMemAccLat 31191.01 # Average memory access latency system.physmem.avgRdBW 56.78 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 43.23 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 56.78 # Average consumed read bandwidth in MB/s @@ -196,17 +196,17 @@ system.cpu.fetch.Branches 214994146 # Nu system.cpu.fetch.predictedBranches 147887338 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 371275147 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 83409102 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 231974123 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 231974121 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 33791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 326928 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 173497134 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 3845609 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 854248204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 854248202 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.593680 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.388732 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 487377953 57.05% 57.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 487377951 57.05% 57.05% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 24712671 2.89% 59.95% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 27340185 3.20% 63.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 28885218 3.38% 66.53% # Number of instructions fetched each cycle (Total) @@ -218,11 +218,11 @@ system.cpu.fetch.rateDist::8 183370419 21.47% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 854248204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 854248202 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.247246 # Number of branch fetches per cycle system.cpu.fetch.rate 1.372267 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 237078092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 188537109 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 188537107 # Number of cycles decode is blocked system.cpu.decode.RunCycles 313423018 # Number of cycles decode is running system.cpu.decode.UnblockCycles 45192344 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 70017641 # Number of cycles decode is squashing @@ -230,7 +230,7 @@ system.cpu.decode.DecodedInsts 2166915251 # Nu system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 70017641 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 270505809 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54166582 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 54166580 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16246 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 322705449 # Number of cycles rename is running system.cpu.rename.UnblockCycles 136836477 # Number of cycles rename is unblocking @@ -259,11 +259,11 @@ system.cpu.iq.iqSquashedInstsIssued 841556 # Nu system.cpu.iq.iqSquashedInstsExamined 499552115 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 818199817 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 23145 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 854248204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 854248202 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.116852 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.887224 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233580311 27.34% 27.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233580309 27.34% 27.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 145624549 17.05% 44.39% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 138385021 16.20% 60.59% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 133093921 15.58% 76.17% # Number of insts issued each cycle @@ -275,7 +275,7 @@ system.cpu.iq.issued_per_cycle::8 1900056 0.22% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 854248204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 854248202 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 4959094 32.46% 32.46% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 32.46% # attempts to use FU when none available @@ -348,7 +348,7 @@ system.cpu.iq.FU_type_0::total 1808317213 # Ty system.cpu.iq.rate 2.079584 # Inst issue rate system.cpu.iq.fu_busy_cnt 15278274 # FU busy when requested system.cpu.iq.fu_busy_rate 0.008449 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4486980237 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 4486980235 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2533813283 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1768843031 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 22223 # Number of floating instruction queue reads @@ -368,7 +368,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 12353 # system.cpu.iew.lsq.thread0.cacheBlocked 585 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 70017641 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16317048 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 16317046 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 2892217 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 2034046776 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 2393263 # Number of squashed instructions skipped by dispatch @@ -401,11 +401,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 505092905 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 13168881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 784230563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 784230561 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.949667 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.458347 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 290802586 37.08% 37.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 290802584 37.08% 37.08% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 195769482 24.96% 62.04% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 62065599 7.91% 69.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 92211558 11.76% 81.72% # Number of insts commited each cycle @@ -417,7 +417,7 @@ system.cpu.commit.committed_per_cycle::8 69877590 8.91% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 784230563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 784230561 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -430,10 +430,10 @@ system.cpu.commit.int_insts 1528317561 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 69877590 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2748434579 # The number of ROB reads +system.cpu.rob.rob_reads 2748434577 # The number of ROB reads system.cpu.rob.rob_writes 4138359582 # The number of ROB writes system.cpu.timesIdled 322597 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15308951 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 15308953 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated @@ -532,14 +532,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4129.492827 system.cpu.icache.overall_avg_mshr_miss_latency::total 4129.492827 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 353068 # number of replacements -system.cpu.l2cache.tagsinuse 29624.531163 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29624.531166 # Cycle average of tags in use system.cpu.l2cache.total_refs 3697718 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 385429 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 9.593772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 201975419000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21048.484716 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21048.484720 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 232.592119 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8343.454327 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8343.454326 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.642349 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.007098 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.254622 # Average percentage of cache occupancy @@ -573,18 +573,18 @@ system.cpu.l2cache.overall_misses::cpu.inst 3245 # system.cpu.l2cache.overall_misses::cpu.data 382536 # number of overall misses system.cpu.l2cache.overall_misses::total 385781 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 201201000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10144981454 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 10346182454 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10144983954 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 10346184954 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7392500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 7392500 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10367117000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 10367117000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 201201000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20512098454 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20713299454 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20512100954 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20713301954 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 201201000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20512098454 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20713299454 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20512100954 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20713301954 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 7061 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1762430 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1769491 # number of ReadReq accesses(hits+misses) @@ -614,18 +614,18 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459567 system.cpu.l2cache.overall_miss_rate::cpu.data 0.150976 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151834 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62003.389831 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57716.709453 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57794.413123 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57716.723676 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57794.427088 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.243085 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.243085 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50139.855101 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50139.855101 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53621.354471 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53691.860029 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53621.361007 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53691.866510 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53621.354471 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53691.860029 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53621.361007 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53691.866510 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -650,18 +650,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 3245 system.cpu.l2cache.overall_mshr_misses::cpu.data 382536 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160858519 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7969651402 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8130509921 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7969654402 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8130512921 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2164647428 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2164647428 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7779866278 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7779866278 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160858519 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15749517680 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15910376199 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15749520680 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15910379199 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160858519 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15749517680 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15910376199 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15749520680 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15910379199 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099733 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101169 # mshr miss rate for ReadReq accesses @@ -676,18 +676,18 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.459567 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150976 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151834 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49571.192296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45340.847245 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45417.529737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45340.864313 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45417.546496 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.947133 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.947133 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37626.793243 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37626.793243 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41171.334672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41241.990142 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41171.342514 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41241.997919 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41171.334672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41241.990142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41171.342514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41241.997919 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2529656 # number of replacements system.cpu.dcache.tagsinuse 4087.796251 # Cycle average of tags in use @@ -716,12 +716,12 @@ system.cpu.dcache.overall_misses::cpu.data 3900651 # system.cpu.dcache.overall_misses::total 3900651 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 51401791500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 51401791500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23898482499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23898482499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75300273999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75300273999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75300273999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75300273999 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23898481499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23898481499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75300272999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75300272999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75300272999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75300272999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 259505338 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 259505338 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) @@ -740,12 +740,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17753.363092 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 17753.363092 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23771.920793 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23771.920793 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19304.540191 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19304.540191 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19304.540191 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19304.540191 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23771.919798 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23771.919798 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19304.539934 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19304.539934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19304.539934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19304.539934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 6530 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 642 # number of cycles access was blocked diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index a79a513d0..36773aebe 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.042726 # Nu sim_ticks 42726055500 # Number of ticks simulated final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89848 # Simulator instruction rate (inst/s) -host_op_rate 89848 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43455006 # Simulator tick rate (ticks/s) -host_mem_usage 257260 # Number of bytes of host memory used -host_seconds 983.23 # Real time elapsed on the host +host_inst_rate 80618 # Simulator instruction rate (inst/s) +host_op_rate 80618 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38990762 # Simulator tick rate (ticks/s) +host_mem_usage 257380 # Number of bytes of host memory used +host_seconds 1095.80 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory @@ -36,7 +36,7 @@ system.physmem.bw_total::cpu.data 237287713 # To system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 165519 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279530 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 279517 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 10593216 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize() @@ -76,7 +76,7 @@ system.physmem.perBankWrReqs::13 7250 # Tr system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry system.physmem.totGap 42726035000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 1 # Wh system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.totQLat 7053839750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9647402250 # Sum of mem lat for all requests +system.physmem.totQLat 7053831750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9647394250 # Sum of mem lat for all requests system.physmem.totBusLat 827595000 # Total cycles spent in databus access system.physmem.totBankLat 1765967500 # Total cycles spent in bank access -system.physmem.avgQLat 42616.50 # Average queueing delay per request +system.physmem.avgQLat 42616.45 # Average queueing delay per request system.physmem.avgBankLat 10669.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58285.77 # Average memory access latency +system.physmem.avgMemAccLat 58285.72 # Average memory access latency system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s @@ -403,14 +403,14 @@ system.cpu.l2cache.overall_misses::total 165519 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 455300000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513155000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1968455000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996427000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11996427000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996609634 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11996609634 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 455300000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13509582000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13964882000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13509764634 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13965064634 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 455300000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13509582000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13964882000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13509764634 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13965064634 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 86354 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses) @@ -438,14 +438,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.569383 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64063.599268 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54981.832056 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 56845.760656 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91652.038719 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91652.038719 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91653.434033 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91653.434033 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84370.265649 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.457352 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84371.369051 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84370.265649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.457352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84371.369051 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,14 +470,14 @@ system.cpu.l2cache.overall_mshr_misses::total 165519 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366897656 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1170781845 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537679501 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407190958 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407190958 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407373592 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407373592 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366897656 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11577972803 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11944870459 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11578155437 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11945053093 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366897656 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11577972803 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11944870459 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11578155437 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11945053093 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses @@ -492,14 +492,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51624.828479 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42541.399113 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44405.668852 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79510.363264 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79510.363264 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79511.758578 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79511.758578 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73088.878601 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72167.262326 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73088.878601 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72167.262326 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200249 # number of replacements system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 74c8f08b1..b5df8dc7b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023888 # Nu sim_ticks 23888231000 # Number of ticks simulated final_tick 23888231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143918 # Simulator instruction rate (inst/s) -host_op_rate 143918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43194720 # Simulator tick rate (ticks/s) -host_mem_usage 260336 # Number of bytes of host memory used -host_seconds 553.04 # Real time elapsed on the host +host_inst_rate 183235 # Simulator instruction rate (inst/s) +host_op_rate 183235 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54995028 # Simulator tick rate (ticks/s) +host_mem_usage 260452 # Number of bytes of host memory used +host_seconds 434.37 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 490944 # Number of bytes read from this memory @@ -604,14 +604,14 @@ system.cpu.l2cache.overall_misses::total 166330 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 493837000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1614539500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 2108376500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12203454500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12203454500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12203503384 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12203503384 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 493837000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13817994000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14311831000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13818042884 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14311879884 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 493837000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13817994000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14311831000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13818042884 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14311879884 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 93652 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 62106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 155758 # number of ReadReq accesses(hits+misses) @@ -639,14 +639,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.555949 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64368.743483 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57947.724499 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 59334.060337 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93301.435059 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93301.435059 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93301.808801 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93301.808801 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64368.743483 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87092.954657 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86044.796489 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87093.262766 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86045.090387 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64368.743483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87092.954657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86044.796489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87093.262766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86045.090387 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -671,14 +671,14 @@ system.cpu.l2cache.overall_mshr_misses::total 166330 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 398141894 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1271865950 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1670007844 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10613542919 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10613542919 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10613591803 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10613591803 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 398141894 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11885408869 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12283550763 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11885457753 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12283599647 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 398141894 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11885408869 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12283550763 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11885457753 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12283599647 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081920 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228136 # mshr miss rate for ReadReq accesses @@ -693,14 +693,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.555949 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51895.450209 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45648.767138 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46997.462824 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81145.776010 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81145.776010 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81146.149752 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81146.149752 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51895.450209 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74912.130929 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73850.482553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74912.439039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73850.776450 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51895.450209 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74912.130929 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73850.482553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74912.439039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73850.776450 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 201434 # number of replacements system.cpu.dcache.tagsinuse 4076.506217 # Cycle average of tags in use diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 6f25374e1..f9d46e356 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025578 # Number of seconds simulated -sim_ticks 25578307500 # Number of ticks simulated -final_tick 25578307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025579 # Number of seconds simulated +sim_ticks 25578679000 # Number of ticks simulated +final_tick 25578679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122516 # Simulator instruction rate (inst/s) -host_op_rate 173866 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44194830 # Simulator tick rate (ticks/s) -host_mem_usage 267056 # Number of bytes of host memory used -host_seconds 578.76 # Real time elapsed on the host +host_inst_rate 106593 # Simulator instruction rate (inst/s) +host_op_rate 151269 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38451628 # Simulator tick rate (ticks/s) +host_mem_usage 298528 # Number of bytes of host memory used +host_seconds 665.22 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241664 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372288 # Number of bytes written to this memory system.physmem.bytes_written::total 5372288 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128776 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83942 # Number of write requests responded to by this memory system.physmem.num_writes::total 83942 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11654876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 310553151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 322208027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11654876 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11654876 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 210032974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 210032974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 210032974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11654876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 310553151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 532241001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128775 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 11654707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 310553645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 322208352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11654707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11654707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 210029924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 210029924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 210029924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11654707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 310553645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 532238275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128777 # Total number of read requests seen system.physmem.writeReqs 83942 # Total number of write requests seen -system.physmem.cpureqs 213036 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8241536 # Total number of bytes read from memory +system.physmem.cpureqs 213038 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8241664 # Total number of bytes read from memory system.physmem.bytesWritten 5372288 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8241536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 5372288 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 319 # Reqs where no action is needed system.physmem.perBankRdReqs::0 7977 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8192 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 8064 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 8161 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 8170 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 8108 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7996 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8047 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7986 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 8126 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 8035 # Track reads on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 5132 # Tr system.physmem.perBankWrReqs::15 5152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25578289000 # Total gap between requests +system.physmem.totGap 25578660500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128775 # Categorize read packet sizes +system.physmem.readPktSize::6 128777 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,9 +92,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 83942 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 70073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2088 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -124,7 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3552 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 3640 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3648 # What write queue length does an incoming req see @@ -147,7 +147,7 @@ system.physmem.wrQLenPdf::19 3649 # Wh system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 98 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3208033250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 5250782000 # Sum of mem lat for all requests -system.physmem.totBusLat 643865000 # Total cycles spent in databus access -system.physmem.totBankLat 1398883750 # Total cycles spent in bank access -system.physmem.avgQLat 24912.31 # Average queueing delay per request -system.physmem.avgBankLat 10863.18 # Average bank access latency per request +system.physmem.totQLat 3210060500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5252104250 # Sum of mem lat for all requests +system.physmem.totBusLat 643875000 # Total cycles spent in databus access +system.physmem.totBankLat 1398168750 # Total cycles spent in bank access +system.physmem.avgQLat 24927.67 # Average queueing delay per request +system.physmem.avgBankLat 10857.45 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40775.49 # Average memory access latency +system.physmem.avgMemAccLat 40785.12 # Average memory access latency system.physmem.avgRdBW 322.21 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 210.03 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 322.21 # Average consumed read bandwidth in MB/s @@ -172,19 +172,19 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 4.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.21 # Average read queue length over time system.physmem.avgWrQLen 9.59 # Average write queue length over time -system.physmem.readRowHits 116753 # Number of row buffer hits during reads -system.physmem.writeRowHits 52875 # Number of row buffer hits during writes +system.physmem.readRowHits 116755 # Number of row buffer hits during reads +system.physmem.writeRowHits 52878 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes -system.physmem.avgGap 120245.63 # Average gap between requests -system.cpu.branchPred.lookups 16623364 # Number of BP lookups -system.cpu.branchPred.condPredicted 12760071 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 602765 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10462695 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7764975 # Number of BTB hits +system.physmem.avgGap 120246.24 # Average gap between requests +system.cpu.branchPred.lookups 16623550 # Number of BP lookups +system.cpu.branchPred.condPredicted 12760225 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 602776 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10462790 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7764993 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.215821 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825729 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 74.215319 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1825730 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 113390 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -229,99 +229,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 51156616 # number of cpu cycles simulated +system.cpu.numCycles 51157359 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12528030 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85177625 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16623364 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9590704 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21186632 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2363015 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10581483 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 556 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 12528196 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85178151 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16623550 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9590723 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21186766 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2362966 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10580824 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 65 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 592 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11675113 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179601 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46030680 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.591102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 11675240 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179625 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46030286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.591135 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335079 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24864286 54.02% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2136700 4.64% 58.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1964680 4.27% 62.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2042011 4.44% 67.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1465176 3.18% 70.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1378812 3.00% 73.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 958023 2.08% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1192746 2.59% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10028246 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24863758 54.02% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2136664 4.64% 58.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1964751 4.27% 62.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2042058 4.44% 67.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1465237 3.18% 70.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1378794 3.00% 73.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 958007 2.08% 75.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1192757 2.59% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10028260 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46030680 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324950 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.665036 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14611647 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8930047 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19464619 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1393461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1630906 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3329793 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104768 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116826129 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 364020 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1630906 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16323488 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2561901 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 880060 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19095828 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5538497 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114955733 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 140 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 16360 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4684188 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 46030286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324949 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.665022 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14611843 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8929429 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19464778 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1393400 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1630836 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3329843 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104767 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116826409 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 364015 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1630836 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16323672 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2560343 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 881200 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19095931 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5538304 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114955778 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 16357 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4684077 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 269 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115265758 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529627924 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529622592 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 115266627 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529628092 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529622760 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 5332 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16133086 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20210 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20206 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13085457 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29620481 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22434207 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3897313 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4409985 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111515856 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35838 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107234062 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 271666 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10778201 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25823888 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2052 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46030680 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.329622 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.987561 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16133955 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20202 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20198 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13085199 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29620303 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22433978 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3897320 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4410132 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111515414 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35833 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107233709 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 271611 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10777789 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25822592 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2047 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46030286 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.329634 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.987559 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10772740 23.40% 23.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8089543 17.57% 40.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7436956 16.16% 57.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7132439 15.49% 72.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5411666 11.76% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3908589 8.49% 92.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1839107 4.00% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 868081 1.89% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571559 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10772482 23.40% 23.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8089494 17.57% 40.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7436899 16.16% 57.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7132502 15.50% 72.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5411548 11.76% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3908660 8.49% 92.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1839023 4.00% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 868143 1.89% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 571535 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46030680 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46030286 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112263 4.55% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112260 4.55% 4.55% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available @@ -350,13 +350,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1357458 55.03% 59.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 996979 40.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1357456 55.03% 59.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 996870 40.41% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56624593 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91608 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56624482 52.80% 52.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91603 0.09% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 187 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued @@ -384,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28897959 26.95% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21619708 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28897893 26.95% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21619537 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107234062 # Type of FU issued -system.cpu.iq.rate 2.096191 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2466700 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023003 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263236655 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122357738 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105553758 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 107233709 # Type of FU issued +system.cpu.iq.rate 2.096154 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2466586 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023002 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263235386 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122356888 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105553525 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 515 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 808 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109700502 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 109700035 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2179129 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 2179098 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2313373 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6760 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29813 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1878469 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2313195 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6752 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29821 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1878240 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 507 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1630906 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1049242 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45608 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111561445 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 293593 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29620481 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22434207 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19918 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6795 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5249 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29813 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 391440 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181697 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 573137 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106207608 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28598944 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1026454 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1630836 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1047773 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45606 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111560996 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 293586 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29620303 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22433978 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19913 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6800 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5244 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29821 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 391475 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181717 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573192 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106207305 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28598865 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1026404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9751 # number of nop insts executed -system.cpu.iew.exec_refs 49933957 # number of memory reference insts executed -system.cpu.iew.exec_branches 14599960 # Number of branches executed -system.cpu.iew.exec_stores 21335013 # Number of stores executed -system.cpu.iew.exec_rate 2.076127 # Inst execution rate -system.cpu.iew.wb_sent 105772826 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105553928 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53290488 # num instructions producing a value -system.cpu.iew.wb_consumers 103570522 # num instructions consuming a value +system.cpu.iew.exec_nop 9749 # number of nop insts executed +system.cpu.iew.exec_refs 49933799 # number of memory reference insts executed +system.cpu.iew.exec_branches 14599943 # Number of branches executed +system.cpu.iew.exec_stores 21334934 # Number of stores executed +system.cpu.iew.exec_rate 2.076090 # Inst execution rate +system.cpu.iew.wb_sent 105772568 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105553695 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53290851 # num instructions producing a value +system.cpu.iew.wb_consumers 103571318 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.063349 # insts written-back per cycle +system.cpu.iew.wb_rate 2.063314 # insts written-back per cycle system.cpu.iew.wb_fanout 0.514533 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10929916 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10929447 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 499809 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44399774 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.266508 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.764024 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 499822 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44399450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.266524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764020 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15322992 34.51% 34.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11640164 26.22% 60.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3466305 7.81% 68.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2879897 6.49% 75.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880990 4.24% 79.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1948005 4.39% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685170 1.54% 85.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 565050 1.27% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6011201 13.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15322466 34.51% 34.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11640372 26.22% 60.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3466304 7.81% 68.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2879944 6.49% 75.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1880994 4.24% 79.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1947998 4.39% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685125 1.54% 85.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 565076 1.27% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6011171 13.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44399774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44399450 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,70 +472,70 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6011201 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6011171 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149925618 # The number of ROB reads -system.cpu.rob.rob_writes 224764611 # The number of ROB writes -system.cpu.timesIdled 74074 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5125936 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 149924855 # The number of ROB reads +system.cpu.rob.rob_writes 224763597 # The number of ROB writes +system.cpu.timesIdled 74024 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5127073 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.721454 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.721454 # CPI: Total CPI of All Threads -system.cpu.ipc 1.386089 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.386089 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511542927 # number of integer regfile reads -system.cpu.int_regfile_writes 103323311 # number of integer regfile writes +system.cpu.cpi 0.721465 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.721465 # CPI: Total CPI of All Threads +system.cpu.ipc 1.386069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.386069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511541679 # number of integer regfile reads +system.cpu.int_regfile_writes 103323268 # number of integer regfile writes system.cpu.fp_regfile_reads 788 # number of floating regfile reads system.cpu.fp_regfile_writes 660 # number of floating regfile writes -system.cpu.misc_regfile_reads 49174075 # number of misc regfile reads +system.cpu.misc_regfile_reads 49173958 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes system.cpu.icache.replacements 28620 # number of replacements -system.cpu.icache.tagsinuse 1814.212486 # Cycle average of tags in use -system.cpu.icache.total_refs 11640356 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1814.215623 # Cycle average of tags in use +system.cpu.icache.total_refs 11640482 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 30656 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379.708899 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 379.713009 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.212486 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.885846 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.885846 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11640361 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11640361 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11640361 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11640361 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11640361 # number of overall hits -system.cpu.icache.overall_hits::total 11640361 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34752 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34752 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34752 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34752 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34752 # number of overall misses -system.cpu.icache.overall_misses::total 34752 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 732057000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 732057000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 732057000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 732057000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 732057000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 732057000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11675113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11675113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11675113 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11675113 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11675113 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11675113 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1814.215623 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885847 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885847 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11640487 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11640487 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11640487 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11640487 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11640487 # number of overall hits +system.cpu.icache.overall_hits::total 11640487 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34753 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34753 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34753 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34753 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34753 # number of overall misses +system.cpu.icache.overall_misses::total 34753 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 732473500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 732473500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 732473500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 732473500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 732473500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 732473500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11675240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11675240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11675240 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11675240 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11675240 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11675240 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002977 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.002977 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.002977 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.002977 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.002977 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.002977 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21065.176105 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21065.176105 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21065.176105 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21065.176105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21065.176105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21065.176105 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21076.554542 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21076.554542 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21076.554542 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21076.554542 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21076.554542 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21076.554542 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 767 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked @@ -544,132 +544,132 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 31.958333 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955441 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955441 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955423 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955423 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.153060 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.764596 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.764594 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.667810 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153060 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.764596 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.764594 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.667810 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5395861980 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245320540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606004493 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6851325033 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245320540 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606004493 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6851325033 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394681 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308632 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394710 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308652 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.943787 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.943787 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955441 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955441 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955423 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955423 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764214 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764212 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.667411 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764214 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764212 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.667411 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52596.435072 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55188.518047 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54733.109850 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52655.192101 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55356.228581 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54881.713914 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.203762 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.203762 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52788.974877 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52788.974877 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52596.435072 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53211.576429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53189.320994 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52596.435072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53211.576429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53189.320994 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52767.653853 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52767.653853 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52655.192101 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53223.581535 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53203.017876 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52655.192101 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53223.581535 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53203.017876 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158314 # number of replacements -system.cpu.dcache.tagsinuse 4072.315596 # Cycle average of tags in use -system.cpu.dcache.total_refs 44364658 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162410 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.164571 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158317 # number of replacements +system.cpu.dcache.tagsinuse 4072.315940 # Cycle average of tags in use +system.cpu.dcache.total_refs 44364640 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162413 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.159415 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.315596 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4072.315940 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26064858 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26064858 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18267205 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18267205 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 26064832 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26064832 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267213 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44332063 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44332063 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44332063 # number of overall hits -system.cpu.dcache.overall_hits::total 44332063 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124444 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124444 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1582696 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1582696 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 44332045 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44332045 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44332045 # number of overall hits +system.cpu.dcache.overall_hits::total 44332045 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124417 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124417 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1582688 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1582688 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707140 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707140 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707140 # number of overall misses -system.cpu.dcache.overall_misses::total 1707140 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4243660500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4243660500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 98452063982 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 98452063982 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1707105 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707105 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707105 # number of overall misses +system.cpu.dcache.overall_misses::total 1707105 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247904000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4247904000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98406408482 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98406408482 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1297000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 1297000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102695724482 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102695724482 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102695724482 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102695724482 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26189302 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26189302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 102654312482 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102654312482 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102654312482 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102654312482 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26189249 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26189249 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16031 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 16031 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46039203 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46039203 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46039203 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46039203 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 46039150 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46039150 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46039150 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46039150 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004751 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004751 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079733 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.079733 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002807 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002807 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037080 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037080 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037080 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037080 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34100.965093 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34100.965093 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62205.290202 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62205.290202 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.037079 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037079 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037079 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037079 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34142.472492 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34142.472492 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62176.757821 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62176.757821 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28822.222222 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28822.222222 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60156.592009 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60156.592009 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5240 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60133.566759 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60133.566759 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60133.566759 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60133.566759 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5187 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.305785 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.516393 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129088 # number of writebacks -system.cpu.dcache.writebacks::total 129088 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69028 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69028 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475364 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475364 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 129090 # number of writebacks +system.cpu.dcache.writebacks::total 129090 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69000 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69000 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475354 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475354 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544392 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544392 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544392 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544392 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55416 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55416 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162748 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162748 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162748 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162748 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1874890000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1874890000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6816019991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6816019991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8690909991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8690909991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8690909991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8690909991 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1544354 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544354 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544354 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544354 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55417 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55417 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107334 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107334 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162751 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162751 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162751 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162751 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878666500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878666500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6813869491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6813869491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8692535991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8692535991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8692535991 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8692535991 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses @@ -859,14 +859,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33833.008517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33833.008517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63504.080712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63504.080712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33900.544959 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33900.544959 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63482.861824 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63482.861824 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53410.031219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53410.031219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53410.031219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53410.031219 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 4d872659d..6baeed8b3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.993559 # Nu sim_ticks 993559170500 # Number of ticks simulated final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139940 # Simulator instruction rate (inst/s) -host_op_rate 139940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76403951 # Simulator tick rate (ticks/s) -host_mem_usage 449176 # Number of bytes of host memory used -host_seconds 13004.03 # Real time elapsed on the host +host_inst_rate 90803 # Simulator instruction rate (inst/s) +host_op_rate 90803 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49576515 # Simulator tick rate (ticks/s) +host_mem_usage 449304 # Number of bytes of host memory used +host_seconds 20040.92 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -36,7 +36,7 @@ system.physmem.bw_total::cpu.data 126177745 # To system.physmem.bw_total::total 191811167 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1959688 # Total number of read requests seen system.physmem.writeReqs 1018058 # Total number of write requests seen -system.physmem.cpureqs 2977859 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 125420032 # Total number of bytes read from memory system.physmem.bytesWritten 65155712 # Total number of bytes written to memory system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize() @@ -76,7 +76,7 @@ system.physmem.perBankWrReqs::13 64147 # Tr system.physmem.perBankWrReqs::14 63647 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 64278 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 113 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry system.physmem.totGap 993559118500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index e183c5fce..75aae5e90 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.665771 # Number of seconds simulated -sim_ticks 665770972500 # Number of ticks simulated -final_tick 665770972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.665696 # Number of seconds simulated +sim_ticks 665695988500 # Number of ticks simulated +final_tick 665695988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179472 # Simulator instruction rate (inst/s) -host_op_rate 179472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68827168 # Simulator tick rate (ticks/s) -host_mem_usage 452252 # Number of bytes of host memory used -host_seconds 9673.08 # Real time elapsed on the host +host_inst_rate 147850 # Simulator instruction rate (inst/s) +host_op_rate 147850 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56693787 # Simulator tick rate (ticks/s) +host_mem_usage 452372 # Number of bytes of host memory used +host_seconds 11741.96 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 62016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125796608 # Number of bytes read from this memory -system.physmem.bytes_read::total 125858624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265344 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265344 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 969 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965572 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966541 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019771 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019771 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 188948772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 189041922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98029723 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98029723 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98029723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 188948772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 287071645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966541 # Total number of read requests seen -system.physmem.writeReqs 1019771 # Total number of write requests seen -system.physmem.cpureqs 2988947 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125858624 # Total number of bytes read from memory -system.physmem.bytesWritten 65265344 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125858624 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65265344 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 566 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125794176 # Number of bytes read from this memory +system.physmem.bytes_read::total 125855680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65263360 # Number of bytes written to this memory +system.physmem.bytes_written::total 65263360 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965534 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966495 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019740 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019740 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 188966402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 189058793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98037785 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98037785 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98037785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 188966402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 287096578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966495 # Total number of read requests seen +system.physmem.writeReqs 1019740 # Total number of write requests seen +system.physmem.cpureqs 2986251 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125855680 # Total number of bytes read from memory +system.physmem.bytesWritten 65263360 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125855680 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65263360 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 570 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 122314 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 122187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 124202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122594 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 122637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 122329 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 122200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 124178 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122601 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 120701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 121432 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121606 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 121460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 123481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 125598 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 124291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 123180 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 124411 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63480 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 62406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63107 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63843 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 64137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63874 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63470 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63464 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 63489 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63362 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64287 # Track writes on a per bank basis +system.physmem.perBankRdReqs::7 121425 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121612 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122268 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 121458 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 123448 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125589 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 124287 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 123163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 124393 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63486 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 62408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 64141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63880 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63465 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63456 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 63488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63352 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64238 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64665 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64277 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 63760 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64358 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2635 # Number of times wr buffer was full causing retry -system.physmem.totGap 665770904000 # Total gap between requests +system.physmem.numWrRetry 16 # Number of times wr buffer was full causing retry +system.physmem.totGap 665695920000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966541 # Categorize read packet sizes +system.physmem.readPktSize::6 1966495 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1019771 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1625771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 77503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019740 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1625686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 77588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -124,88 +124,88 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44298 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.totQLat 34478547500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102599787500 # Sum of mem lat for all requests -system.physmem.totBusLat 9829875000 # Total cycles spent in databus access -system.physmem.totBankLat 58291365000 # Total cycles spent in bank access -system.physmem.avgQLat 17537.63 # Average queueing delay per request -system.physmem.avgBankLat 29650.10 # Average bank access latency per request +system.physmem.totQLat 34438847000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102566423250 # Sum of mem lat for all requests +system.physmem.totBusLat 9829625000 # Total cycles spent in databus access +system.physmem.totBankLat 58297951250 # Total cycles spent in bank access +system.physmem.avgQLat 17517.88 # Average queueing delay per request +system.physmem.avgBankLat 29654.21 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52187.74 # Average memory access latency -system.physmem.avgRdBW 189.04 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 98.03 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 189.04 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 98.03 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52172.09 # Average memory access latency +system.physmem.avgRdBW 189.06 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 98.04 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 189.06 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 98.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.24 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.14 # Average write queue length over time -system.physmem.readRowHits 776350 # Number of row buffer hits during reads -system.physmem.writeRowHits 285987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.04 # Row buffer hit rate for writes -system.physmem.avgGap 222940.84 # Average gap between requests -system.cpu.branchPred.lookups 381390262 # Number of BP lookups -system.cpu.branchPred.condPredicted 296397889 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16086653 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262140629 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259559256 # Number of BTB hits +system.physmem.avgWrQLen 10.61 # Average write queue length over time +system.physmem.readRowHits 776012 # Number of row buffer hits during reads +system.physmem.writeRowHits 286087 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.05 # Row buffer hit rate for writes +system.physmem.avgGap 222921.48 # Average gap between requests +system.cpu.branchPred.lookups 381386947 # Number of BP lookups +system.cpu.branchPred.condPredicted 296385810 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16088637 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262415494 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259543645 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.015272 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24699160 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3055 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.905610 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24703591 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3035 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613788534 # DTB read hits -system.cpu.dtb.read_misses 11249325 # DTB read misses +system.cpu.dtb.read_hits 613791968 # DTB read hits +system.cpu.dtb.read_misses 11248781 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625037859 # DTB read accesses -system.cpu.dtb.write_hits 212245958 # DTB write hits -system.cpu.dtb.write_misses 7142739 # DTB write misses +system.cpu.dtb.read_accesses 625040749 # DTB read accesses +system.cpu.dtb.write_hits 212266069 # DTB write hits +system.cpu.dtb.write_misses 7139950 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219388697 # DTB write accesses -system.cpu.dtb.data_hits 826034492 # DTB hits -system.cpu.dtb.data_misses 18392064 # DTB misses +system.cpu.dtb.write_accesses 219406019 # DTB write accesses +system.cpu.dtb.data_hits 826058037 # DTB hits +system.cpu.dtb.data_misses 18388731 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844426556 # DTB accesses -system.cpu.itb.fetch_hits 390787767 # ITB hits -system.cpu.itb.fetch_misses 43 # ITB misses +system.cpu.dtb.data_accesses 844446768 # DTB accesses +system.cpu.itb.fetch_hits 390789739 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 390787810 # ITB accesses +system.cpu.itb.fetch_accesses 390789783 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,138 +219,138 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1331541946 # number of cpu cycles simulated +system.cpu.numCycles 1331391978 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402238482 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3159760476 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381390262 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284258416 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574242721 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140320135 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 173885771 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1317 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 44 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 390787767 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8065204 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1266865295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152669 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402247693 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3159701831 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381386947 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284247236 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574240478 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140323731 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 173777898 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1315 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 390789739 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8060023 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1266766339 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494305 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152696 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 692622574 54.67% 54.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42615431 3.36% 58.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21758353 1.72% 59.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39697295 3.13% 62.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129259260 10.20% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61526950 4.86% 77.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38544819 3.04% 80.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28129154 2.22% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212711459 16.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 692525861 54.67% 54.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42625697 3.36% 58.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21759185 1.72% 59.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39691714 3.13% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129252182 10.20% 73.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61534262 4.86% 77.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38544537 3.04% 80.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28127846 2.22% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212705055 16.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1266865295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286428 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.373009 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 433949818 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 155380202 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542435049 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18604092 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116496134 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58311036 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 855 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3087126857 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2089 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116496134 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 456815247 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 101557658 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5194 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535499027 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56492035 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3005134049 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 566488 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1739616 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 50408333 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2246840239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3897438135 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3896197591 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1240544 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1266766339 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286457 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.373232 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433937783 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 155286584 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542483654 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18560300 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116498018 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58313191 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 862 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3087105649 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2059 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116498018 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456816204 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 101540810 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6220 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535489445 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56415642 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3005086963 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 566623 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1738834 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 50324811 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2246778226 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3897347889 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3896105158 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1242731 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 870637276 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 168 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 870575263 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 167 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 166 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121366950 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679350790 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255350759 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67967300 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37114772 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2723579625 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 126 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2508981641 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3091159 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 978310045 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 415071720 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 97 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1266865295 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.980464 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.972855 # Number of insts issued each cycle +system.cpu.rename.skidInsts 121265991 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679360736 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255356957 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68007624 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36872048 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2723554804 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 129 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2508984537 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3092752 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 978311226 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 415025058 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 100 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1266766339 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.980621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.972970 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 426523141 33.67% 33.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201951837 15.94% 49.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185492394 14.64% 64.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153160708 12.09% 76.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133131866 10.51% 86.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81031270 6.40% 93.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65244416 5.15% 98.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15224722 1.20% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5104941 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 426534847 33.67% 33.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201890440 15.94% 49.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185333352 14.63% 64.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153215856 12.10% 76.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133163574 10.51% 86.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81070069 6.40% 93.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65235911 5.15% 98.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15218602 1.20% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5103688 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1266865295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1266766339 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2143481 11.64% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11871999 64.46% 76.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4401590 23.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2143232 11.63% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11878025 64.46% 76.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4404432 23.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643559437 65.51% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 106 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643533281 65.51% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 99 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 261 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 268 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 31 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 192 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 26 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued @@ -373,84 +373,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641411468 25.56% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224010136 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641423714 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224026917 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2508981641 # Type of FU issued -system.cpu.iq.rate 1.884268 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18417070 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007340 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6304440735 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3700781380 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2412589185 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1896071 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1214370 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 849902 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2526461544 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 937167 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62583251 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2508984537 # Type of FU issued +system.cpu.iq.rate 1.884482 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18425689 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007344 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6304354052 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3700755338 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2412575558 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1899802 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217218 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 851053 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2526471243 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 938983 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62590757 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234755127 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263530 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107682 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94622257 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234765073 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 264281 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 108176 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94628455 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 167 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1505929 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 156 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1505453 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116496134 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 45259128 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1153276 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2865598045 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8882954 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679350790 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255350759 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 126 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 296462 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17110 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107682 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10363121 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8561161 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18924282 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2461596227 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625038408 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47385414 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116498018 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45291754 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1153048 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2865571059 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8871235 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679360736 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255356957 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 129 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 296395 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17051 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 108176 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10360108 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8562955 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18923063 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2461579211 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625041270 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47405326 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142018294 # number of nop insts executed -system.cpu.iew.exec_refs 844427141 # number of memory reference insts executed -system.cpu.iew.exec_branches 300792164 # Number of branches executed -system.cpu.iew.exec_stores 219388733 # Number of stores executed -system.cpu.iew.exec_rate 1.848681 # Inst execution rate -system.cpu.iew.wb_sent 2441396740 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413439087 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388573479 # num instructions producing a value -system.cpu.iew.wb_consumers 1764243384 # num instructions consuming a value +system.cpu.iew.exec_nop 142016126 # number of nop insts executed +system.cpu.iew.exec_refs 844447329 # number of memory reference insts executed +system.cpu.iew.exec_branches 300798489 # Number of branches executed +system.cpu.iew.exec_stores 219406059 # Number of stores executed +system.cpu.iew.exec_rate 1.848876 # Inst execution rate +system.cpu.iew.wb_sent 2441376362 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413426611 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388583006 # num instructions producing a value +system.cpu.iew.wb_consumers 1764301470 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.812515 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.787065 # average fanout of values written-back +system.cpu.iew.wb_rate 1.812709 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.787044 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 824671147 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 824638318 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16085857 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1150369161 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.581910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.512649 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16087839 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1150268321 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.582048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.512804 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 636844570 55.36% 55.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174611268 15.18% 70.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86171312 7.49% 78.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53631613 4.66% 82.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34569452 3.01% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25367501 2.21% 87.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21831937 1.90% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22907604 1.99% 91.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94433904 8.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 636823398 55.36% 55.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174498580 15.17% 70.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86188355 7.49% 78.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53663047 4.67% 82.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34548846 3.00% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25343487 2.20% 87.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21850232 1.90% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22917524 1.99% 91.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94434852 8.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1150369161 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1150268321 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,189 +461,189 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94433904 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94434852 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3614607330 # The number of ROB reads -system.cpu.rob.rob_writes 5405498913 # The number of ROB writes -system.cpu.timesIdled 817784 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64676651 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3614472713 # The number of ROB reads +system.cpu.rob.rob_writes 5405435258 # The number of ROB writes +system.cpu.timesIdled 818038 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64625639 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.766998 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.766998 # CPI: Total CPI of All Threads -system.cpu.ipc 1.303785 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.303785 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3317361939 # number of integer regfile reads -system.cpu.int_regfile_writes 1931707111 # number of integer regfile writes -system.cpu.fp_regfile_reads 30073 # number of floating regfile reads -system.cpu.fp_regfile_writes 529 # number of floating regfile writes +system.cpu.cpi 0.766912 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.766912 # CPI: Total CPI of All Threads +system.cpu.ipc 1.303931 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.303931 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3317336179 # number of integer regfile reads +system.cpu.int_regfile_writes 1931663734 # number of integer regfile writes +system.cpu.fp_regfile_reads 30582 # number of floating regfile reads +system.cpu.fp_regfile_writes 562 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 776.168102 # Cycle average of tags in use -system.cpu.icache.total_refs 390786293 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 969 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 403288.228070 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 772.833210 # Cycle average of tags in use +system.cpu.icache.total_refs 390788277 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 406647.530697 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 776.168102 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.378988 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.378988 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 390786293 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 390786293 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 390786293 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 390786293 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 390786293 # number of overall hits -system.cpu.icache.overall_hits::total 390786293 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1474 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1474 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1474 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1474 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1474 # number of overall misses -system.cpu.icache.overall_misses::total 1474 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 87004499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 87004499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 87004499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 87004499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 87004499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 87004499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 390787767 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 390787767 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 390787767 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 390787767 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 390787767 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 390787767 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 772.833210 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.377360 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.377360 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 390788277 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 390788277 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 390788277 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 390788277 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 390788277 # number of overall hits +system.cpu.icache.overall_hits::total 390788277 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1461 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1461 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1461 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1461 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1461 # number of overall misses +system.cpu.icache.overall_misses::total 1461 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 84586499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 84586499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 84586499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 84586499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 84586499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 84586499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 390789738 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 390789738 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 390789738 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 390789738 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 390789738 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 390789738 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59026.118725 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59026.118725 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59026.118725 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59026.118725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59026.118725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59026.118725 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1157 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57896.303217 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 57896.303217 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 57896.303217 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 57896.303217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 57896.303217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 57896.303217 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1190 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 289.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 238 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 505 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 505 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 505 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 505 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75065.967304 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62721.362229 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75447.107254 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75440.836728 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62721.362229 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75447.107254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75440.836728 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214107 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214190 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61254.942768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75750.557143 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -652,180 +652,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019771 # number of writebacks -system.cpu.l2cache.writebacks::total 1019771 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190438 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191407 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775134 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775134 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 969 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50305.499484 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62988.955050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62982.705361 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214107 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214190 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48838.479709 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63300.969359 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63289.303810 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62472.130081 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62472.130081 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48838.479709 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62974.126429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62967.218526 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48838.479709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62974.126429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62967.218526 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176037 # number of replacements -system.cpu.dcache.tagsinuse 4087.525084 # Cycle average of tags in use -system.cpu.dcache.total_refs 694351222 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180133 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.636292 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9176040 # number of replacements +system.cpu.dcache.tagsinuse 4087.524129 # Cycle average of tags in use +system.cpu.dcache.total_refs 694346796 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180136 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.635785 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5069314000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.525084 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4087.524129 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997931 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997931 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538704902 # 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number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 518986048308 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 518986048308 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 549984845 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 549984845 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 519240752713 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 519240752713 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 519240752713 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 519240752713 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 549981274 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 549981274 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710713347 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710713347 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710713347 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710713347 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020510 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020510 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.031620 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023022 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023022 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023022 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023022 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26145.856854 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26145.856854 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44087.783760 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44087.783760 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710709776 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710709776 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710709776 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710709776 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020512 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020512 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031618 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031618 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023023 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023023 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023023 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023023 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26167.913100 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26167.913100 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44085.212756 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44085.212756 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31718.737826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31718.737826 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12309965 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5809756 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 734892 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.750713 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.196979 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31732.644407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31732.644407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31732.644407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31732.644407 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12246964 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5806156 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 735074 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.660859 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.140339 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3724718 # number of writebacks -system.cpu.dcache.writebacks::total 3724718 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3983366 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3983366 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198630 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3198630 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7181996 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7181996 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7181996 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7181996 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296577 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296577 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3724734 # number of writebacks +system.cpu.dcache.writebacks::total 3724734 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3984427 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3984427 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198422 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3198422 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7182849 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7182849 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7182849 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7182849 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296563 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883572 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883572 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180132 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180132 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180132 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180132 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159251608500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 159251608500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71602703007 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71602703007 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159317479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 159317479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71504257401 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71504257401 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 47500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 47500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230854311507 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230854311507 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230854311507 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230854311507 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230821736901 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230821736901 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230821736901 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230821736901 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013267 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013267 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.522913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.522913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38014.660048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38014.660048 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21834.592465 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21834.592465 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37962.051571 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37962.051571 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 47500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 47500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25143.610296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25143.610296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25143.610296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25143.610296 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 8f6283962..765d31514 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517371 # Number of seconds simulated -sim_ticks 517371024000 # Number of ticks simulated -final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517386 # Number of seconds simulated +sim_ticks 517386284000 # Number of ticks simulated +final_tick 517386284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139447 # Simulator instruction rate (inst/s) -host_op_rate 155563 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46709499 # Simulator tick rate (ticks/s) -host_mem_usage 485516 # Number of bytes of host memory used -host_seconds 11076.36 # Real time elapsed on the host +host_inst_rate 116249 # Simulator instruction rate (inst/s) +host_op_rate 129685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38940374 # Simulator tick rate (ticks/s) +host_mem_usage 515484 # Number of bytes of host memory used +host_seconds 13286.63 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143734144 # Number of bytes read from this memory -system.physmem.bytes_read::total 143782208 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70446784 # Number of bytes written to this memory -system.physmem.bytes_written::total 70446784 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245846 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246597 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100731 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100731 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277816378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 277909279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136162987 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136162987 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136162987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277816378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 414072265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246597 # Total number of read requests seen -system.physmem.writeReqs 1100731 # Total number of write requests seen -system.physmem.cpureqs 3350452 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143782208 # Total number of bytes read from memory -system.physmem.bytesWritten 70446784 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143782208 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70446784 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 642 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143753728 # Number of bytes read from this memory +system.physmem.bytes_read::total 143802048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70452928 # Number of bytes written to this memory +system.physmem.bytes_written::total 70452928 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2246152 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246907 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100827 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100827 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277846036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 277939428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93393 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93393 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136170846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136170846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136170846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277846036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 414110274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246907 # Total number of read requests seen +system.physmem.writeReqs 1100827 # Total number of write requests seen +system.physmem.cpureqs 3347751 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143802048 # Total number of bytes read from memory +system.physmem.bytesWritten 70452928 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143802048 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70452928 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 626 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 141495 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 139690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141749 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 142295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140068 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141091 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 140693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 138519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 136203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 141066 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 139208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 139271 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 141669 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69094 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 68448 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 69468 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 69338 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 69046 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 67828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 66957 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 69534 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 69263 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 69109 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 68653 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68959 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 141345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 139694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 142344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140081 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141241 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 140671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 138680 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 136252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140722 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 141030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 139261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 139241 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 141699 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69025 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 68435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 69463 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 69359 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 69032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68404 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 67870 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 66992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 69579 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 69317 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 69127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 68645 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 68513 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68932 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3124 # Number of times wr buffer was full causing retry -system.physmem.totGap 517370944500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times wr buffer was full causing retry +system.physmem.totGap 517386204500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246597 # Categorize read packet sizes +system.physmem.readPktSize::6 2246907 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1100731 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1563680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 451075 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 162592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100827 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1563682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 451240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,68 +124,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 44125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 44008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see -system.physmem.totQLat 51812524750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 131293078500 # Sum of mem lat for all requests -system.physmem.totBusLat 11229775000 # Total cycles spent in databus access -system.physmem.totBankLat 68250778750 # Total cycles spent in bank access -system.physmem.avgQLat 23069.26 # Average queueing delay per request -system.physmem.avgBankLat 30388.31 # Average bank access latency per request +system.physmem.totQLat 51773260500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 131271366750 # Sum of mem lat for all requests +system.physmem.totBusLat 11231405000 # Total cycles spent in databus access +system.physmem.totBankLat 68266701250 # Total cycles spent in bank access +system.physmem.avgQLat 23048.43 # Average queueing delay per request +system.physmem.avgBankLat 30390.99 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58457.57 # Average memory access latency -system.physmem.avgRdBW 277.91 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 136.16 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 277.91 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 136.16 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 58439.42 # Average memory access latency +system.physmem.avgRdBW 277.94 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 136.17 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 277.94 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 136.17 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.23 # Data bus utilization in percentage +system.physmem.busUtil 3.24 # Data bus utilization in percentage system.physmem.avgRdQLen 0.25 # Average read queue length over time -system.physmem.avgWrQLen 10.92 # Average write queue length over time -system.physmem.readRowHits 827855 # Number of row buffer hits during reads -system.physmem.writeRowHits 271156 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes -system.physmem.avgGap 154562.37 # Average gap between requests -system.cpu.branchPred.lookups 303290873 # Number of BP lookups -system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 174596633 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits +system.physmem.avgWrQLen 10.87 # Average write queue length over time +system.physmem.readRowHits 827731 # Number of row buffer hits during reads +system.physmem.writeRowHits 271594 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 24.67 # Row buffer hit rate for writes +system.physmem.avgGap 154548.18 # Average gap between requests +system.cpu.branchPred.lookups 303270186 # Number of BP lookups +system.cpu.branchPred.condPredicted 249470609 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15218764 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 173872286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161453824 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.481343 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.857711 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17556602 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 209 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,99 +229,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1034742049 # number of cpu cycles simulated +system.cpu.numCycles 1034772569 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303290873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155399906 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 380 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 288562414 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5732154 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 958634216 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.523474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.213325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 298199766 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2186256801 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303270186 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179010426 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435094842 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87837458 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155394915 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 268 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 288550611 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5724997 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 958581863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.523504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.213349 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 523513675 54.61% 54.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25518990 2.66% 57.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39095186 4.08% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48349741 5.04% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43010158 4.49% 70.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46440341 4.84% 75.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38425121 4.01% 79.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18710957 1.95% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175570047 18.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 523487088 54.61% 54.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25513973 2.66% 57.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39086986 4.08% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48352591 5.04% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43006673 4.49% 70.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46441362 4.84% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38409512 4.01% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18721015 1.95% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175562663 18.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 958634216 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.293108 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.112936 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 329763250 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 133666994 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405221512 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20079412 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69903048 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46058380 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2367190993 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2433 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69903048 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 353304996 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63447183 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15614 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400231748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71731627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2304653779 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 133097 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5040028 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58589233 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2280042978 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10643127773 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10643124880 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2893 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 958581863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293079 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.112790 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 329745900 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 133661747 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405202825 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20079986 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69891405 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46059780 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 688 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2367115109 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2459 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69891405 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 353286700 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63436503 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16572 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400214250 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71736433 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2304580712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133421 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5040530 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58596294 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2279975350 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10642754356 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10642751444 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2912 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 573723048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 497 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 494 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158827938 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624515157 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220983969 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86332349 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 71315853 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2201513470 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018112827 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4002858 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 473886256 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1126241029 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 958634216 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.105196 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906381 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 573655420 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 616 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 613 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158838581 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624481317 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220982521 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86134760 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71220480 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2201443562 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 640 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018130110 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4002265 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 473800004 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1125761712 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 470 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 958581863 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.105329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906457 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 277594004 28.96% 28.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151404549 15.79% 44.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161201477 16.82% 61.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119812250 12.50% 74.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123999377 12.94% 87.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73820536 7.70% 94.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38419650 4.01% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9808498 1.02% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2573875 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 277596353 28.96% 28.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151362321 15.79% 44.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161174547 16.81% 61.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119755421 12.49% 74.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124050787 12.94% 87.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73850082 7.70% 94.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38416449 4.01% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9807044 1.02% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2568859 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 958634216 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 958581863 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 872312 3.66% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5645 0.02% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 872338 3.65% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5545 0.02% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available @@ -349,13 +349,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18268766 76.62% 80.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4697940 19.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18290184 76.58% 80.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4715401 19.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236677496 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 926030 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236676135 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925418 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -377,90 +377,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 33 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 42 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587482532 29.11% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193026708 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587478696 29.11% 90.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193049790 9.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018112827 # Type of FU issued -system.cpu.iq.rate 1.950354 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23844663 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011815 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5022707128 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2675590256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957438118 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 556 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2041957357 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64629974 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018130110 # Type of FU issued +system.cpu.iq.rate 1.950313 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23883468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011834 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5022727533 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2675434216 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957455216 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 532 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042013436 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 142 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64634043 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138588388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 271831 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192988 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46136924 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138554548 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 275107 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 193018 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46135476 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4659196 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4656763 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69903048 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28888784 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1501235 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2201514122 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6139547 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624515157 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220983969 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 460 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 475783 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 89669 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192988 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8156378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9617829 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17774207 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988116656 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573901246 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29996171 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69891405 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28868892 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1502139 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2201444330 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6139194 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624481317 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220982521 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 578 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 475852 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 89903 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 193018 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8153538 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9615023 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17768561 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988122287 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573893211 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30007823 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 130 # number of nop insts executed -system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed -system.cpu.iew.exec_branches 238330373 # Number of branches executed -system.cpu.iew.exec_stores 190143920 # Number of stores executed -system.cpu.iew.exec_rate 1.921365 # Inst execution rate -system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957438221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296419261 # num instructions producing a value -system.cpu.iew.wb_consumers 2061223018 # num instructions consuming a value +system.cpu.iew.exec_nop 128 # number of nop insts executed +system.cpu.iew.exec_refs 764057589 # number of memory reference insts executed +system.cpu.iew.exec_branches 238332739 # Number of branches executed +system.cpu.iew.exec_stores 190164378 # Number of stores executed +system.cpu.iew.exec_rate 1.921313 # Inst execution rate +system.cpu.iew.wb_sent 1965900634 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957455330 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296412413 # num instructions producing a value +system.cpu.iew.wb_consumers 2061187346 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.891716 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628956 # average fanout of values written-back +system.cpu.iew.wb_rate 1.891677 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628964 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 478537797 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 478468669 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15221576 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 888731168 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.938802 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.727796 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15218100 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 888690458 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.938891 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727933 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 401249220 45.15% 45.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192209497 21.63% 66.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72554391 8.16% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35214687 3.96% 78.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19001350 2.14% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30768614 3.46% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20079948 2.26% 86.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11444333 1.29% 88.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106209128 11.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 401243318 45.15% 45.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192174198 21.62% 66.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72553521 8.16% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35226900 3.96% 78.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18988678 2.14% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30770684 3.46% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20065099 2.26% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11431293 1.29% 88.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106236767 11.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 888731168 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 888690458 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -471,70 +471,70 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106209128 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106236767 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2984133091 # The number of ROB reads -system.cpu.rob.rob_writes 4473274350 # The number of ROB writes -system.cpu.timesIdled 1017651 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76107833 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2983995614 # The number of ROB reads +system.cpu.rob.rob_writes 4473124072 # The number of ROB writes +system.cpu.timesIdled 1018062 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76190706 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.669925 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.669925 # CPI: Total CPI of All Threads -system.cpu.ipc 1.492703 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.492703 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956233395 # number of integer regfile reads -system.cpu.int_regfile_writes 1937436072 # number of integer regfile writes -system.cpu.fp_regfile_reads 98 # number of floating regfile reads -system.cpu.fp_regfile_writes 104 # number of floating regfile writes -system.cpu.misc_regfile_reads 737527238 # number of misc regfile reads +system.cpu.cpi 0.669945 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.669945 # CPI: Total CPI of All Threads +system.cpu.ipc 1.492659 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.492659 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956292181 # number of integer regfile reads +system.cpu.int_regfile_writes 1937433329 # number of integer regfile writes +system.cpu.fp_regfile_reads 115 # number of floating regfile reads +system.cpu.fp_regfile_writes 119 # number of floating regfile writes +system.cpu.misc_regfile_reads 737551848 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 625.709575 # Cycle average of tags in use -system.cpu.icache.total_refs 288561231 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 370425.200257 # Average number of references to valid blocks. +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.tagsinuse 627.796190 # Cycle average of tags in use +system.cpu.icache.total_refs 288549428 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 783 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 368517.787995 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 625.709575 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305522 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305522 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 288561231 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 288561231 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 288561231 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 288561231 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 288561231 # number of overall hits -system.cpu.icache.overall_hits::total 288561231 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 627.796190 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306541 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306541 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 288549428 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 288549428 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 288549428 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 288549428 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 288549428 # number of overall hits +system.cpu.icache.overall_hits::total 288549428 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1183 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1183 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1183 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1183 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1183 # number of overall misses system.cpu.icache.overall_misses::total 1183 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 68862000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 68862000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 68862000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 68862000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 68862000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 68862000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 288562414 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 288562414 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 288562414 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 288562414 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 288562414 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 288562414 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66818000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66818000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66818000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66818000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66818000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66818000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 288550611 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 288550611 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 288550611 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 288550611 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 288550611 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 288550611 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58209.636517 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58209.636517 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58209.636517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58209.636517 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56481.825866 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56481.825866 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56481.825866 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56481.825866 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56481.825866 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56481.825866 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 195 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -543,120 +543,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 65 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 404 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 404 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 404 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 404 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 779 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 779 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 779 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 779 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 779 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 779 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46813500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46813500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46813500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46813500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46813500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46813500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 400 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 400 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 400 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 400 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 400 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 783 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 783 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 783 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 783 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46629500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46629500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46629500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46629500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46629500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46629500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60094.351733 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60094.351733 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59552.362708 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59552.362708 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59552.362708 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59552.362708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59552.362708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59552.362708 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2213910 # number of replacements -system.cpu.l2cache.tagsinuse 31531.957469 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9247495 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2243685 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.121566 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2214216 # number of replacements +system.cpu.l2cache.tagsinuse 31531.914906 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9246344 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2243990 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.120493 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 20448147251 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14435.927117 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 20.343245 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17075.687107 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440550 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000621 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.521109 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.962279 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 14434.884106 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 20.460044 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17076.570756 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440518 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000624 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.521136 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.962278 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6290241 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6290268 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3781695 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3781695 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1066899 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1066899 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6289407 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6289434 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3781376 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3781376 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1066860 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1066860 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7357140 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7357167 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7356267 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7356294 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 27 # 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number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9602994 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9603773 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965340 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184086 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.184165 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965340 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.233870 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.233930 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965340 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82051.269806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82044.172855 # average overall miss latency +system.cpu.l2cache.overall_hits::cpu.data 7356267 # number of overall hits +system.cpu.l2cache.overall_hits::total 7356294 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 756 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1419505 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1420261 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826656 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826656 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 756 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2246161 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2246917 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 756 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233976 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233916 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233976 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60273.809524 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80148.534524 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80137.955277 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85268.415762 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85268.415762 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60273.809524 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82032.807532 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82025.486478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60273.809524 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82032.807532 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82025.486478 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -665,187 +665,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1100731 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36118599 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156391540883 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 156427659482 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184085 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184164 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233869 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419496 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1420251 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826656 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60227207126 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35881848 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156370756270 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156406638118 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35881848 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156370756270 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156406638118 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964240 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184137 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184216 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436572 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436572 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964240 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233975 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964240 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233975 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47525.626490 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67730.764401 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67720.023427 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72856.432574 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72856.432574 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47525.626490 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69617.174737 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69609.751591 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47525.626490 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69617.174737 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69609.751591 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 323000428500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 229631369718 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 229631369718 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 423500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 423500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 552631798218 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 552631798218 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 552631798218 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 552631798218 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500530116 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500530116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17015493 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17015493 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17015493 # number of overall misses +system.cpu.dcache.overall_misses::total 17015493 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 322799095500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 322799095500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 229643990242 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 229643990242 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 608000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 608000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 552443085742 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 552443085742 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 552443085742 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 552443085742 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500520613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500520613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 66 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 66 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673116163 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673116163 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673116163 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673116163 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025281 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025281 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025281 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025281 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28139.570735 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28139.570735 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389561 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389561 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 141166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 141166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32474.859624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32474.859624 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 26343962 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1054966 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1182360 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64552 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.280830 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16.342886 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673106660 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673106660 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673106660 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673106660 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045455 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045455 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025279 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025279 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025279 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025279 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28127.326131 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28127.326131 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41458.412097 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41458.412097 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 202666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 202666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32467.063149 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32467.063149 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32467.063149 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32467.063149 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26333844 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1054452 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1182092 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64550 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.277322 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16.335430 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781695 # number of writebacks -system.cpu.dcache.writebacks::total 3781695 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3769070 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3769070 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645155 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3645155 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3781376 # number of writebacks +system.cpu.dcache.writebacks::total 3781376 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767440 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3767440 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3645625 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7414225 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7414225 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7414225 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7414225 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709443 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7709443 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893551 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893551 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9602994 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9602994 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9602994 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9602994 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186232562000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 186232562000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83589909224 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83589909224 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269822471224 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 269822471224 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269822471224 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 269822471224 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7413065 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7413065 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7413065 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7413065 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708912 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708912 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893516 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893516 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602428 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602428 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602428 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602428 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186208076000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 186208076000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83587939217 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83587939217 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269796015217 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 269796015217 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269796015217 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 269796015217 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014266 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014266 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24156.422455 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24156.422455 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.524876 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.524876 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24154.910057 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24154.910057 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.300453 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.300453 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28096.645475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28096.645475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28096.645475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28096.645475 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |