diff options
Diffstat (limited to 'tests/long/se')
40 files changed, 4317 insertions, 4351 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 46194a700..358021124 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/gem5/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 5bcc38f1b..afe1d756a 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 18:59:47 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:34:09 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 8b98b78ac..650fe9ea1 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.164568 # Nu sim_ticks 164568389500 # Number of ticks simulated final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195675 # Simulator instruction rate (inst/s) -host_op_rate 206765 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56489453 # Simulator tick rate (ticks/s) -host_mem_usage 277972 # Number of bytes of host memory used -host_seconds 2913.26 # Real time elapsed on the host +host_inst_rate 61098 # Simulator instruction rate (inst/s) +host_op_rate 64561 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17638362 # Simulator tick rate (ticks/s) +host_mem_usage 233000 # Number of bytes of host memory used +host_seconds 9330.14 # Real time elapsed on the host sim_insts 570052720 # Number of instructions simulated sim_ops 602360926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 164 # Tr system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164568371500 # Total gap between requests +system.physmem.totGap 164568372500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 953340995 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1657962995 # Sum of mem lat for all requests +system.physmem.totQLat 953339495 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1657961495 # Sum of mem lat for all requests system.physmem.totBusLat 109328000 # Total cycles spent in databus access system.physmem.totBankLat 595294000 # Total cycles spent in bank access -system.physmem.avgQLat 34880.03 # Average queueing delay per request +system.physmem.avgQLat 34879.98 # Average queueing delay per request system.physmem.avgBankLat 21780.11 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 60660.14 # Average memory access latency +system.physmem.avgMemAccLat 60660.09 # Average memory access latency system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s @@ -191,7 +191,7 @@ system.physmem.readRowHits 17765 # Nu system.physmem.writeRowHits 1091 # Number of row buffer hits during writes system.physmem.readRowHitRate 65.00 # Row buffer hit rate for reads system.physmem.writeRowHitRate 43.00 # Row buffer hit rate for writes -system.physmem.avgGap 5509671.28 # Average gap between requests +system.physmem.avgGap 5509671.31 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -246,23 +246,23 @@ system.cpu.BPredUnit.BTBHits 46871026 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 1427560 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 1061 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68501011 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 68501012 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 666829693 # Number of instructions fetch has processed system.cpu.fetch.Branches 85146783 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 48298586 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 129620938 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 13095502 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119329475 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 119329476 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67084220 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 755001 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328178874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 67084221 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755002 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328178875 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.165282 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.193965 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198558185 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198558186 60.50% 60.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 20911289 6.37% 66.87% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 4967188 1.51% 68.39% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 14345258 4.37% 72.76% # Number of instructions fetched each cycle (Total) @@ -274,11 +274,11 @@ system.cpu.fetch.rateDist::8 60883054 18.55% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328178874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 328178875 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.258697 # Number of branch fetches per cycle system.cpu.fetch.rate 2.025996 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 92947684 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96199178 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 96199179 # Number of cycles decode is blocked system.cpu.decode.RunCycles 107899614 # Number of cycles decode is running system.cpu.decode.UnblockCycles 20406722 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 10725676 # Number of cycles decode is squashing @@ -290,19 +290,19 @@ system.cpu.rename.SquashCycles 10725676 # Nu system.cpu.rename.IdleCycles 107135136 # Number of cycles rename is idle system.cpu.rename.BlockCycles 14450172 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 44143 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114043084 # Number of cycles rename is running +system.cpu.rename.RunCycles 114043085 # Number of cycles rename is running system.cpu.rename.UnblockCycles 81780663 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694816427 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 694816428 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 59310091 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 20339427 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721301804 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230529001 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230528873 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 721301805 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230529005 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230528877 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93882615 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 93882616 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 2064 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 2020 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 170675831 # count of insts added to the skid buffer @@ -317,11 +317,11 @@ system.cpu.iq.iqSquashedInstsIssued 1370428 # Nu system.cpu.iq.iqSquashedInstsExamined 77447824 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 193234107 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328178874 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 328178875 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.967223 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.725262 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68164683 20.77% 20.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68164684 20.77% 20.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 85309693 25.99% 46.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 75934594 23.14% 69.90% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 40814180 12.44% 82.34% # Number of insts issued each cycle @@ -333,7 +333,7 @@ system.cpu.iq.issued_per_cycle::8 2116297 0.64% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328178874 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328178875 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 216945 5.75% 5.75% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available @@ -406,7 +406,7 @@ system.cpu.iq.FU_type_0::total 645601186 # Ty system.cpu.iq.rate 1.961498 # Inst issue rate system.cpu.iq.fu_busy_cnt 3772110 # FU busy when requested system.cpu.iq.fu_busy_rate 0.005843 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624523748 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 1624523749 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 757451010 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 637563052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -429,7 +429,7 @@ system.cpu.iew.iewSquashCycles 10725676 # Nu system.cpu.iew.iewBlockCycles 798492 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 92069 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 679994152 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 690727 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 690728 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 172202980 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 80458110 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1965 # Number of dispatched non-speculative instructions @@ -491,7 +491,7 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 977035801 # The number of ROB reads system.cpu.rob.rob_writes 1370761733 # The number of ROB writes system.cpu.timesIdled 41126 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 957906 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 957905 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570052720 # Number of Instructions Simulated system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated @@ -519,36 +519,36 @@ system.cpu.icache.demand_hits::cpu.inst 67083066 # nu system.cpu.icache.demand_hits::total 67083066 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 67083066 # number of overall hits system.cpu.icache.overall_hits::total 67083066 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses -system.cpu.icache.overall_misses::total 1154 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51351999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51351999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51351999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51351999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51351999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51351999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67084220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67084220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67084220 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67084220 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67084220 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67084220 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 1155 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1155 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1155 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1155 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1155 # number of overall misses +system.cpu.icache.overall_misses::total 1155 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51421999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51421999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51421999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51421999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51421999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51421999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67084221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67084221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67084221 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67084221 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67084221 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67084221 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44499.132582 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44499.132582 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44499.132582 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44499.132582 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44521.211255 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44521.211255 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44521.211255 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44521.211255 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -557,171 +557,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 38.428571 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 334 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47142.681707 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47142.681707 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47142.681707 # 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number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses -system.cpu.dcache.overall_misses::total 3714801 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159651000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5159651000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250551202 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40250551202 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # 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number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # 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average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12224.127807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12224.127807 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks -system.cpu.dcache.writebacks::total 421636 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060483756 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060483756 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.145796 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.145796 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.629975 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.629975 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2559 # number of replacements -system.cpu.l2cache.tagsinuse 22365.188889 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22365.188888 # Cycle average of tags in use system.cpu.l2cache.total_refs 517231 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 24170 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.399710 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 20763.498620 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 646.825200 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 646.825199 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 954.865069 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.633652 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.019740 # Average percentage of cache occupancy @@ -751,17 +625,17 @@ system.cpu.l2cache.demand_misses::total 27343 # nu system.cpu.l2cache.overall_misses::cpu.inst 739 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 26604 # number of overall misses system.cpu.l2cache.overall_misses::total 27343 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37001500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 728778000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 765779500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1545376000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1545376000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37001500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37000500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 728777500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 765778000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1545376500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1545376500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37000500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 2274154000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2311155500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37001500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 2311154500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37000500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 2274154000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2311155500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2311154500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 820 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197619 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198439 # number of ReadReq accesses(hits+misses) @@ -786,17 +660,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.061362 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.901220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.059814 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.061362 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50069.688769 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151387.203988 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 137903.745723 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70921.340064 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70921.340064 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50069.688769 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50068.335589 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151387.100125 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 137903.475599 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70921.363011 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70921.363011 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50068.335589 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84524.576674 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50069.688769 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84524.540102 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50068.335589 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84524.576674 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84524.540102 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -827,17 +701,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27332 system.cpu.l2cache.overall_mshr_misses::cpu.inst 736 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26596 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27332 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27342673 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668140562 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695483235 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273790796 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273790796 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27342673 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941931358 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1969274031 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27342673 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941931358 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1969274031 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27342173 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668139562 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695481735 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273791296 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273791296 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27342173 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941930858 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1969273031 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27342173 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941930858 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1969273031 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024320 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027928 # mshr miss rate for ReadReq accesses @@ -849,17 +723,143 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.061338 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059796 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.061338 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37150.370924 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139022.172701 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125493.185673 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.585865 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.585865 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37150.370924 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73015.918108 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72050.125531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37150.370924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.918108 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.125531 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37149.691576 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139021.964628 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125492.915013 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.608811 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.608811 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37149.691576 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73015.899308 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72050.088943 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37149.691576 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.899308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.088943 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 440681 # number of replacements +system.cpu.dcache.tagsinuse 4091.500678 # Cycle average of tags in use +system.cpu.dcache.total_refs 197565955 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444777 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 444.191033 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 320845000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4091.500678 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998902 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998902 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 131517978 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131517978 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66044747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66044747 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1676 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1676 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 197562725 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197562725 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197562725 # number of overall hits +system.cpu.dcache.overall_hits::total 197562725 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 342017 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 342017 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3372784 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3372784 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses +system.cpu.dcache.overall_misses::total 3714801 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159649500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5159649500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250552202 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 40250552202 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45410201702 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45410201702 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45410201702 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45410201702 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131859995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131859995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1698 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1698 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018456 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018456 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018456 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018456 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.944558 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.944558 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.925268 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.925268 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12224.127673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12224.127673 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks +system.cpu.dcache.writebacks::total 421636 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060484256 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060484256 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.143266 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.143266 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.631998 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.631998 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 48dcd7446..a8742bbf7 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -116,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -132,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -426,21 +422,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -463,21 +454,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -504,7 +490,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip +executable=/gem5/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 10b614f5f..4ff3426c2 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:11:57 -gem5 started Oct 30 2012 14:00:44 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:16:54 +gem5 started Jan 4 2013 22:00:02 +gem5 executing on u200540 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 387281648500 because target called exit() +Exiting @ tick 387279743500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index c74d8b444..14b499f19 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387282 # Number of seconds simulated -sim_ticks 387281648500 # Number of ticks simulated -final_tick 387281648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387280 # Number of seconds simulated +sim_ticks 387279743500 # Number of ticks simulated +final_tick 387279743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171377 # Simulator instruction rate (inst/s) -host_op_rate 171918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47367883 # Simulator tick rate (ticks/s) -host_mem_usage 224920 # Number of bytes of host memory used -host_seconds 8176.04 # Real time elapsed on the host +host_inst_rate 70741 # Simulator instruction rate (inst/s) +host_op_rate 70964 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19552386 # Simulator tick rate (ticks/s) +host_mem_usage 225936 # Number of bytes of host memory used +host_seconds 19807.29 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678464 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76608 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 76416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678400 # Number of bytes read from this memory +system.physmem.bytes_read::total 1754816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76416 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1197 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26226 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1194 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26225 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27419 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4333962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4531772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197810 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197810 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418589 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418589 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4333962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4950361 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27424 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4333818 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4531133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4333818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4949724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27420 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755072 # Total number of bytes read from memory +system.physmem.cpureqs 29953 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1754816 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1754816 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1698 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1715 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1714 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1803 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1696 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1667 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1745 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1746 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1621 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 158 # Tr system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387281620500 # Total gap between requests +system.physmem.totGap 387279715500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27424 # Categorize read packet sizes +system.physmem.readPktSize::6 27420 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,9 +105,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5215 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 916 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 722664308 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1404176308 # Sum of mem lat for all requests -system.physmem.totBusLat 109696000 # Total cycles spent in databus access -system.physmem.totBankLat 571816000 # Total cycles spent in bank access -system.physmem.avgQLat 26351.53 # Average queueing delay per request -system.physmem.avgBankLat 20850.93 # Average bank access latency per request +system.physmem.totQLat 724473296 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1405549296 # Sum of mem lat for all requests +system.physmem.totBusLat 109680000 # Total cycles spent in databus access +system.physmem.totBankLat 571396000 # Total cycles spent in bank access +system.physmem.avgQLat 26421.35 # Average queueing delay per request +system.physmem.avgBankLat 20838.66 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 51202.46 # Average memory access latency +system.physmem.avgMemAccLat 51260.00 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s @@ -186,148 +186,148 @@ system.physmem.avgConsumedWrBW 0.42 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 17.43 # Average write queue length over time -system.physmem.readRowHits 18322 # Number of row buffer hits during reads -system.physmem.writeRowHits 1102 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.51 # Row buffer hit rate for writes -system.physmem.avgGap 12927917.36 # Average gap between requests +system.physmem.avgWrQLen 17.06 # Average write queue length over time +system.physmem.readRowHits 18324 # Number of row buffer hits during reads +system.physmem.writeRowHits 1098 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.35 # Row buffer hit rate for writes +system.physmem.avgGap 12929580.19 # Average gap between requests system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774563298 # number of cpu cycles simulated +system.cpu.numCycles 774559488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 97756783 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88046378 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3616115 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 65822232 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65492473 # Number of BTB hits +system.cpu.BPredUnit.lookups 97757265 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88048400 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3615880 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 65812942 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65493412 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1334 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 164852368 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642212446 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97756783 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65493807 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329195647 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20823123 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263322100 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2527 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 1346 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 164857001 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642241879 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97757265 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65494758 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329201347 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20830567 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263300608 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2484 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161933661 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 734964 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774355546 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126740 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 161939590 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 736919 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774350695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126792 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146705 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445159899 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74061304 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37898461 4.89% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9077519 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28105677 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18773272 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11484924 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3792333 0.49% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146002157 18.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445149348 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74062635 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37899346 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9077460 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28106060 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18772938 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11486101 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3791039 0.49% 81.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146005768 18.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774355546 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126209 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.120178 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 215883064 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214466469 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284208572 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42814616 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16982825 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636500589 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16982825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239715972 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36727743 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52434063 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302057850 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126437093 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625611071 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30924044 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73480825 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3128707 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356294088 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746297990 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712224165 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34073825 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774350695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.120227 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 215923264 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214411776 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284212483 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42813992 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16989180 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636523306 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16989180 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239767996 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36725834 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52426044 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302047092 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126394549 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625641256 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 163 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30927570 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73422293 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3124815 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356325471 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746325758 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712253189 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34072569 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111523649 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2645349 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2664178 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271657434 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436922066 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179745095 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254298230 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83339884 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512454597 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2610820 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459325981 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53748 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109158045 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130052751 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 367149 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774355546 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884568 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.432012 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111555032 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2644888 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2664020 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271706062 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436927389 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179744218 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254493315 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83217297 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512489363 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2610612 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459355655 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53704 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109193723 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130058810 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 366941 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774350695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884619 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431536 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145671235 18.81% 18.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184692846 23.85% 42.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209497548 27.05% 69.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131299597 16.96% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70722781 9.13% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20304331 2.62% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8026000 1.04% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3959195 0.51% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 182013 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145647727 18.81% 18.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184570267 23.84% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209695290 27.08% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131219118 16.95% 86.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70710319 9.13% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20417492 2.64% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8005951 1.03% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3903236 0.50% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181295 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774355546 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774350695 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 90752 5.46% 5.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95014 5.72% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1160014 69.81% 80.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 315922 19.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 116724 6.93% 6.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95410 5.66% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1152580 68.43% 81.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 319525 18.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866438962 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866464141 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644873 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644770 0.18% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued @@ -353,84 +353,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419117163 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171124983 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419120072 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171126672 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459325981 # Type of FU issued -system.cpu.iq.rate 1.884063 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1661702 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3676896998 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615267495 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443201042 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17825960 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9193607 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8546616 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451866721 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9120962 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215450617 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459355655 # Type of FU issued +system.cpu.iq.rate 1.884110 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1684239 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001154 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3676971209 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615339802 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443231270 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17828739 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9193054 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8547507 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451917046 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9122848 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215321036 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34409223 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 57798 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 244556 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12896953 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34414546 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58846 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 246003 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12896076 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3310 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 91608 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3349 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 91624 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16982825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3082295 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 247112 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608751818 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4125389 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436922066 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179745095 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2527727 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 148822 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1680 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 244556 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2270064 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1474247 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3744311 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454009970 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416570645 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5316011 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16989180 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3081240 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 246114 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608786135 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4123964 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436927389 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179744218 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2527628 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 148187 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1651 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 246003 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2270880 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473539 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3744419 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454037467 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416573795 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5318188 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93686401 # number of nop insts executed -system.cpu.iew.exec_refs 587021920 # number of memory reference insts executed -system.cpu.iew.exec_branches 89037548 # Number of branches executed -system.cpu.iew.exec_stores 170451275 # Number of stores executed -system.cpu.iew.exec_rate 1.877200 # Inst execution rate -system.cpu.iew.wb_sent 1452636193 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451747658 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153420359 # num instructions producing a value -system.cpu.iew.wb_consumers 1204679279 # num instructions consuming a value +system.cpu.iew.exec_nop 93686160 # number of nop insts executed +system.cpu.iew.exec_refs 587024674 # number of memory reference insts executed +system.cpu.iew.exec_branches 89036390 # Number of branches executed +system.cpu.iew.exec_stores 170450879 # Number of stores executed +system.cpu.iew.exec_rate 1.877244 # Inst execution rate +system.cpu.iew.wb_sent 1452666848 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451778777 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153445523 # num instructions producing a value +system.cpu.iew.wb_consumers 1204705379 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874279 # insts written-back per cycle +system.cpu.iew.wb_rate 1.874328 # insts written-back per cycle system.cpu.iew.wb_fanout 0.957450 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119133058 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119167265 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3616115 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757373332 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966696 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509453 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3615880 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757361515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966727 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509795 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 239955150 31.68% 31.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275777678 36.41% 68.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42556583 5.62% 73.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54728215 7.23% 80.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19718156 2.60% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13293088 1.76% 85.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30577311 4.04% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10491345 1.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70275806 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240009654 31.69% 31.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275743732 36.41% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42570119 5.62% 73.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54687779 7.22% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19671272 2.60% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13286277 1.75% 85.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30573058 4.04% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10535838 1.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70283786 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757373332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757361515 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,192 +441,192 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70275806 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70283786 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295688996 # The number of ROB reads -system.cpu.rob.rob_writes 3234318218 # The number of ROB writes -system.cpu.timesIdled 25993 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 207752 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295703406 # The number of ROB reads +system.cpu.rob.rob_writes 3234392884 # The number of ROB writes +system.cpu.timesIdled 26078 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 208793 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552790 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552790 # CPI: Total CPI of All Threads -system.cpu.ipc 1.809005 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.809005 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979115545 # number of integer regfile reads -system.cpu.int_regfile_writes 1275157860 # number of integer regfile writes -system.cpu.fp_regfile_reads 16963296 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491838 # number of floating regfile writes -system.cpu.misc_regfile_reads 592677531 # number of misc regfile reads +system.cpu.cpi 0.552787 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552787 # CPI: Total CPI of All Threads +system.cpu.ipc 1.809014 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.809014 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979140277 # number of integer regfile reads +system.cpu.int_regfile_writes 1275189089 # number of integer regfile writes +system.cpu.fp_regfile_reads 16965348 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491584 # number of floating regfile writes +system.cpu.misc_regfile_reads 592679771 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 190 # number of replacements -system.cpu.icache.tagsinuse 1035.892325 # Cycle average of tags in use -system.cpu.icache.total_refs 161931728 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1331 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121661.703982 # Average number of references to valid blocks. +system.cpu.icache.replacements 200 # number of replacements +system.cpu.icache.tagsinuse 1035.695786 # Cycle average of tags in use +system.cpu.icache.total_refs 161937647 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121029.631540 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.892325 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505807 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505807 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161931728 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161931728 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161931728 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161931728 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161931728 # number of overall hits -system.cpu.icache.overall_hits::total 161931728 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1933 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1933 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1933 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1933 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1933 # number of overall misses -system.cpu.icache.overall_misses::total 1933 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 80019500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 80019500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 80019500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 80019500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 80019500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 80019500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161933661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161933661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161933661 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161933661 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161933661 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161933661 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.695786 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505711 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505711 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161937647 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161937647 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161937647 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161937647 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161937647 # number of overall hits +system.cpu.icache.overall_hits::total 161937647 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1943 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1943 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1943 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1943 # number of overall misses +system.cpu.icache.overall_misses::total 1943 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81333500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81333500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81333500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81333500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81333500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81333500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161939590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161939590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161939590 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161939590 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161939590 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161939590 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41396.533885 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41396.533885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41396.533885 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41396.533885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41396.533885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41396.533885 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41859.752959 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41859.752959 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41859.752959 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41859.752959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41859.752959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41859.752959 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 601 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 601 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 601 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 601 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 601 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 601 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1332 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1332 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1332 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1332 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1332 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58461000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 58461000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58461000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 58461000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58461000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 58461000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59309500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59309500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59309500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59309500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59309500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59309500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43889.639640 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43889.639640 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43889.639640 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43889.639640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43889.639640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43889.639640 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44293.876027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44293.876027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44293.876027 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 44293.876027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44293.876027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 44293.876027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22450.499541 # Cycle average of tags in use -system.cpu.l2cache.total_refs 550174 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24271 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.667958 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22451.919806 # Cycle average of tags in use +system.cpu.l2cache.total_refs 550398 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24266 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.681859 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20742.731551 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1060.708507 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 647.059483 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633018 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.032370 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019747 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.685135 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 134 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 196304 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 196438 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 443776 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 647.177496 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.633057 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.032371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019750 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.685178 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 144 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 196423 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 196567 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 443928 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 443928 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 240651 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 240651 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 144 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47291.631799 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76986.863680 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75692.706054 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,178 +637,178 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks system.cpu.l2cache.writebacks::total 2533 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1198 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4435 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1195 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022095 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083018 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083018 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.892457 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056605 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059014 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.892457 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056605 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059014 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34704.553975 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93077.228031 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80693.889579 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58615.991004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58615.991004 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34704.553975 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64447.791573 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63151.541794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34704.553975 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64447.791573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63151.541794 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459017 # number of replacements -system.cpu.dcache.tagsinuse 4093.828969 # Cycle average of tags in use -system.cpu.dcache.total_refs 365038721 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463113 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 788.228188 # Average number of references to valid blocks. +system.cpu.dcache.replacements 459203 # number of replacements +system.cpu.dcache.tagsinuse 4093.828957 # Cycle average of tags in use +system.cpu.dcache.total_refs 365170885 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463299 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 788.197007 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 342772000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.828969 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4093.828957 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999470 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999470 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200081459 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200081459 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164955943 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164955943 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 200214093 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200214093 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955473 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955473 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365037402 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365037402 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365037402 # number of overall hits -system.cpu.dcache.overall_hits::total 365037402 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 927524 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 927524 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1890873 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1890873 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365169566 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365169566 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365169566 # number of overall hits +system.cpu.dcache.overall_hits::total 365169566 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 927691 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 927691 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1891343 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1891343 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2818397 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2818397 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2818397 # number of overall misses -system.cpu.dcache.overall_misses::total 2818397 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14988914500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14988914500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31918196457 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31918196457 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2819034 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2819034 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2819034 # number of overall misses +system.cpu.dcache.overall_misses::total 2819034 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14988091500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14988091500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31927965942 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31927965942 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46907110957 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46907110957 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46907110957 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46907110957 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201008983 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201008983 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 46916057442 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46916057442 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46916057442 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46916057442 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201141784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201141784 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 367855799 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 367855799 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 367855799 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 367855799 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004614 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004614 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011333 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011333 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 367988600 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 367988600 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 367988600 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 367988600 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004612 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004612 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007662 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007662 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007662 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007662 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16160.136557 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16160.136557 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16880.137617 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16880.137617 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.007661 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007661 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007661 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007661 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16156.340312 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16156.340312 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16881.108261 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16881.108261 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16643.187939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16643.187939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 574305 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35651 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.109085 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16642.600778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16642.600778 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 573681 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35664 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.085717 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443776 # number of writebacks -system.cpu.dcache.writebacks::total 443776 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726784 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 726784 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628507 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628507 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2355291 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2355291 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2355291 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2355291 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200740 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200740 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262366 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262366 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443928 # number of writebacks +system.cpu.dcache.writebacks::total 443928 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726830 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 726830 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628912 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628912 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2355742 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2355742 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2355742 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2355742 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200861 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200861 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262431 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262431 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463106 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463106 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463106 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463106 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2634282500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2634282500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319277500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319277500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 463292 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463292 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463292 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463292 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2635998000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2635998000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319921000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319921000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6953560000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6953560000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6953560000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6953560000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6955919000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6955919000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6955919000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6955919000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001572 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13122.857926 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13122.857926 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16462.794341 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16462.794341 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13123.493361 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13123.493361 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16461.168841 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16461.168841 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index e5a53f4f2..0e20d1517 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -433,21 +430,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -464,6 +456,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -483,21 +478,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -524,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/gem5/dist/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 22f96a7fe..c000af4ff 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2012 00:35:18 -gem5 started Dec 30 2012 00:35:30 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jan 4 2013 21:20:54 +gem5 started Jan 4 2013 22:11:32 +gem5 executing on u200540 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 63873cca1..6e46a8347 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.607446 # Nu sim_ticks 607445544000 # Number of ticks simulated final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57635 # Simulator instruction rate (inst/s) -host_op_rate 106195 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39782943 # Simulator tick rate (ticks/s) -host_mem_usage 279268 # Number of bytes of host memory used -host_seconds 15268.99 # Real time elapsed on the host +host_inst_rate 35384 # Simulator instruction rate (inst/s) +host_op_rate 65197 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24424271 # Simulator tick rate (ticks/s) +host_mem_usage 239876 # Number of bytes of host memory used +host_seconds 24870.57 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 156 # Tr system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 607445529000 # Total gap between requests +system.physmem.totGap 607445530000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 68456169 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 822256169 # Sum of mem lat for all requests +system.physmem.totQLat 68456669 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 822256669 # Sum of mem lat for all requests system.physmem.totBusLat 109436000 # Total cycles spent in databus access system.physmem.totBankLat 644364000 # Total cycles spent in bank access -system.physmem.avgQLat 2502.14 # Average queueing delay per request +system.physmem.avgQLat 2502.16 # Average queueing delay per request system.physmem.avgBankLat 23552.18 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30054.32 # Average memory access latency +system.physmem.avgMemAccLat 30054.34 # Average memory access latency system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s @@ -191,7 +191,7 @@ system.physmem.readRowHits 17697 # Nu system.physmem.writeRowHits 1084 # Number of row buffer hits during writes system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes -system.physmem.avgGap 20320661.33 # Average gap between requests +system.physmem.avgGap 20320661.36 # Average gap between requests system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1214891089 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -204,22 +204,22 @@ system.cpu.BPredUnit.BTBHits 84079165 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 179135724 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 84079165 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 399080479 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 88232216 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 574634439 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 574634441 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 187842502 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11743850 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1214538068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 187842503 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11743851 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1214538070 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.059666 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.253312 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 822675210 67.74% 67.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 822675212 67.74% 67.74% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 26883309 2.21% 69.95% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 13192065 1.09% 71.04% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 20566257 1.69% 72.73% # Number of instructions fetched each cycle (Total) @@ -231,18 +231,18 @@ system.cpu.fetch.rateDist::8 215850749 17.77% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1214538068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1214538070 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.130370 # Number of branch fetches per cycle system.cpu.fetch.rate 1.200462 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 288247470 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497953946 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 497953948 # Number of cycles decode is blocked system.cpu.decode.RunCycles 274080522 # Number of cycles decode is running system.cpu.decode.UnblockCycles 92569137 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 61686993 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 2343830219 # Number of instructions handled by decode system.cpu.rename.SquashCycles 61686993 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 336887109 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124143934 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 124143936 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2487 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 304057721 # Number of cycles rename is running system.cpu.rename.UnblockCycles 387759824 # Number of cycles rename is unblocking @@ -270,11 +270,11 @@ system.cpu.iq.iqSquashedInstsIssued 243450 # Nu system.cpu.iq.iqSquashedInstsExamined 372613756 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 761627172 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 239 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1214538068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1214538070 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.468938 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.421549 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 360345167 29.67% 29.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360345169 29.67% 29.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 364336445 30.00% 59.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 234287346 19.29% 78.96% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 141446603 11.65% 90.60% # Number of insts issued each cycle @@ -286,7 +286,7 @@ system.cpu.iq.issued_per_cycle::8 597279 0.05% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1214538068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1214538070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 437572 15.09% 15.09% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 15.09% # attempts to use FU when none available @@ -359,7 +359,7 @@ system.cpu.iq.FU_type_0::total 1784080761 # Ty system.cpu.iq.rate 1.468511 # Inst issue rate system.cpu.iq.fu_busy_cnt 2900605 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4785843295 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 4785843297 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2367295034 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1724820361 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 350 # Number of floating instruction queue reads @@ -379,7 +379,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 2481 # system.cpu.iew.lsq.thread0.cacheBlocked 68 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 61686993 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1142263 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 1142265 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 110648 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 1994506717 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 63004482 # Number of squashed instructions skipped by dispatch @@ -412,11 +412,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 373014217 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 26390469 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1152851075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 1152851077 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.406508 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.830012 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 418199685 36.28% 36.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 418199687 36.28% 36.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 415017727 36.00% 72.27% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 87014149 7.55% 79.82% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 122172880 10.60% 90.42% # Number of insts commited each cycle @@ -428,7 +428,7 @@ system.cpu.commit.committed_per_cycle::8 32432091 2.81% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1152851075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1152851077 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493926 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,10 +441,10 @@ system.cpu.commit.int_insts 1621354437 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 32432091 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3114927127 # The number of ROB reads +system.cpu.rob.rob_reads 3114927129 # The number of ROB reads system.cpu.rob.rob_writes 4050738571 # The number of ROB writes system.cpu.timesIdled 58873 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 353021 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 353019 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493926 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated @@ -471,36 +471,36 @@ system.cpu.icache.demand_hits::cpu.inst 187841119 # nu system.cpu.icache.demand_hits::total 187841119 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 187841119 # number of overall hits system.cpu.icache.overall_hits::total 187841119 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1383 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1383 # number of overall misses -system.cpu.icache.overall_misses::total 1383 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64282500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64282500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64282500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64282500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64282500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64282500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 187842502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 187842502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 187842502 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 187842502 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 187842502 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 187842502 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 1384 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1384 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1384 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1384 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1384 # number of overall misses +system.cpu.icache.overall_misses::total 1384 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64353500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64353500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64353500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64353500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64353500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64353500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 187842503 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 187842503 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 187842503 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 187842503 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 187842503 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 187842503 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46480.477223 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46480.477223 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46480.477223 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46480.477223 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46480.477223 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46480.477223 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46498.193642 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46498.193642 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46498.193642 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46498.193642 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -509,12 +509,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 40.600000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 465 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 465 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 465 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 465 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 465 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 466 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 466 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 466 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 466 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 466 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 466 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 918 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 918 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 918 # number of demand (read+write) MSHR misses @@ -540,114 +540,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50259.259259 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50259.259259 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50259.259259 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 446019 # number of replacements -system.cpu.dcache.tagsinuse 4092.902027 # Cycle average of tags in use -system.cpu.dcache.total_refs 452395605 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 450115 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1005.066716 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 828955000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4092.902027 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999244 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999244 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264455973 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264455973 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939624 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939624 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452395597 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452395597 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452395597 # 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number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7079925499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7079925499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7079925499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7079925499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264667108 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264667108 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452853166 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452853166 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452853166 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16490.618174 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15472.913373 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15472.913373 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15472.913373 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15472.913373 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 474 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.875000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428963 # number of writebacks -system.cpu.dcache.writebacks::total 428963 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7361 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7361 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 84 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 84 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7445 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7445 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7445 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7445 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203774 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246350 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246350 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 450124 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 450124 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 450124 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 450124 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523541000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523541000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3570237499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3570237499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6093778499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6093778499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6093778499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6093778499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12384.018570 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12384.018570 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14492.541096 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14492.541096 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13537.999527 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13537.999527 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13537.999527 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13537.999527 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements system.cpu.l2cache.tagsinuse 22259.528577 # Cycle average of tags in use system.cpu.l2cache.total_refs 531228 # Total number of references to valid blocks. @@ -655,7 +547,7 @@ system.cpu.l2cache.sampled_refs 24191 # Sa system.cpu.l2cache.avg_refs 21.959737 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 20782.488903 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 799.212801 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 799.212802 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 677.826873 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.634231 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.024390 # Average percentage of cache occupancy @@ -688,16 +580,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 902 # system.cpu.l2cache.overall_misses::cpu.data 26457 # number of overall misses system.cpu.l2cache.overall_misses::total 27359 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45120000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325819500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 370939500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079318500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1079318500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325819000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 370939000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079319500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1079319500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 45120000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1405138000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1450258000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1405138500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1450258500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 45120000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1405138000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1450258000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1405138500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1450258500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 910 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 203769 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 204679 # number of ReadReq accesses(hits+misses) @@ -725,16 +617,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991209 system.cpu.l2cache.overall_miss_rate::cpu.data 0.058778 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.060659 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50022.172949 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71451.644737 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67912.760893 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49290.701923 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49290.701923 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71451.535088 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67912.669352 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49290.747591 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49290.747591 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50022.172949 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53110.254375 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53008.443291 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53110.273274 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53008.461567 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50022.172949 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53110.254375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53008.443291 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53110.273274 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53008.461567 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -756,16 +648,16 @@ system.cpu.l2cache.demand_mshr_misses::total 27359 system.cpu.l2cache.overall_mshr_misses::cpu.inst 902 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26457 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27359 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33761933 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267685448 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301447381 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 796656102 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 796656102 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33761933 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064341550 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33761433 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267684948 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301446381 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 796657102 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 796657102 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33761433 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064342050 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 1098103483 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33761933 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064341550 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33761433 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064342050 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 1098103483 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991209 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022378 # mshr miss rate for ReadReq accesses @@ -778,17 +670,125 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.060659 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991209 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058778 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.060659 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37430.080931 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58702.949123 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55189.926950 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36381.974791 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36381.974791 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37430.080931 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40229.109498 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37429.526608 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58702.839474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55189.743867 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36382.020459 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36382.020459 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37429.526608 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40229.128397 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40136.828210 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37430.080931 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40229.109498 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37429.526608 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40229.128397 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40136.828210 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 446019 # number of replacements +system.cpu.dcache.tagsinuse 4092.902027 # Cycle average of tags in use +system.cpu.dcache.total_refs 452395605 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 450115 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1005.066716 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 828955000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.902027 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999244 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999244 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264455973 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264455973 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939624 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939624 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452395597 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452395597 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452395597 # number of overall hits +system.cpu.dcache.overall_hits::total 452395597 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 211135 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 211135 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246434 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246434 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 457569 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 457569 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 457569 # number of overall misses +system.cpu.dcache.overall_misses::total 457569 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3016076000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3016076000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4063849999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4063849999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7079925999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7079925999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7079925999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7079925999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264667108 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264667108 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 452853166 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452853166 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452853166 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452853166 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001310 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14285.059322 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14285.059322 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16490.622232 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16490.622232 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15472.914465 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15472.914465 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 474 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.875000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 428963 # number of writebacks +system.cpu.dcache.writebacks::total 428963 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7361 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7361 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 84 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 84 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7445 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7445 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7445 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7445 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203774 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246350 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246350 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450124 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450124 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450124 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450124 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523540500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523540500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3570238499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3570238499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6093778999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6093778999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6093778999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6093778999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12384.016116 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12384.016116 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14492.545155 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14492.545155 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index f5f3830e6..80bca85f9 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,9 +522,9 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/gem5/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 15ba3aa9f..73d194ff5 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 19:23:29 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:47:37 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index fae2b58b3..48597bbbd 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026786 # Nu sim_ticks 26786364500 # Number of ticks simulated final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184396 # Simulator instruction rate (inst/s) -host_op_rate 185720 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54518089 # Simulator tick rate (ticks/s) -host_mem_usage 410024 # Number of bytes of host memory used -host_seconds 491.33 # Real time elapsed on the host +host_inst_rate 55091 # Simulator instruction rate (inst/s) +host_op_rate 55487 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16288150 # Simulator tick rate (ticks/s) +host_mem_usage 365372 # Number of bytes of host memory used +host_seconds 1644.53 # Real time elapsed on the host sim_insts 90599358 # Number of instructions simulated sim_ops 91249911 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26786185500 # Total gap between requests +system.physmem.totGap 26786186500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 45050979 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 279102979 # Sum of mem lat for all requests +system.physmem.totQLat 45051479 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 279103479 # Sum of mem lat for all requests system.physmem.totBusLat 62048000 # Total cycles spent in databus access system.physmem.totBankLat 172004000 # Total cycles spent in bank access -system.physmem.avgQLat 2904.27 # Average queueing delay per request +system.physmem.avgQLat 2904.30 # Average queueing delay per request system.physmem.avgBankLat 11088.45 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 17992.71 # Average memory access latency +system.physmem.avgMemAccLat 17992.75 # Average memory access latency system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s @@ -184,7 +184,7 @@ system.physmem.readRowHits 15087 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1726804.12 # Average gap between requests +system.physmem.avgGap 1726804.18 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -239,23 +239,23 @@ system.cpu.BPredUnit.BTBHits 11281654 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14169802 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 14169803 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11256916 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 11256917 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13841949 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329938 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53360207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13841950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53360208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29366337 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29366338 55.03% 55.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total) @@ -267,11 +267,11 @@ system.cpu.fetch.rateDist::8 9833914 18.43% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53360207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 53360208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9104448 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 9104449 # Number of cycles decode is blocked system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing @@ -283,19 +283,19 @@ system.cpu.rename.SquashCycles 3892391 # Nu system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21547168 # Number of cycles rename is running +system.cpu.rename.RunCycles 21547169 # Number of cycles rename is running system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123140443 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 123140444 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143600920 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536395589 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536390601 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 143600921 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536395593 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536390605 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36171438 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 36171439 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer @@ -310,11 +310,11 @@ system.cpu.iq.iqSquashedInstsIssued 79722 # Nu system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53360207 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 53360208 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15336122 28.74% 28.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15336123 28.74% 28.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle @@ -326,7 +326,7 @@ system.cpu.iq.issued_per_cycle::8 445093 0.83% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53360207 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53360208 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available @@ -399,7 +399,7 @@ system.cpu.iq.FU_type_0::total 105160593 # Ty system.cpu.iq.rate 1.962950 # Inst issue rate system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264421445 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 264421446 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads @@ -422,7 +422,7 @@ system.cpu.iew.iewSquashCycles 3892391 # Nu system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309093 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 309094 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions @@ -484,7 +484,7 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 162359257 # The number of ROB reads system.cpu.rob.rob_writes 240263976 # The number of ROB writes system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 212523 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 212522 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90599358 # Number of Instructions Simulated system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated @@ -513,36 +513,36 @@ system.cpu.icache.demand_hits::cpu.inst 13840965 # nu system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits system.cpu.icache.overall_hits::total 13840965 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses -system.cpu.icache.overall_misses::total 983 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48291499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48291499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48291499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48291499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48291499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48291499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13841948 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13841948 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13841948 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13841948 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13841948 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13841948 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses +system.cpu.icache.overall_misses::total 984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48362499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48362499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48362499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48362499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48362499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48362499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13841949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13841949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13841949 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13841949 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13841949 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13841949 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49126.652085 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49126.652085 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49126.652085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49126.652085 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49148.881098 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49148.881098 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49148.881098 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49148.881098 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked @@ -551,12 +551,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 122.111111 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses @@ -582,132 +582,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943495 # number of replacements -system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use -system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits -system.cpu.dcache.overall_hits::total 28133775 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses -system.cpu.dcache.overall_misses::total 1370806 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks -system.cpu.dcache.writebacks::total 942892 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks. @@ -750,16 +624,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 708 # system.cpu.l2cache.overall_misses::cpu.data 14815 # number of overall misses system.cpu.l2cache.overall_misses::total 15523 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14541500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 50282500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14542000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 50283000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 602811500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 602811500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 35741000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 617353000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 653094000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 617353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 653094500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 35741000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 617353000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 653094000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 617353500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 653094500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 735 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 904075 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904810 # number of ReadReq accesses(hits+misses) @@ -789,16 +663,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963265 system.cpu.l2cache.overall_miss_rate::cpu.data 0.015634 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016369 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50481.638418 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52496.389892 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.223350 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52498.194946 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.730964 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41464.541202 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41464.541202 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 42072.666366 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 42072.698576 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 42072.666366 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 42072.698576 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -829,19 +703,19 @@ system.cpu.l2cache.demand_mshr_misses::total 15512 system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15512 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819084 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819584 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10783379 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602463 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602963 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 420800342 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 420800342 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819084 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819584 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 431583721 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 458402805 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819084 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 458403305 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819584 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 431583721 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 458402805 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 458403305 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses @@ -855,19 +729,145 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016357 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016357 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37933.640736 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37934.347949 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40387.187266 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.224846 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.738193 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28944.857752 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28944.857752 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 943495 # number of replacements +system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use +system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits +system.cpu.dcache.overall_hits::total 28133775 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses +system.cpu.dcache.overall_misses::total 1370806 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880184000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13880184000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19250281404 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19250281404 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19250281404 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19250281404 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782919 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782919 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14043.038478 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14043.038478 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks +system.cpu.dcache.writebacks::total 942892 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989578000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989578000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120952 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10947120952 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120952 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10947120952 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.342542 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.342542 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 4d1a87896..e9db1ff8f 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -433,21 +430,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -464,6 +456,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -483,21 +478,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -524,9 +514,9 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/gem5/dist/cpu2000/binaries/x86/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 0aa3d6ea9..83aadb6fc 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2012 00:35:18 -gem5 started Dec 30 2012 00:35:30 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jan 4 2013 21:20:54 +gem5 started Jan 4 2013 22:18:55 +gem5 executing on u200540 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 1e22e4596..0c883f6c5 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.065983 # Nu sim_ticks 65982862500 # Number of ticks simulated final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71115 # Simulator instruction rate (inst/s) -host_op_rate 125222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29700736 # Simulator tick rate (ticks/s) -host_mem_usage 413360 # Number of bytes of host memory used -host_seconds 2221.59 # Real time elapsed on the host +host_inst_rate 39069 # Simulator instruction rate (inst/s) +host_op_rate 68794 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16316772 # Simulator tick rate (ticks/s) +host_mem_usage 376348 # Number of bytes of host memory used +host_seconds 4043.87 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 65982842000 # Total gap between requests +system.physmem.totGap 65982843000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 10444357 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 571602357 # Sum of mem lat for all requests +system.physmem.totQLat 10445857 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 571603857 # Sum of mem lat for all requests system.physmem.totBusLat 121544000 # Total cycles spent in databus access system.physmem.totBankLat 439614000 # Total cycles spent in bank access -system.physmem.avgQLat 343.72 # Average queueing delay per request +system.physmem.avgQLat 343.77 # Average queueing delay per request system.physmem.avgBankLat 14467.65 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18811.37 # Average memory access latency +system.physmem.avgMemAccLat 18811.42 # Average memory access latency system.physmem.avgRdBW 29.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 29.53 # Average consumed read bandwidth in MB/s @@ -191,7 +191,7 @@ system.physmem.readRowHits 29640 # Nu system.physmem.writeRowHits 45 # Number of row buffer hits during writes system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes -system.physmem.avgGap 2155034.36 # Average gap between requests +system.physmem.avgGap 2155034.39 # Average gap between requests system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 131965726 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -204,18 +204,18 @@ system.cpu.BPredUnit.BTBHits 24642661 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 26601820 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 24642661 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 56492855 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 6109576 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 43628030 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25952050 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 188970 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 25952051 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 188971 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 131886743 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.485312 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.326723 # Number of instructions fetched each cycle (Total) @@ -460,12 +460,12 @@ system.cpu.fp_regfile_reads 138 # nu system.cpu.fp_regfile_writes 78 # number of floating regfile writes system.cpu.misc_regfile_reads 192690356 # number of misc regfile reads system.cpu.icache.replacements 68 # number of replacements -system.cpu.icache.tagsinuse 836.141366 # Cycle average of tags in use +system.cpu.icache.tagsinuse 836.141368 # Cycle average of tags in use system.cpu.icache.total_refs 25950700 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1039 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 24976.612127 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 836.141366 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 836.141368 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.408272 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.408272 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 25950700 # number of ReadReq hits @@ -474,36 +474,36 @@ system.cpu.icache.demand_hits::cpu.inst 25950700 # nu system.cpu.icache.demand_hits::total 25950700 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 25950700 # number of overall hits system.cpu.icache.overall_hits::total 25950700 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1350 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1350 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1350 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1350 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1350 # number of overall misses -system.cpu.icache.overall_misses::total 1350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65277000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65277000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65277000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65277000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65277000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65277000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25952050 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25952050 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25952050 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25952050 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25952050 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25952050 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 1351 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1351 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1351 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1351 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1351 # number of overall misses +system.cpu.icache.overall_misses::total 1351 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65349000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65349000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65349000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65349000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65349000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65349000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25952051 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25952051 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25952051 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25952051 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25952051 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25952051 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48353.333333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48353.333333 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48353.333333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48353.333333 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48370.836417 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48370.836417 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48370.836417 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48370.836417 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 243 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -512,153 +512,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 48.600000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 311 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 311 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 311 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 311 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1040 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1040 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 1040 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1040 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1040 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1040 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52080000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 52080000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52080000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 52080000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52080000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 52080000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52081000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 52081000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52081000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 52081000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52081000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 52081000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50076.923077 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50076.923077 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50077.884615 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50077.884615 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072071 # number of replacements -system.cpu.dcache.tagsinuse 4072.565348 # Cycle average of tags in use -system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.565348 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits -system.cpu.dcache.overall_hits::total 71946748 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses -system.cpu.dcache.overall_misses::total 2723462 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321017500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31321017500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33409125998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33409125998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33409125998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33409125998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.970796 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.970796 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.153350 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12267.153350 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.153350 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12267.153350 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks -system.cpu.dcache.writebacks::total 2066432 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983433500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983433500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23796285498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23796285498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531267 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531267 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621176 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621176 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621176 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621176 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 488 # number of replacements -system.cpu.l2cache.tagsinuse 20806.359939 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 20806.359941 # Cycle average of tags in use system.cpu.l2cache.total_refs 4028768 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 30421 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 132.433779 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 19869.947946 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 692.491885 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 692.491887 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 243.920108 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.606383 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021133 # Average percentage of cache occupancy @@ -690,17 +582,17 @@ system.cpu.l2cache.demand_misses::total 30444 # nu system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses system.cpu.l2cache.overall_misses::total 30444 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50832500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21222500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 72055000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50833500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21223000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 72056500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199120000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1199120000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50832500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1220342500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1271175000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50832500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1220342500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1271175000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 50833500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1220343000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1271176500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 50833500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1220343000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1271176500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1039 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1993942 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1994981 # number of ReadReq accesses(hits+misses) @@ -729,17 +621,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014656 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980751 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014173 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014656 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49884.690873 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50053.066038 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49934.164934 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49885.672228 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50054.245283 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49935.204435 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41347.539740 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41347.539740 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 41754.532913 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 41754.532913 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 41754.582184 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 41754.582184 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -763,19 +655,19 @@ system.cpu.l2cache.demand_mshr_misses::total 30444 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29425 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30444 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37999583 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880149 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53879732 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38000083 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880649 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53880732 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824195395 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824195395 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37999583 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840075544 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 878075127 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37999583 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840075544 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 878075127 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38000083 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840076044 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 878076127 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38000083 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840076044 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 878076127 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000723 # mshr miss rate for ReadReq accesses @@ -789,19 +681,127 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014656 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014656 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.052993 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37453.181604 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37338.691615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.543670 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37454.360849 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37339.384615 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28419.550878 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28419.550878 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2072071 # number of replacements +system.cpu.dcache.tagsinuse 4072.565350 # Cycle average of tags in use +system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.565350 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits +system.cpu.dcache.overall_hits::total 71946748 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses +system.cpu.dcache.overall_misses::total 2723462 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321024000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31321024000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33409132498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33409132498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33409132498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33409132498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.973272 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.973272 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12267.155737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12267.155737 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks +system.cpu.dcache.writebacks::total 2066432 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983434000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983434000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23796285998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23796285998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531518 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531518 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 3f8e309bf..e7ade82e3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,9 +522,9 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/gem5/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index 374965c0a..b4d96e4ea 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] -warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7] hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index c76d776a9..ad20b1136 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 19:35:49 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:51:04 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 206019870500 because target called exit() +Exiting @ tick 206006891000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 114baeb55..fe6fd5ff5 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.206025 # Number of seconds simulated -sim_ticks 206024606500 # Number of ticks simulated -final_tick 206024606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.206007 # Number of seconds simulated +sim_ticks 206006891000 # Number of ticks simulated +final_tick 206006891000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152686 # Simulator instruction rate (inst/s) -host_op_rate 172002 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61807337 # Simulator tick rate (ticks/s) -host_mem_usage 303988 # Number of bytes of host memory used -host_seconds 3333.34 # Real time elapsed on the host -sim_insts 508955238 # Number of instructions simulated -sim_ops 573341798 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9266560 # Number of bytes read from this memory -system.physmem.bytes_read::total 9483840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6249216 # Number of bytes written to this memory -system.physmem.bytes_written::total 6249216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144790 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148185 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97644 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97644 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1054631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44977928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46032560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1054631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1054631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30332377 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30332377 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30332377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1054631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44977928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 76364937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148186 # Total number of read requests seen -system.physmem.writeReqs 97644 # Total number of write requests seen -system.physmem.cpureqs 245841 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9483840 # Total number of bytes read from memory -system.physmem.bytesWritten 6249216 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9483840 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6249216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 83 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9199 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8811 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9127 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10272 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 9693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9129 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8756 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5972 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5945 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6129 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5951 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6373 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6322 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6045 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6065 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5778 # Track writes on a per bank basis +host_inst_rate 48397 # Simulator instruction rate (inst/s) +host_op_rate 54519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19589283 # Simulator tick rate (ticks/s) +host_mem_usage 261836 # Number of bytes of host memory used +host_seconds 10516.31 # Real time elapsed on the host +sim_insts 508955198 # Number of instructions simulated +sim_ops 573341758 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 216256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9272640 # Number of bytes read from this memory +system.physmem.bytes_read::total 9488896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6250240 # Number of bytes written to this memory +system.physmem.bytes_written::total 6250240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3379 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144885 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148264 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97660 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97660 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1049751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45011310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46061061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30339956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30339956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30339956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45011310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 76401017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148265 # Total number of read requests seen +system.physmem.writeReqs 97660 # Total number of write requests seen +system.physmem.cpureqs 245934 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9488896 # Total number of bytes read from memory +system.physmem.bytesWritten 6250240 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9488896 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6250240 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9341 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8981 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9466 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9155 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 9694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9134 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9019 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8746 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5978 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6111 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6105 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5940 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6031 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6368 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6669 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6289 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6316 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6051 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6056 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5774 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 206024585500 # Total gap between requests +system.physmem.totGap 206006873500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148186 # Categorize read packet sizes +system.physmem.readPktSize::6 148265 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 97644 # categorize write packet sizes +system.physmem.writePktSize::6 97660 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,15 +102,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11 # categorize neither packet sizes +system.physmem.neitherpktsize::6 9 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 138148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 138270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,8 +138,8 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4247 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 4246 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4246 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4246 # What write queue length does an incoming req see @@ -147,20 +147,20 @@ system.physmem.wrQLenPdf::5 4246 # Wh system.physmem.wrQLenPdf::6 4246 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4246 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1634901672 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4710633672 # Sum of mem lat for all requests -system.physmem.totBusLat 592412000 # Total cycles spent in databus access -system.physmem.totBankLat 2483320000 # Total cycles spent in bank access -system.physmem.avgQLat 11038.95 # Average queueing delay per request -system.physmem.avgBankLat 16767.52 # Average bank access latency per request +system.physmem.totQLat 1631933240 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4708845240 # Sum of mem lat for all requests +system.physmem.totBusLat 592780000 # Total cycles spent in databus access +system.physmem.totBankLat 2484132000 # Total cycles spent in bank access +system.physmem.avgQLat 11012.07 # Average queueing delay per request +system.physmem.avgBankLat 16762.59 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31806.47 # Average memory access latency -system.physmem.avgRdBW 46.03 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 30.33 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 46.03 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 30.33 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31774.66 # Average memory access latency +system.physmem.avgRdBW 46.06 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 30.34 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 46.06 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 30.34 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.48 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.63 # Average write queue length over time -system.physmem.readRowHits 128528 # Number of row buffer hits during reads -system.physmem.writeRowHits 35061 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 35.91 # Row buffer hit rate for writes -system.physmem.avgGap 838077.47 # Average gap between requests +system.physmem.avgWrQLen 8.58 # Average write queue length over time +system.physmem.readRowHits 128622 # Number of row buffer hits during reads +system.physmem.writeRowHits 35037 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 35.88 # Row buffer hit rate for writes +system.physmem.avgGap 837681.71 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,107 +235,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 412049214 # number of cpu cycles simulated +system.cpu.numCycles 412013783 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 182068030 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 142371650 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7270692 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 93491623 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 88706856 # Number of BTB hits +system.cpu.BPredUnit.lookups 182073557 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142374329 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7271583 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 93640941 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 88714986 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12684721 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 116337 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 117167260 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 763059580 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182068030 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 101391577 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170902348 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35691223 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 89206735 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 447 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 113060023 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2443326 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 404896941 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.113484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.961332 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12682930 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 115717 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 117168420 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 763090504 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182073557 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 101397916 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170904146 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35690489 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 89173012 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 387 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 113064693 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2443926 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 404864320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.113664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.961425 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 234007224 57.79% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14183787 3.50% 61.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22898202 5.66% 66.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22746913 5.62% 72.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20897614 5.16% 77.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13086335 3.23% 80.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13059349 3.23% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11995905 2.96% 87.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52021612 12.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 233972788 57.79% 57.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14182494 3.50% 61.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22907477 5.66% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22746192 5.62% 72.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20892499 5.16% 77.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13088798 3.23% 80.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13051042 3.22% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11993527 2.96% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52029503 12.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 404896941 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.441860 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.851865 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127568061 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83247236 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 161078099 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5457696 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27545849 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26128375 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76880 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 833033782 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 297363 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27545849 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135637511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9603466 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 58001862 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158291644 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15816609 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 804360707 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1150 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3056892 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8825253 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 274 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 960209661 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3520079656 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3520077996 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672200315 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288009346 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3037560 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3037556 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48985402 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170961044 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 74192431 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27929541 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15655992 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 757955551 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4467760 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 669035735 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1391656 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187243555 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479554620 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 746625 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 404896941 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.652361 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.728633 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 404864320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.441911 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.852099 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127567795 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83214346 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 161081773 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5456100 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27544306 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26131693 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76746 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 833046476 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 293832 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27544306 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135636368 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9592122 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57998215 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158294561 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15798748 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 804356889 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3056071 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8809517 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 236 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 960228219 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3520047664 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3520046036 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1628 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672200251 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 288027968 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3037400 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3037395 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48984020 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170948465 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74181775 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27930048 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15662241 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 757938362 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4467556 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 669004170 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1390745 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187223839 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479595431 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 746429 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 404864320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.652416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.728625 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145342748 35.90% 35.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 75751868 18.71% 54.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69103679 17.07% 71.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53697004 13.26% 84.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30880919 7.63% 92.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16180758 4.00% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9302044 2.30% 98.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3357601 0.83% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1280320 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145294997 35.89% 35.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 75803785 18.72% 54.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69074812 17.06% 71.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53696610 13.26% 84.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30882442 7.63% 92.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16155264 3.99% 96.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9314791 2.30% 98.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3366855 0.83% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1274764 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 404896941 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 404864320 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 478504 4.99% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 478550 4.99% 4.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.99% # attempts to use FU when none available @@ -364,447 +364,321 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.99% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6546722 68.33% 73.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2556023 26.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6548662 68.24% 73.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2569141 26.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 449967918 67.26% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383484 0.06% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 154140670 23.04% 90.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 64543544 9.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 449957502 67.26% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383513 0.06% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 114 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 154129801 23.04% 90.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 64533237 9.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 669035735 # Type of FU issued -system.cpu.iq.rate 1.623679 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9581249 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014321 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1753941049 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 950473417 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 649676758 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 669004170 # Type of FU issued +system.cpu.iq.rate 1.623742 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9596353 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014344 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1753859495 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 950436200 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 649651296 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 358 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 678616849 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8574736 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 678600390 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8560025 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44187986 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 40720 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810577 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16588451 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44175415 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 40342 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810510 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16577803 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19568 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4004 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19533 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4184 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27545849 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4988149 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 372803 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 763982304 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1114436 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170961044 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 74192431 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2979014 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 218503 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11510 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810577 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4341639 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4005453 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8347092 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 659537182 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150855099 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9498553 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27544306 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4979953 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 372702 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 763965600 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1116680 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170948465 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74181775 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2978814 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 218949 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11431 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810510 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4342934 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4004049 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8346983 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 659511571 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150841037 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9492599 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558993 # number of nop insts executed -system.cpu.iew.exec_refs 214102413 # number of memory reference insts executed -system.cpu.iew.exec_branches 139198797 # Number of branches executed -system.cpu.iew.exec_stores 63247314 # Number of stores executed -system.cpu.iew.exec_rate 1.600627 # Inst execution rate -system.cpu.iew.wb_sent 654653382 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 649676774 # cumulative count of insts written-back -system.cpu.iew.wb_producers 375457821 # num instructions producing a value -system.cpu.iew.wb_consumers 646369335 # num instructions consuming a value +system.cpu.iew.exec_nop 1559682 # number of nop insts executed +system.cpu.iew.exec_refs 214084743 # number of memory reference insts executed +system.cpu.iew.exec_branches 139192858 # Number of branches executed +system.cpu.iew.exec_stores 63243706 # Number of stores executed +system.cpu.iew.exec_rate 1.600703 # Inst execution rate +system.cpu.iew.wb_sent 654626894 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 649651312 # cumulative count of insts written-back +system.cpu.iew.wb_producers 375421754 # num instructions producing a value +system.cpu.iew.wb_consumers 646280118 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.576697 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.580872 # average fanout of values written-back +system.cpu.iew.wb_rate 1.576771 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.580896 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189322511 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721135 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7196542 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 377351093 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.522947 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.207142 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 189306245 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721127 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 7197604 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 377320014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.523072 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.207570 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 165639440 43.90% 43.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102355544 27.12% 71.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 34004026 9.01% 80.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18854456 5.00% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16118319 4.27% 89.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7599031 2.01% 91.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6941679 1.84% 93.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3068571 0.81% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22770027 6.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 165631141 43.90% 43.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102377769 27.13% 71.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33965417 9.00% 80.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18834681 4.99% 85.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16120892 4.27% 89.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7588494 2.01% 91.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6947007 1.84% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3071988 0.81% 93.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22782625 6.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 377351093 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510299122 # Number of instructions committed -system.cpu.commit.committedOps 574685682 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 377320014 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510299082 # Number of instructions committed +system.cpu.commit.committedOps 574685642 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377038 # Number of memory references committed -system.cpu.commit.loads 126773058 # Number of loads committed +system.cpu.commit.refs 184377022 # Number of memory references committed +system.cpu.commit.loads 126773050 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 122291804 # Number of branches committed +system.cpu.commit.branches 122291796 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701705 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701673 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22770027 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22782625 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1118582121 # The number of ROB reads -system.cpu.rob.rob_writes 1555682986 # The number of ROB writes -system.cpu.timesIdled 306922 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7152273 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508955238 # Number of Instructions Simulated -system.cpu.committedOps 573341798 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508955238 # Number of Instructions Simulated -system.cpu.cpi 0.809598 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.809598 # CPI: Total CPI of All Threads -system.cpu.ipc 1.235181 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.235181 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3078487600 # number of integer regfile reads -system.cpu.int_regfile_writes 757812476 # number of integer regfile writes +system.cpu.rob.rob_reads 1118522138 # The number of ROB reads +system.cpu.rob.rob_writes 1555649058 # The number of ROB writes +system.cpu.timesIdled 306506 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7149463 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508955198 # Number of Instructions Simulated +system.cpu.committedOps 573341758 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508955198 # Number of Instructions Simulated +system.cpu.cpi 0.809529 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.809529 # CPI: Total CPI of All Threads +system.cpu.ipc 1.235287 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.235287 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3078340491 # number of integer regfile reads +system.cpu.int_regfile_writes 757780607 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 213834943 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464090 # number of misc regfile writes -system.cpu.icache.replacements 14939 # number of replacements -system.cpu.icache.tagsinuse 1085.691077 # Cycle average of tags in use -system.cpu.icache.total_refs 113039002 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16794 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6730.915922 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 213817535 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464074 # number of misc regfile writes +system.cpu.icache.replacements 15034 # number of replacements +system.cpu.icache.tagsinuse 1084.596639 # Cycle average of tags in use +system.cpu.icache.total_refs 113043631 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16888 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6693.725189 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1085.691077 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.530123 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.530123 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 113039002 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113039002 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113039002 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113039002 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113039002 # number of overall hits -system.cpu.icache.overall_hits::total 113039002 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21020 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21020 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21020 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21020 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21020 # number of overall misses -system.cpu.icache.overall_misses::total 21020 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 467898499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 467898499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 467898499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 467898499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 467898499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 467898499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 113060022 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 113060022 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 113060022 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 113060022 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 113060022 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 113060022 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1084.596639 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.529588 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.529588 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 113043631 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113043631 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113043631 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113043631 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113043631 # number of overall hits +system.cpu.icache.overall_hits::total 113043631 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21062 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21062 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21062 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21062 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21062 # number of overall misses +system.cpu.icache.overall_misses::total 21062 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 460496000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 460496000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 460496000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 460496000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 460496000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 460496000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 113064693 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 113064693 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 113064693 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 113064693 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 113064693 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 113064693 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22259.681208 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22259.681208 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22259.681208 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22259.681208 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22259.681208 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22259.681208 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 617 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21863.830595 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21863.830595 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21863.830595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21863.830595 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1088 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44.071429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 90.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4142 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4142 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4142 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4142 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4142 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4142 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16878 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16878 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16878 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16878 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16878 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16878 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 345467499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 345467499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 345467499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 345467499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 345467499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 345467499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20468.509243 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20468.509243 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20468.509243 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20468.509243 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20468.509243 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20468.509243 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4099 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4099 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4099 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4099 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4099 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4099 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16963 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16963 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16963 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16963 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16963 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16963 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340828000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 340828000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340828000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 340828000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340828000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 340828000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000150 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000150 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000150 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20092.436479 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20092.436479 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192636 # number of replacements -system.cpu.dcache.tagsinuse 4054.758730 # Cycle average of tags in use -system.cpu.dcache.total_refs 191679858 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196732 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 160.169410 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4054.758730 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989931 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989931 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136223332 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136223332 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50991136 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50991136 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233077 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2233077 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2232044 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2232044 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187214468 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187214468 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187214468 # number of overall hits -system.cpu.dcache.overall_hits::total 187214468 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1695528 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1695528 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3248170 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3248170 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4943698 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4943698 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4943698 # number of overall misses -system.cpu.dcache.overall_misses::total 4943698 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25996744000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25996744000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58872632949 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58872632949 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 602000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 602000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84869376949 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84869376949 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84869376949 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84869376949 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137918860 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137918860 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233117 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2233117 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232044 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2232044 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192158166 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192158166 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192158166 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192158166 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012294 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012294 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059886 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059886 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000018 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000018 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025727 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025727 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025727 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025727 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15332.535942 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15332.535942 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18124.861984 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18124.861984 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15050 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15050 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17167.184757 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17167.184757 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14786 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14311 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1668 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 602 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.864508 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23.772425 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110847 # number of writebacks -system.cpu.dcache.writebacks::total 1110847 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 847136 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 847136 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899743 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2899743 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3746879 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3746879 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3746879 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3746879 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848392 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848392 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348427 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348427 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196819 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196819 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196819 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196819 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11475027500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11475027500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8270144996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8270144996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19745172496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19745172496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19745172496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19745172496 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13525.619643 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13525.619643 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23735.660543 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23735.660543 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16498.043978 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16498.043978 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16498.043978 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16498.043978 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 115436 # number of replacements -system.cpu.l2cache.tagsinuse 26914.677594 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1781438 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 146695 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 12.143822 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 106786835500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 22885.911087 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 362.909713 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3665.856794 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.698423 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.011075 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.111873 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.821371 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13377 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804311 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817688 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1110847 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1110847 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 76 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 76 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247608 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247608 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 13377 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1051919 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065296 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 13377 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1051919 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065296 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3401 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 43520 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 46921 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101293 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101293 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3401 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144813 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 148214 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3401 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144813 # number of overall misses -system.cpu.l2cache.overall_misses::total 148214 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 194270000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2545313000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2739583000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5395902500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5395902500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 194270000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7941215500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8135485500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 194270000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7941215500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8135485500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16778 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 847831 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 864609 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1110847 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1110847 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 87 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 87 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 348901 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 348901 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 16778 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1196732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1213510 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16778 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1196732 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1213510 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.202706 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051331 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.054268 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.126437 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.126437 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290320 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.290320 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.202706 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.121007 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.122137 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.202706 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.121007 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.122137 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57121.434872 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58486.052390 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 58387.140087 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53270.240787 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53270.240787 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57121.434872 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 144900235 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6102247819 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6247148054 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 144900235 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6102247819 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6247148054 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051433 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054337 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.120000 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45715.303021 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45511.561558 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40554.119426 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40554.119426 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44452.667845 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42111.248374 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42164.907022 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44452.667845 # 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average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1192383 # number of replacements +system.cpu.dcache.tagsinuse 4054.755183 # Cycle average of tags in use +system.cpu.dcache.total_refs 191684453 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196479 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 160.207119 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4054.755183 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989930 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989930 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136225611 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136225611 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50993519 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50993519 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233068 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2233068 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2232036 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2232036 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 187219130 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187219130 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187219130 # number of overall hits +system.cpu.dcache.overall_hits::total 187219130 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1694816 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1694816 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3245787 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3245787 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4940603 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4940603 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4940603 # number of overall misses +system.cpu.dcache.overall_misses::total 4940603 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25904626000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25904626000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58849421949 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58849421949 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 574000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 574000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84754047949 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84754047949 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84754047949 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84754047949 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137920427 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137920427 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233106 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2233106 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232036 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2232036 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 192159733 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192159733 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192159733 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192159733 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012288 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012288 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059842 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059842 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000017 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000017 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025711 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025711 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025711 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025711 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15284.624408 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15284.624408 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18131.017824 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18131.017824 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15105.263158 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15105.263158 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17154.595896 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17154.595896 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17154.595896 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17154.595896 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17486 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15854 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1635 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 605 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.694801 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26.204959 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1110621 # number of writebacks +system.cpu.dcache.writebacks::total 1110621 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 846554 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 846554 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2897494 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2897494 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3744048 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3744048 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3744048 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3744048 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848262 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848262 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348293 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348293 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196555 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196555 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196555 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196555 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11478175000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11478175000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269727997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269727997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19747902997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19747902997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19747902997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19747902997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13531.403033 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13531.403033 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23743.595183 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23743.595183 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 891e5989e..b3fdd5038 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -433,21 +430,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -464,6 +456,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -483,21 +478,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -524,9 +514,9 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/gem5/dist/cpu2000/binaries/x86/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 1d8d6278f..1c86b657b 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2012 00:35:18 -gem5 started Dec 30 2012 01:06:22 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jan 4 2013 21:20:54 +gem5 started Jan 4 2013 22:32:47 +gem5 executing on u200540 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index c659e891f..93e747e50 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.434475 # Nu sim_ticks 434474519000 # Number of ticks simulated final_tick 434474519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64407 # Simulator instruction rate (inst/s) -host_op_rate 119096 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33842135 # Simulator tick rate (ticks/s) -host_mem_usage 385848 # Number of bytes of host memory used -host_seconds 12838.27 # Real time elapsed on the host +host_inst_rate 38128 # Simulator instruction rate (inst/s) +host_op_rate 70503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20033995 # Simulator tick rate (ticks/s) +host_mem_usage 425632 # Number of bytes of host memory used +host_seconds 21686.86 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 208768 # Number of bytes read from this memory @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 18336 # Tr system.physmem.perBankWrReqs::15 18435 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 434474501000 # Total gap between requests +system.physmem.totGap 434474502000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 213431 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 380876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 380877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3519471180 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11592783180 # Sum of mem lat for all requests +system.physmem.totQLat 3519643685 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11592955685 # Sum of mem lat for all requests system.physmem.totBusLat 1542368000 # Total cycles spent in databus access system.physmem.totBankLat 6530944000 # Total cycles spent in bank access -system.physmem.avgQLat 9127.45 # Average queueing delay per request +system.physmem.avgQLat 9127.90 # Average queueing delay per request system.physmem.avgBankLat 16937.45 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30064.90 # Average memory access latency +system.physmem.avgMemAccLat 30065.34 # Average memory access latency system.physmem.avgRdBW 56.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 56.82 # Average consumed read bandwidth in MB/s @@ -204,23 +204,23 @@ system.cpu.BPredUnit.BTBHits 147901505 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180614780 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 180614847 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 1193262475 # Number of instructions fetch has processed system.cpu.fetch.Branches 215014033 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 147901505 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 371277896 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 83426833 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 232782957 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33410 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 232782979 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33409 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 326127 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173495456 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3828583 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 855065189 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 173495457 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3828584 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 855065277 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.591332 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.388123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.388122 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 488192448 57.09% 57.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 488192536 57.09% 57.09% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 24710241 2.89% 59.98% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 27337259 3.20% 63.18% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 28858306 3.37% 66.56% # Number of instructions fetched each cycle (Total) @@ -232,19 +232,19 @@ system.cpu.fetch.rateDist::8 183354461 21.44% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 855065189 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 855065277 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.247441 # Number of branch fetches per cycle system.cpu.fetch.rate 1.373225 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 236982201 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 189423350 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 236982267 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 189423372 # Number of cycles decode is blocked system.cpu.decode.RunCycles 313528776 # Number of cycles decode is running system.cpu.decode.UnblockCycles 45100886 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 70029976 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 2167023894 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 70029976 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270449019 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55242457 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 270449085 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55242479 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16336 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 322681638 # Number of cycles rename is running system.cpu.rename.UnblockCycles 136645763 # Number of cycles rename is unblocking @@ -273,23 +273,23 @@ system.cpu.iq.iqSquashedInstsIssued 844321 # Nu system.cpu.iq.iqSquashedInstsExamined 499602168 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 818314817 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 22641 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 855065189 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 855065277 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.114825 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.887939 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 234637640 27.44% 27.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145403734 17.00% 44.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138360213 16.18% 60.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 132907886 15.54% 76.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 234637728 27.44% 27.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145403732 17.00% 44.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138360216 16.18% 60.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 132907885 15.54% 76.17% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 96033162 11.23% 87.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58823756 6.88% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34984723 4.09% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58823757 6.88% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34984722 4.09% 98.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 12006815 1.40% 99.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1907260 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 855065189 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 855065277 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 4945166 32.31% 32.31% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available @@ -362,7 +362,7 @@ system.cpu.iq.FU_type_0::total 1808313369 # Ty system.cpu.iq.rate 2.081035 # Inst issue rate system.cpu.iq.fu_busy_cnt 15304879 # FU busy when requested system.cpu.iq.fu_busy_rate 0.008464 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4487818661 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 4487818749 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2533909829 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1768767082 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 22466 # Number of floating instruction queue reads @@ -407,7 +407,7 @@ system.cpu.iew.exec_rate 2.049103 # In system.cpu.iew.wb_sent 1775473697 # cumulative count of insts sent to commit system.cpu.iew.wb_count 1768772258 # cumulative count of insts written-back system.cpu.iew.wb_producers 1341647639 # num instructions producing a value -system.cpu.iew.wb_consumers 1964496611 # num instructions consuming a value +system.cpu.iew.wb_consumers 1964496615 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.035530 # insts written-back per cycle system.cpu.iew.wb_fanout 0.682947 # average fanout of values written-back @@ -415,23 +415,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 505138383 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 13172358 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 785035213 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 785035301 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.947669 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.458282 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 291749690 37.16% 37.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195656651 24.92% 62.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62029976 7.90% 69.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 291749780 37.16% 37.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195656650 24.92% 62.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62029975 7.90% 69.99% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 92178611 11.74% 81.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25075018 3.19% 84.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25075017 3.19% 84.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 28259306 3.60% 88.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 9351525 1.19% 89.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10844976 1.38% 91.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10844977 1.38% 91.10% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 69889460 8.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 785035213 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 785035301 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -444,10 +444,10 @@ system.cpu.commit.int_insts 1528317559 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 69889460 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2749272836 # The number of ROB reads +system.cpu.rob.rob_reads 2749272924 # The number of ROB reads system.cpu.rob.rob_writes 4138465929 # The number of ROB writes system.cpu.timesIdled 341987 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13883850 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 13883762 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated @@ -461,50 +461,50 @@ system.cpu.fp_regfile_reads 5173 # nu system.cpu.fp_regfile_writes 5 # number of floating regfile writes system.cpu.misc_regfile_reads 980297933 # number of misc regfile reads system.cpu.icache.replacements 5393 # number of replacements -system.cpu.icache.tagsinuse 1034.711161 # Cycle average of tags in use -system.cpu.icache.total_refs 173255659 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1034.711169 # Cycle average of tags in use +system.cpu.icache.total_refs 173255660 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 6985 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24803.959771 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 24803.959914 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1034.711161 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1034.711169 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.505230 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.505230 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173271213 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173271213 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173271213 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173271213 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173271213 # number of overall hits -system.cpu.icache.overall_hits::total 173271213 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 173271214 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173271214 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173271214 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173271214 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173271214 # number of overall hits +system.cpu.icache.overall_hits::total 173271214 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 224243 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 224243 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 224243 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 224243 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 224243 # number of overall misses system.cpu.icache.overall_misses::total 224243 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1407047499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1407047499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1407047499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1407047499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1407047499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1407047499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173495456 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173495456 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173495456 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173495456 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173495456 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173495456 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1406797999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1406797999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1406797999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1406797999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1406797999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1406797999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173495457 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173495457 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173495457 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173495457 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173495457 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173495457 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001293 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001293 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001293 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001293 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001293 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001293 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6274.655169 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6274.655169 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6274.655169 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6274.655169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6274.655169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6274.655169 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6273.542536 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6273.542536 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6273.542536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6273.542536 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -525,142 +525,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 221942 system.cpu.icache.demand_mshr_misses::total 221942 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 221942 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 221942 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 897816999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 897816999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 897816999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 897816999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 897816999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 897816999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 897728499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 897728499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 897728499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 897728499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 897728499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 897728499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001279 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001279 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001279 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4045.277591 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4045.277591 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4045.277591 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4045.277591 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4045.277591 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4045.277591 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4044.878838 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4044.878838 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4044.878838 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4044.878838 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4044.878838 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4044.878838 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529684 # number of replacements -system.cpu.dcache.tagsinuse 4087.842109 # Cycle average of tags in use -system.cpu.dcache.total_refs 405350413 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533780 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 159.978535 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.842109 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 256614449 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 256614449 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148157374 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148157374 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 404771823 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 404771823 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 404771823 # number of overall hits -system.cpu.dcache.overall_hits::total 404771823 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2894004 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2894004 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1002828 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1002828 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3896832 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3896832 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3896832 # number of overall misses -system.cpu.dcache.overall_misses::total 3896832 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 50112496000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 50112496000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24443364500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24443364500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 74555860500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 74555860500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 74555860500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 74555860500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 259508453 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 259508453 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408668655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408668655 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408668655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408668655 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011152 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006723 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006723 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17315.973302 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17315.973302 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24374.433602 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24374.433602 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19132.428727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19132.428727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19132.428727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19132.428727 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5893 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 639 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.222222 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331225 # number of writebacks -system.cpu.dcache.writebacks::total 2331225 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1131349 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1131349 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16796 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16796 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1148145 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1148145 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1148145 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1148145 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762655 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762655 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 986032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 986032 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2748687 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2748687 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2748687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2748687 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26924620000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26924620000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22273932000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 22273932000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49198552000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49198552000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49198552000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49198552000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006726 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006726 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15275.036805 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15275.036805 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22589.461600 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22589.461600 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17898.928470 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17898.928470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17898.928470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17898.928470 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 353060 # number of replacements -system.cpu.l2cache.tagsinuse 29622.342662 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29622.342672 # Cycle average of tags in use system.cpu.l2cache.total_refs 3697189 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 385414 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 9.592773 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 201829074500 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 21058.164970 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 233.252125 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8330.925568 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 233.252133 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8330.925570 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.642644 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.007118 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.254240 # Average percentage of cache occupancy @@ -693,19 +585,19 @@ system.cpu.l2cache.demand_misses::total 385781 # nu system.cpu.l2cache.overall_misses::cpu.inst 3263 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 382518 # number of overall misses system.cpu.l2cache.overall_misses::total 385781 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183141000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9258521455 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9441662455 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183052500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9258735955 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9441788455 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7420500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 7420500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10977669000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10977669000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 183141000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20236190455 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20419331455 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 183141000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20236190455 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20419331455 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10977713000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10977713000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 183052500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20236448955 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20419501455 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 183052500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20236448955 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20419501455 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6941 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1762382 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1769323 # number of ReadReq accesses(hits+misses) @@ -734,19 +626,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.151839 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.470105 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.150967 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151839 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56126.570641 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52679.465696 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52742.297880 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56099.448360 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52680.686166 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52743.001732 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.773379 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.773379 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53092.234700 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53092.234700 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56126.570641 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52902.583552 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52929.852572 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56126.570641 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52902.583552 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52929.852572 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53092.447501 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53092.447501 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56099.448360 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52903.259337 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52930.293236 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56099.448360 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52903.259337 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52930.293236 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -770,19 +662,19 @@ system.cpu.l2cache.demand_mshr_misses::total 385781 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3263 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 382518 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 141900442 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6995851441 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7137751883 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 141813443 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6996065941 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7137879384 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2139624153 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2139624153 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8343850802 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8343850802 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141900442 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15339702243 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15481602685 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141900442 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15339702243 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15481602685 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8343894304 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8343894304 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141813443 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15339960245 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15481773688 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141813443 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15339960245 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15481773688 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099724 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101177 # mshr miss rate for ReadReq accesses @@ -796,19 +688,127 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.151839 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150967 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151839 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43487.723567 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39805.245124 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39872.367584 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43461.061293 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39806.465594 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39873.079820 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.542920 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.542920 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40354.075631 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40354.075631 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43487.723567 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40101.909565 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43487.723567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40101.909565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40354.286024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40354.286024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2529684 # number of replacements +system.cpu.dcache.tagsinuse 4087.842112 # Cycle average of tags in use +system.cpu.dcache.total_refs 405350413 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533780 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 159.978535 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.842112 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 256614449 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256614449 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148157374 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148157374 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404771823 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404771823 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404771823 # number of overall hits +system.cpu.dcache.overall_hits::total 404771823 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2894004 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2894004 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1002828 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1002828 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3896832 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3896832 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3896832 # number of overall misses +system.cpu.dcache.overall_misses::total 3896832 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 50112721500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 50112721500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24443408500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24443408500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 74556130000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 74556130000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 74556130000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 74556130000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259508453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259508453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 408668655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408668655 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408668655 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408668655 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011152 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006723 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006723 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17316.051222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17316.051222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24374.477478 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24374.477478 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19132.497885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19132.497885 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5893 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 639 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.222222 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2331225 # number of writebacks +system.cpu.dcache.writebacks::total 2331225 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1131349 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1131349 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16796 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16796 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1148145 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1148145 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1148145 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1148145 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762655 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762655 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 986032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 986032 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2748687 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2748687 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2748687 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2748687 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26924834500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26924834500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22273976000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 22273976000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49198810500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49198810500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49198810500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49198810500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006611 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006611 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006726 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006726 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15275.158497 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15275.158497 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22589.506223 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22589.506223 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index aecbd5e16..cd1ce8718 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/gem5/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 4b90608f0..46ca25e4c 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 19:45:28 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 00:06:54 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 210b47f80..3611ed5dd 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068267 # Nu sim_ticks 68267465500 # Number of ticks simulated final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160764 # Simulator instruction rate (inst/s) -host_op_rate 205527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40194170 # Simulator tick rate (ticks/s) -host_mem_usage 285344 # Number of bytes of host memory used -host_seconds 1698.44 # Real time elapsed on the host +host_inst_rate 47859 # Simulator instruction rate (inst/s) +host_op_rate 61184 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11965597 # Simulator tick rate (ticks/s) +host_mem_usage 240720 # Number of bytes of host memory used +host_seconds 5705.31 # Real time elapsed on the host sim_insts 273048375 # Number of instructions simulated sim_ops 349076099 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68267282000 # Total gap between requests +system.physmem.totGap 68267283000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -184,7 +184,7 @@ system.physmem.readRowHits 6392 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9355527.20 # Average gap between requests +system.physmem.avgGap 9355527.34 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -239,23 +239,23 @@ system.cpu.BPredUnit.BTBHits 16735646 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 6736138 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 7270 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 38860071 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 38860072 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 317518566 # Number of instructions fetch has processed system.cpu.fetch.Branches 41739250 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 23471784 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 70794265 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 6760095 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21559516 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 21559517 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37487912 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 519564 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136324280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37487913 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 519565 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136324281 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.989165 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.456365 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66156807 48.53% 48.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66156808 48.53% 48.53% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 6761816 4.96% 53.49% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 5641032 4.14% 57.63% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 6022575 4.42% 62.04% # Number of instructions fetched each cycle (Total) @@ -267,11 +267,11 @@ system.cpu.fetch.rateDist::8 35352444 25.93% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136324280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 136324281 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.305704 # Number of branch fetches per cycle system.cpu.fetch.rate 2.325548 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 45389084 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16729555 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 16729556 # Number of cycles decode is blocked system.cpu.decode.RunCycles 66615921 # Number of cycles decode is running system.cpu.decode.UnblockCycles 2549925 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 5039795 # Number of cycles decode is squashing @@ -283,19 +283,19 @@ system.cpu.rename.SquashCycles 5039795 # Nu system.cpu.rename.IdleCycles 50891753 # Number of cycles rename is idle system.cpu.rename.BlockCycles 1911896 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 347462 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63595531 # Number of cycles rename is running +system.cpu.rename.RunCycles 63595532 # Number of cycles rename is running system.cpu.rename.UnblockCycles 14537843 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 393365757 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 393365758 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1668272 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 10291112 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 1086 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 431881386 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2329985493 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1257436076 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 431881387 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2329985497 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1257436080 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 1072549417 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384584833 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47296553 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 47296554 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 14334 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 14333 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 36353497 # count of insts added to the skid buffer @@ -310,11 +310,11 @@ system.cpu.iq.iqSquashedInstsIssued 1224653 # Nu system.cpu.iq.iqSquashedInstsExamined 34098402 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 84823076 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 961 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136324280 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 136324281 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.743078 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.023492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24852306 18.23% 18.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24852307 18.23% 18.23% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 19962410 14.64% 32.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 20554570 15.08% 47.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 18105177 13.28% 61.23% # Number of insts issued each cycle @@ -326,7 +326,7 @@ system.cpu.iq.issued_per_cycle::8 911515 0.67% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136324280 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136324281 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8956 0.05% 0.05% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available @@ -399,7 +399,7 @@ system.cpu.iq.FU_type_0::total 373948163 # Ty system.cpu.iq.rate 2.738846 # Inst issue rate system.cpu.iq.fu_busy_cnt 17797690 # FU busy when requested system.cpu.iq.fu_busy_rate 0.047594 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653530496 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 653530497 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 287597541 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 249877083 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 249712453 # Number of floating instruction queue reads @@ -422,7 +422,7 @@ system.cpu.iew.iewSquashCycles 5039795 # Nu system.cpu.iew.iewBlockCycles 281091 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 41482 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 383923458 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 951525 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 951526 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 103432229 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 91356063 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 14236 # Number of dispatched non-speculative instructions @@ -484,7 +484,7 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 500559121 # The number of ROB reads system.cpu.rob.rob_writes 772890927 # The number of ROB writes system.cpu.timesIdled 6411 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 210652 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 210651 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273048375 # Number of Instructions Simulated system.cpu.committedOps 349076099 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273048375 # Number of Instructions Simulated @@ -513,36 +513,36 @@ system.cpu.icache.demand_hits::cpu.inst 37470862 # nu system.cpu.icache.demand_hits::total 37470862 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 37470862 # number of overall hits system.cpu.icache.overall_hits::total 37470862 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17049 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17049 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17049 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17049 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17049 # number of overall misses -system.cpu.icache.overall_misses::total 17049 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 356549497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 356549497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 356549497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 356549497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 356549497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 356549497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37487911 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37487911 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37487911 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37487911 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37487911 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37487911 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 17050 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17050 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17050 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17050 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17050 # number of overall misses +system.cpu.icache.overall_misses::total 17050 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 356620497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 356620497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 356620497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 356620497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 356620497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 356620497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37487912 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37487912 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37487912 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37487912 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37487912 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37487912 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000455 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000455 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000455 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000455 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000455 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000455 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20913.220541 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20913.220541 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20913.220541 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20913.220541 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20916.158182 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20916.158182 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20916.158182 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20916.158182 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 585 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -551,12 +551,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 30.789474 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1254 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1254 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1254 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1254 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1254 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1254 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1255 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1255 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1255 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1255 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1255 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1255 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15795 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 15795 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 15795 # number of demand (read+write) MSHR misses @@ -582,140 +582,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 18468.059323 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1414 # number of replacements -system.cpu.dcache.tagsinuse 3122.405383 # Cycle average of tags in use -system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3122.405383 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits -system.cpu.dcache.overall_hits::total 170846791 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses -system.cpu.dcache.overall_misses::total 25149 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 164690000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks -system.cpu.dcache.writebacks::total 1040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3959.582107 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3959.582108 # Cycle average of tags in use system.cpu.l2cache.total_refs 13162 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 5412 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.432003 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 367.644751 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2774.541574 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2774.541575 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 817.395782 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011220 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.084672 # Average percentage of cache occupancy @@ -746,16 +620,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 3042 # system.cpu.l2cache.overall_misses::cpu.data 4307 # number of overall misses system.cpu.l2cache.overall_misses::total 7349 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 148332000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74801500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 223133500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74802000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 223134000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128955500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 128955500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 148332000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 203757000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 352089000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 203757500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 352089500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 148332000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 203757000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 352089000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 203757500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 352089500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15795 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1811 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 17606 # number of ReadReq accesses(hits+misses) @@ -781,16 +655,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192593 system.cpu.l2cache.overall_miss_rate::cpu.data 0.931445 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.359910 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48761.341223 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49471.891534 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.255160 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49472.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.364954 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46137.924866 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46137.924866 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 47909.783644 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 47909.851681 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 47909.783644 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 47909.851681 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -853,5 +727,131 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36140.626733 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1414 # number of replacements +system.cpu.dcache.tagsinuse 3122.405384 # Cycle average of tags in use +system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3122.405384 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits +system.cpu.dcache.overall_hits::total 170846791 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses +system.cpu.dcache.overall_misses::total 25149 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 164690500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 996644664 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 996644664 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 996644664 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 996644664 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.522986 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.522986 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39629.594179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39629.594179 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks +system.cpu.dcache.writebacks::total 1040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211724000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211724000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211724000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211724000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.280353 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.280353 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 2cb5b08f3..735e1f1d5 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/gem5/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 220b82b27..638fa449a 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 20:00:53 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 00:23:14 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 2c9a2891f..4f910c5cd 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.624868 # Nu sim_ticks 624867585500 # Number of ticks simulated final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118271 # Simulator instruction rate (inst/s) -host_op_rate 161069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53384157 # Simulator tick rate (ticks/s) -host_mem_usage 298364 # Number of bytes of host memory used -host_seconds 11705.11 # Real time elapsed on the host +host_inst_rate 53257 # Simulator instruction rate (inst/s) +host_op_rate 72528 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24038469 # Simulator tick rate (ticks/s) +host_mem_usage 255596 # Number of bytes of host memory used +host_seconds 25994.48 # Real time elapsed on the host sim_insts 1384379060 # Number of instructions simulated sim_ops 1885333812 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 4108 # Tr system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 624867513500 # Total gap between requests +system.physmem.totGap 624867514500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3316258619 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 18090208619 # Sum of mem lat for all requests +system.physmem.totQLat 3316258119 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 18090208119 # Sum of mem lat for all requests system.physmem.totBusLat 1899312000 # Total cycles spent in databus access system.physmem.totBankLat 12874638000 # Total cycles spent in bank access system.physmem.avgQLat 6984.13 # Average queueing delay per request system.physmem.avgBankLat 27114.32 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38098.45 # Average memory access latency +system.physmem.avgMemAccLat 38098.44 # Average memory access latency system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s @@ -246,23 +246,23 @@ system.cpu.BPredUnit.BTBHits 227490785 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 52186990 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 2806187 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 354123352 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 354123353 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 2285928065 # Number of instructions fetch has processed system.cpu.fetch.Branches 439117025 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 279677775 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 600707462 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 157912293 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133000859 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 133000861 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 564 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11147 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 333825475 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10767149 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1215073364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 333825476 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10767150 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1215073366 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.587868 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.187266 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 614410423 50.57% 50.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614410425 50.57% 50.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 42578199 3.50% 54.07% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 95045800 7.82% 61.89% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 56224969 4.63% 66.52% # Number of instructions fetched each cycle (Total) @@ -274,11 +274,11 @@ system.cpu.fetch.rateDist::8 229019054 18.85% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1215073364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1215073366 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.351368 # Number of branch fetches per cycle system.cpu.fetch.rate 1.829130 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 403820359 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105461627 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 105461629 # Number of cycles decode is blocked system.cpu.decode.RunCycles 561742218 # Number of cycles decode is running system.cpu.decode.UnblockCycles 16831582 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 127217578 # Number of cycles decode is squashing @@ -290,18 +290,18 @@ system.cpu.rename.SquashCycles 127217578 # Nu system.cpu.rename.IdleCycles 439577665 # Number of cycles rename is idle system.cpu.rename.BlockCycles 35450988 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 444214 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540789818 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71593101 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2966286071 # Number of instructions processed by rename +system.cpu.rename.RunCycles 540789819 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71593102 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2966286080 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 4807554 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 56267627 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2940514356 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14121260893 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13550785312 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 2940514359 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14121260922 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13550785341 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 570475581 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993153642 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 947360714 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 947360717 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 22542 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 20019 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 191397273 # count of insts added to the skid buffer @@ -316,11 +316,11 @@ system.cpu.iq.iqSquashedInstsIssued 13311855 # Nu system.cpu.iq.iqSquashedInstsExamined 906440094 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 2354573703 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 7928 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1215073364 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1215073366 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.005123 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.874281 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 379121475 31.20% 31.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 379121477 31.20% 31.20% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 183370974 15.09% 46.29% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 203148367 16.72% 63.01% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 169783138 13.97% 76.98% # Number of insts issued each cycle @@ -332,7 +332,7 @@ system.cpu.iq.issued_per_cycle::8 3045427 0.25% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1215073364 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1215073366 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 714606 0.82% 0.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 24380 0.03% 0.84% # attempts to use FU when none available @@ -405,7 +405,7 @@ system.cpu.iq.FU_type_0::total 2436370950 # Ty system.cpu.iq.rate 1.949510 # Inst issue rate system.cpu.iq.fu_busy_cnt 87664598 # FU busy when requested system.cpu.iq.fu_busy_rate 0.035982 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6066277406 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 6066277408 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 3628118286 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 2252998417 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 122514311 # Number of floating instruction queue reads @@ -428,7 +428,7 @@ system.cpu.iew.iewSquashCycles 127217578 # Nu system.cpu.iew.iewBlockCycles 13751124 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 1562188 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 2804340477 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1409393 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 1409402 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 972715984 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 490205592 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 19935 # Number of dispatched non-speculative instructions @@ -490,7 +490,7 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 3801294955 # The number of ROB reads system.cpu.rob.rob_writes 5735909866 # The number of ROB writes system.cpu.timesIdled 353133 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34661808 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 34661806 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384379060 # Number of Instructions Simulated system.cpu.committedOps 1885333812 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384379060 # Number of Instructions Simulated @@ -519,36 +519,36 @@ system.cpu.icache.demand_hits::cpu.inst 333794637 # nu system.cpu.icache.demand_hits::total 333794637 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 333794637 # number of overall hits system.cpu.icache.overall_hits::total 333794637 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30836 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30836 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30836 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30836 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30836 # number of overall misses -system.cpu.icache.overall_misses::total 30836 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 469688998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 469688998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 469688998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 469688998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 469688998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 469688998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 333825473 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 333825473 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 333825473 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 333825473 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 333825473 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 333825473 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 30837 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 30837 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 30837 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 30837 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 30837 # number of overall misses +system.cpu.icache.overall_misses::total 30837 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 469758998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 469758998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 469758998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 469758998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 469758998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 469758998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 333825474 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 333825474 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 333825474 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 333825474 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 333825474 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 333825474 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15231.839344 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15231.839344 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15231.839344 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15231.839344 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15233.615397 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15233.615397 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15233.615397 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15233.615397 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked @@ -557,163 +557,37 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 34.793103 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2272 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2272 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2272 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2272 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2272 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2272 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2273 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2273 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2273 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2273 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2273 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2273 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28564 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 28564 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379117998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 379117998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379117998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 379117998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379117998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 379117998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379116998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 379116998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379116998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 379116998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379116998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 379116998 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.580801 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.580801 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.545792 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.545792 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532987 # number of replacements -system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use -system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits -system.cpu.dcache.overall_hits::total 969986101 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses -system.cpu.dcache.overall_misses::total 2787983 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369161000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 67369161000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954942470 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39954942470 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 107324103470 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 107324103470 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 107324103470 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 107324103470 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38495.250319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38495.250319 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks -system.cpu.dcache.writebacks::total 96322 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884239500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884239500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478488500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478488500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 442193 # number of replacements system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks. @@ -755,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 474998 # nu system.cpu.l2cache.overall_misses::cpu.inst 2433 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 472565 # number of overall misses system.cpu.l2cache.overall_misses::total 474998 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128014500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837930500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128013500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837931500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 25965945000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242870000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3242870000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 128014500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242869000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3242869000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 128013500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 29080800500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29208815000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 128014500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 29208814000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 128013500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 29080800500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29208815000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29208814000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 24232 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1464568 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1488800 # number of ReadReq accesses(hits+misses) @@ -794,17 +668,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.304229 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100404 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.307443 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.304229 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.906289 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.351956 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.495273 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.354416 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 63498.217273 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.365560 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.365560 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.350425 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.350425 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 61492.501021 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 61492.498916 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 61492.501021 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 61492.498916 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,18 +712,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 2431 system.cpu.l2cache.overall_mshr_misses::cpu.data 472543 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 474974 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97294812 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693796850 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791091662 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693797350 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791092162 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43304330 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43304330 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390499504 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390499504 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390498504 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390498504 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97294812 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084296354 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23181591166 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084295854 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23181590666 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97294812 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084296354 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23181591166 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084295854 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23181590666 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277535 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274651 # mshr miss rate for ReadReq accesses @@ -864,18 +738,144 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100322 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.304214 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.547100 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.131845 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.396826 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.133075 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.398048 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.124981 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.124981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.109847 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.109847 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1532987 # number of replacements +system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use +system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits +system.cpu.dcache.overall_hits::total 969986101 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses +system.cpu.dcache.overall_misses::total 2787983 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369162000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 67369162000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954940470 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39954940470 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 107324102470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 107324102470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 107324102470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 107324102470 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.508124 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.508124 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.989278 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.989278 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38495.249960 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38495.249960 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks +system.cpu.dcache.writebacks::total 96322 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884240500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884240500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478487500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478487500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.142233 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.142233 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.693725 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.693725 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index fd73c9f26..be7e2dd7e 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/gem5/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index dc0676551..ef0c59dbf 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 20:20:38 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 00:36:17 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 0ed850d63..3a52f894e 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026292 # Nu sim_ticks 26292466000 # Number of ticks simulated final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139577 # Simulator instruction rate (inst/s) -host_op_rate 198063 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51742306 # Simulator tick rate (ticks/s) -host_mem_usage 305460 # Number of bytes of host memory used -host_seconds 508.14 # Real time elapsed on the host +host_inst_rate 43892 # Simulator instruction rate (inst/s) +host_op_rate 62284 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16271073 # Simulator tick rate (ticks/s) +host_mem_usage 263196 # Number of bytes of host memory used +host_seconds 1615.90 # Real time elapsed on the host sim_insts 70925094 # Number of instructions simulated sim_ops 100644341 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 5127 # Tr system.physmem.perBankWrReqs::15 5151 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26292446500 # Total gap between requests +system.physmem.totGap 26292447500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4868161034 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6756433034 # Sum of mem lat for all requests +system.physmem.totQLat 4868163034 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6756435034 # Sum of mem lat for all requests system.physmem.totBusLat 515096000 # Total cycles spent in databus access system.physmem.totBankLat 1373176000 # Total cycles spent in bank access -system.physmem.avgQLat 37803.91 # Average queueing delay per request +system.physmem.avgQLat 37803.93 # Average queueing delay per request system.physmem.avgBankLat 10663.46 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52467.37 # Average memory access latency +system.physmem.avgMemAccLat 52467.38 # Average memory access latency system.physmem.avgRdBW 313.46 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 204.33 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 313.46 # Average consumed read bandwidth in MB/s @@ -246,23 +246,23 @@ system.cpu.BPredUnit.BTBHits 7769778 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 1827213 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 113597 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12549160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 12549163 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 85090933 # Number of instructions fetch has processed system.cpu.fetch.Branches 16605622 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9596991 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 21171852 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2347507 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10606958 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 10606959 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 522 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11672224 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 180779 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46048900 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.587178 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 11672225 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 180780 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46048903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.587177 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.333418 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24897026 54.07% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24897029 54.07% 54.07% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2135353 4.64% 58.70% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1967483 4.27% 62.98% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 2044942 4.44% 67.42% # Number of instructions fetched each cycle (Total) @@ -274,11 +274,11 @@ system.cpu.fetch.rateDist::8 10011040 21.74% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46048900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 46048903 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.315787 # Number of branch fetches per cycle system.cpu.fetch.rate 1.618162 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 14627644 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8956467 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 8956470 # Number of cycles decode is blocked system.cpu.decode.RunCycles 19461806 # Number of cycles decode is running system.cpu.decode.UnblockCycles 1385483 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1617500 # Number of cycles decode is squashing @@ -289,20 +289,20 @@ system.cpu.decode.SquashedInsts 360894 # Nu system.cpu.rename.SquashCycles 1617500 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 16338587 # Number of cycles rename is idle system.cpu.rename.BlockCycles 2555401 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 926852 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19086495 # Number of cycles rename is running +system.cpu.rename.serializeStallCycles 926854 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19086496 # Number of cycles rename is running system.cpu.rename.UnblockCycles 5524065 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114852318 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 114852319 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 16183 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 4665174 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 343 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115176508 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529186359 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529181674 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 115176509 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529186363 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529181678 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4685 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99160616 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16015892 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16015893 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 24809 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24798 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 13045945 # count of insts added to the skid buffer @@ -317,11 +317,11 @@ system.cpu.iq.iqSquashedInstsIssued 269260 # Nu system.cpu.iq.iqSquashedInstsExamined 10685136 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 25571717 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3727 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46048900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 46048903 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.328055 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.987613 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10795987 23.44% 23.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10795990 23.44% 23.44% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 8084539 17.56% 41.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 7444488 16.17% 57.17% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 7134852 15.49% 72.66% # Number of insts issued each cycle @@ -333,7 +333,7 @@ system.cpu.iq.issued_per_cycle::8 573509 1.25% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46048900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46048903 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 110622 4.49% 4.49% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available @@ -406,7 +406,7 @@ system.cpu.iq.FU_type_0::total 107204361 # Ty system.cpu.iq.rate 2.038690 # Inst issue rate system.cpu.iq.fu_busy_cnt 2463316 # FU busy when requested system.cpu.iq.fu_busy_rate 0.022978 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263189734 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 263189737 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 122194582 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 105533921 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 464 # Number of floating instruction queue reads @@ -429,7 +429,7 @@ system.cpu.iew.iewSquashCycles 1617500 # Nu system.cpu.iew.iewBlockCycles 1047454 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 46131 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 111491510 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 290951 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 290952 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 29582757 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 22430841 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 24336 # Number of dispatched non-speculative instructions @@ -459,11 +459,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 10842444 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37279 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 498355 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44431401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 44431403 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.265287 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.763630 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15343377 34.53% 34.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15343379 34.53% 34.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 11655601 26.23% 60.77% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 3462235 7.79% 68.56% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2874946 6.47% 75.03% # Number of insts commited each cycle @@ -475,7 +475,7 @@ system.cpu.commit.committed_per_cycle::8 6007585 13.52% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44431401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44431403 # Number of insts commited each cycle system.cpu.commit.committedInsts 70930646 # Number of instructions committed system.cpu.commit.committedOps 100649893 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -488,10 +488,10 @@ system.cpu.commit.int_insts 91486751 # Nu system.cpu.commit.function_calls 1679850 # Number of function calls committed. system.cpu.commit.bw_lim_events 6007585 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149890854 # The number of ROB reads +system.cpu.rob.rob_reads 149890856 # The number of ROB reads system.cpu.rob.rob_writes 224611140 # The number of ROB writes system.cpu.timesIdled 74350 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6536033 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 6536030 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70925094 # Number of Instructions Simulated system.cpu.committedOps 100644341 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70925094 # Number of Instructions Simulated @@ -506,12 +506,12 @@ system.cpu.fp_regfile_writes 582 # nu system.cpu.misc_regfile_reads 49170129 # number of misc regfile reads system.cpu.misc_regfile_writes 38826 # number of misc regfile writes system.cpu.icache.replacements 30543 # number of replacements -system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1820.333458 # Cycle average of tags in use system.cpu.icache.total_refs 11635566 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 32580 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 357.138306 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1820.333452 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1820.333458 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.888835 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.888835 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 11635567 # number of ReadReq hits @@ -520,36 +520,36 @@ system.cpu.icache.demand_hits::cpu.inst 11635567 # nu system.cpu.icache.demand_hits::total 11635567 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 11635567 # number of overall hits system.cpu.icache.overall_hits::total 11635567 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 36657 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 36657 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 36657 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 36657 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 36657 # number of overall misses -system.cpu.icache.overall_misses::total 36657 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 709011999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 709011999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 709011999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 709011999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 709011999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 709011999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11672224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11672224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11672224 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11672224 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11672224 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11672224 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 36658 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 36658 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 36658 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 36658 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 36658 # number of overall misses +system.cpu.icache.overall_misses::total 36658 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 709083999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 709083999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 709083999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 709083999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 709083999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 709083999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11672225 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11672225 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11672225 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11672225 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11672225 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11672225 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003141 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003141 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003141 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.003141 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.003141 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.003141 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19341.790081 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19341.790081 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19341.790081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19341.790081 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19343.226554 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19343.226554 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19343.226554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19343.226554 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked @@ -558,172 +558,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32884 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 32884 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 32884 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 32884 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 32884 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 32884 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580604499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 580604499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580604499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 580604499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580604499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 580604499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580605499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 580605499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580605499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 580605499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580605499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 580605499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002817 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.002817 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.002817 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.139734 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.139734 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.170144 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.170144 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158306 # number of replacements -system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use -system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits -system.cpu.dcache.overall_hits::total 44303188 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses -system.cpu.dcache.overall_misses::total 1709363 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks -system.cpu.dcache.writebacks::total 129052 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 95650 # number of replacements -system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30136.955699 # Cycle average of tags in use system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 126757 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.709468 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 26880.895911 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1379.489976 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1876.569805 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1379.489982 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1876.569807 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.820340 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.042099 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.057268 # Average percentage of cache occupancy @@ -756,19 +630,19 @@ system.cpu.l2cache.demand_misses::total 128851 # nu system.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124171 # number of overall misses system.cpu.l2cache.overall_misses::total 128851 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269870000 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10026730500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 269870000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9756860500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10026730500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 269871000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9756862000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10026733000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 269871000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9756862000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10026733000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 32373 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55368 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 87741 # number of ReadReq accesses(hits+misses) @@ -797,19 +671,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.661538 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144565 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.764590 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.661538 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.529915 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.727812 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.332581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.743590 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.796258 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.426584 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 77.181208 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 77.181208 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79134.349085 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79134.349085 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77816.474067 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77816.474067 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77816.493469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77816.493469 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -842,19 +716,19 @@ system.cpu.l2cache.demand_mshr_misses::total 128777 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 124113 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210181444 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210183444 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8211083763 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8421265207 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210181444 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8421267207 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210183444 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8211083763 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8421265207 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8421267207 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394759 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.302265 # mshr miss rate for ReadReq accesses @@ -868,19 +742,145 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.661158 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.661158 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45064.632075 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45065.060892 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63587.961751 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.437163 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.512575 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66707.495726 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66707.495726 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 158306 # number of replacements +system.cpu.dcache.tagsinuse 4072.986678 # Cycle average of tags in use +system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.986678 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits +system.cpu.dcache.overall_hits::total 44303188 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses +system.cpu.dcache.overall_misses::total 1709363 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670086500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4670086500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 124709259481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 124709259481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 124709259481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 124709259481 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.307299 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.307299 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72956.568898 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72956.568898 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks +system.cpu.dcache.writebacks::total 129052 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060279000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060279000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313871492 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10313871492 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313871492 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10313871492 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.809104 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.809104 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index de7e2e199..9dd6f437e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/gem5/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index e7a9dda21..0fb886b0f 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 20:33:15 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 00:51:58 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 506342716000 because target called exit() +Exiting @ tick 506577346000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 312dc8692..95290563f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.506343 # Number of seconds simulated -sim_ticks 506342716000 # Number of ticks simulated -final_tick 506342716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.506577 # Number of seconds simulated +sim_ticks 506577346000 # Number of ticks simulated +final_tick 506577346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168217 # Simulator instruction rate (inst/s) -host_op_rate 187658 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55145312 # Simulator tick rate (ticks/s) -host_mem_usage 540496 # Number of bytes of host memory used -host_seconds 9181.97 # Real time elapsed on the host -sim_insts 1544563043 # Number of instructions simulated -sim_ops 1723073855 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143751360 # Number of bytes read from this memory -system.physmem.bytes_read::total 143799104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70435456 # Number of bytes written to this memory -system.physmem.bytes_written::total 70435456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 746 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2246115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246861 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100554 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100554 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283901309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 283995601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 139106289 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 139106289 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 139106289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283901309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 423101890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246861 # Total number of read requests seen -system.physmem.writeReqs 1100554 # Total number of write requests seen -system.physmem.cpureqs 3347415 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143799104 # Total number of bytes read from memory -system.physmem.bytesWritten 70435456 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143799104 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70435456 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 613 # Number of read reqs serviced by write Q +host_inst_rate 78526 # Simulator instruction rate (inst/s) +host_op_rate 87602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25754624 # Simulator tick rate (ticks/s) +host_mem_usage 525748 # Number of bytes of host memory used +host_seconds 19669.37 # Real time elapsed on the host +sim_insts 1544563048 # Number of instructions simulated +sim_ops 1723073860 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 47872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143709504 # Number of bytes read from this memory +system.physmem.bytes_read::total 143757376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70427136 # Number of bytes written to this memory +system.physmem.bytes_written::total 70427136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245461 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246209 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100424 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100424 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283687190 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 283781691 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94501 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94501 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 139025435 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 139025435 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 139025435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283687190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 422807126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246209 # Total number of read requests seen +system.physmem.writeReqs 1100424 # Total number of write requests seen +system.physmem.cpureqs 3346633 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143757376 # Total number of bytes read from memory +system.physmem.bytesWritten 70427136 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143757376 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70427136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 648 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 139880 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 143856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141905 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 140877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 137960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141491 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 140982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 141233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 139496 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 137116 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 141034 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 138952 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 139888 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69217 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 70379 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69592 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 68832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 67727 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68464 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 68713 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68501 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 68243 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 68230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 68643 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 68550 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 67188 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70321 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69053 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68901 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 139859 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 143718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141024 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 137951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140151 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141411 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 141047 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 141131 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 139616 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140596 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 136994 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 141023 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 138860 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 140030 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 70316 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69579 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 68829 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 67740 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68386 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 68704 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68489 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 68246 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 68330 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 68656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 68488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 67093 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70319 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69051 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68913 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 506342647500 # Total gap between requests +system.physmem.totGap 506577272500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246861 # Categorize read packet sizes +system.physmem.readPktSize::6 2246209 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1100554 # categorize write packet sizes +system.physmem.writePktSize::6 1100424 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1577627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 446326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 156341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 65934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1577632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 445457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 156427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 66028 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,60 +138,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 27053022176 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102785772176 # Sum of mem lat for all requests -system.physmem.totBusLat 8984992000 # Total cycles spent in databus access -system.physmem.totBankLat 66747758000 # Total cycles spent in bank access -system.physmem.avgQLat 12043.65 # Average queueing delay per request -system.physmem.avgBankLat 29715.22 # Average bank access latency per request +system.physmem.totQLat 27034566792 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102738360792 # Sum of mem lat for all requests +system.physmem.totBusLat 8982244000 # Total cycles spent in databus access +system.physmem.totBankLat 66721550000 # Total cycles spent in bank access +system.physmem.avgQLat 12039.11 # Average queueing delay per request +system.physmem.avgBankLat 29712.64 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 45758.87 # Average memory access latency -system.physmem.avgRdBW 284.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 139.11 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 284.00 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 139.11 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 45751.76 # Average memory access latency +system.physmem.avgRdBW 283.78 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 139.03 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 283.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 139.03 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.64 # Data bus utilization in percentage system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 10.20 # Average write queue length over time -system.physmem.readRowHits 914443 # Number of row buffer hits during reads -system.physmem.writeRowHits 189193 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 17.19 # Row buffer hit rate for writes -system.physmem.avgGap 151263.78 # Average gap between requests +system.physmem.avgWrQLen 10.83 # Average write queue length over time +system.physmem.readRowHits 914455 # Number of row buffer hits during reads +system.physmem.writeRowHits 188951 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.72 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes +system.physmem.avgGap 151369.23 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,141 +235,140 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1012685433 # number of cpu cycles simulated +system.cpu.numCycles 1013154693 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 301954621 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 248216809 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 15201913 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 174080905 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 160275912 # Number of BTB hits +system.cpu.BPredUnit.lookups 302078234 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 248282516 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 15228940 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 174133457 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 160366522 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 17543051 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 217 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 296171329 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2177000343 # Number of instructions fetch has processed -system.cpu.fetch.Branches 301954621 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 177818963 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 433079666 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 86445035 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 152984584 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 67 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 286733341 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5527590 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 951199831 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.533171 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.216208 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 17581353 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 196 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 296396923 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2177678223 # Number of instructions fetch has processed +system.cpu.fetch.Branches 302078234 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 177947875 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 433295900 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 86556891 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 152970163 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 65 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 286931136 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5530103 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 951710373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.532755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.215871 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 518120232 54.47% 54.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25036737 2.63% 57.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39011944 4.10% 61.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48247673 5.07% 66.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 42552998 4.47% 70.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46316076 4.87% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38402395 4.04% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18552878 1.95% 81.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174958898 18.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 518414544 54.47% 54.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25023553 2.63% 57.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39078902 4.11% 61.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48295865 5.07% 66.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 42590853 4.48% 70.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46358394 4.87% 75.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38409844 4.04% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18541861 1.95% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174996557 18.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 951199831 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.298172 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.149730 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 327457175 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 131287653 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403449648 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20041830 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68963525 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46005772 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 694 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2358153457 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68963525 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 350605393 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61238175 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13721 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 398828619 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71550398 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2297300888 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 126992 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5036459 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58395724 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2272291937 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10608987199 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10608983762 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3437 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 565971975 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 459 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158423553 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 623142693 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220479196 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86005454 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70775057 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2196663707 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 506 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2016028881 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3978647 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 469035072 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1108322137 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 332 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 951199831 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.119459 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906333 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 951710373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.298156 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.149403 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 327700398 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 131274030 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403657963 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20031323 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69046659 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46033752 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2358943633 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2468 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69046659 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 350846153 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61254563 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16168 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 399028257 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71518573 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2298097948 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 126905 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5030989 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58378290 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 21 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2273047323 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10612493947 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10612490107 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3840 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319970 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 566727353 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 579 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 576 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158294547 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 623264205 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220545745 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86083879 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71111807 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2197176983 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 617 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2016362984 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3976433 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 469561245 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1109303126 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 442 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 951710373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.118673 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906088 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 271401880 28.53% 28.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 150954811 15.87% 44.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160752249 16.90% 61.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119324059 12.54% 73.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124037458 13.04% 86.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73914082 7.77% 94.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38408733 4.04% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9827717 1.03% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2578842 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 271681104 28.55% 28.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151029292 15.87% 44.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160860951 16.90% 61.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119423719 12.55% 73.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124040655 13.03% 86.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73844505 7.76% 94.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38423887 4.04% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9837914 1.03% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2568346 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 951199831 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 951710373 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 872713 3.66% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5800 0.02% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18252533 76.46% 80.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4741041 19.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 884251 3.71% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5803 0.02% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18260912 76.52% 80.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4713024 19.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1235530867 61.29% 61.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 926678 0.05% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1235730188 61.29% 61.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925294 0.05% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued @@ -391,164 +390,164 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 64 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 25 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 11 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 27 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 13 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 586539458 29.09% 90.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193031781 9.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 586669934 29.10% 90.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193037461 9.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2016028881 # Type of FU issued -system.cpu.iq.rate 1.990775 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23872087 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011841 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5011107955 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2665888919 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1956633156 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 668 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 148 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2039900782 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 186 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64729425 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2016362984 # Type of FU issued +system.cpu.iq.rate 1.990183 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23863990 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011835 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5012276382 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2666928163 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1956898360 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 382 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 744 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2040226783 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 191 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64738379 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 137215920 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 273705 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192829 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45632147 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 137337431 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 268034 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192473 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45698695 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3804190 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 3808296 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68963525 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27139108 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1495868 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2196664320 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6096220 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 623142693 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220479196 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 440 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 474677 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 89373 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192829 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8139641 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9611816 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17751457 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986428018 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573006458 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29600863 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69046659 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27170871 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1494320 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2197177695 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6112052 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 623264205 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220545745 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 552 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 473344 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 89494 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192473 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8164015 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9611639 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17775654 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986719031 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573114745 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29643953 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 107 # number of nop insts executed -system.cpu.iew.exec_refs 763162577 # number of memory reference insts executed -system.cpu.iew.exec_branches 238305506 # Number of branches executed -system.cpu.iew.exec_stores 190156119 # Number of stores executed -system.cpu.iew.exec_rate 1.961545 # Inst execution rate -system.cpu.iew.wb_sent 1965069993 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1956633304 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295741844 # num instructions producing a value -system.cpu.iew.wb_consumers 2060291868 # num instructions consuming a value +system.cpu.iew.exec_nop 95 # number of nop insts executed +system.cpu.iew.exec_refs 763276448 # number of memory reference insts executed +system.cpu.iew.exec_branches 238352176 # Number of branches executed +system.cpu.iew.exec_stores 190161703 # Number of stores executed +system.cpu.iew.exec_rate 1.960924 # Inst execution rate +system.cpu.iew.wb_sent 1965347769 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1956898514 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295796153 # num instructions producing a value +system.cpu.iew.wb_consumers 2060480328 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.932123 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628912 # average fanout of values written-back +system.cpu.iew.wb_rate 1.931490 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628881 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 473688675 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15201254 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 882236307 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.953075 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.733441 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 474201695 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 175 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15228277 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 882663714 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.952130 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.732822 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 395033936 44.78% 44.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192005187 21.76% 66.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72432268 8.21% 74.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35243986 3.99% 78.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18949129 2.15% 80.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30789454 3.49% 84.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20064460 2.27% 86.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11401450 1.29% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106316437 12.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 395325741 44.79% 44.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192113195 21.77% 66.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72479892 8.21% 74.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35250909 3.99% 78.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18971392 2.15% 80.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30754959 3.48% 84.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20068273 2.27% 86.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11416653 1.29% 87.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106282700 12.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 882236307 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563061 # Number of instructions committed -system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 882663714 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563066 # Number of instructions committed +system.cpu.commit.committedOps 1723073878 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773822 # Number of memory references committed -system.cpu.commit.loads 485926773 # Number of loads committed +system.cpu.commit.refs 660773824 # Number of memory references committed +system.cpu.commit.loads 485926774 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462430 # Number of branches committed +system.cpu.commit.branches 213462431 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941861 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106316437 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106282700 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2972681819 # The number of ROB reads -system.cpu.rob.rob_writes 4462636284 # The number of ROB writes -system.cpu.timesIdled 1007749 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61485602 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563043 # Number of Instructions Simulated -system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated -system.cpu.cpi 0.655645 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.655645 # CPI: Total CPI of All Threads -system.cpu.ipc 1.525215 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.525215 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9949187154 # number of integer regfile reads -system.cpu.int_regfile_writes 1936551418 # number of integer regfile writes -system.cpu.fp_regfile_reads 155 # number of floating regfile reads -system.cpu.fp_regfile_writes 154 # number of floating regfile writes -system.cpu.misc_regfile_reads 737521382 # number of misc regfile reads -system.cpu.misc_regfile_writes 132 # number of misc regfile writes -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 625.107966 # Cycle average of tags in use -system.cpu.icache.total_refs 286732187 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 775 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 369977.015484 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2973655988 # The number of ROB reads +system.cpu.rob.rob_writes 4463745378 # The number of ROB writes +system.cpu.timesIdled 1007703 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 61444320 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563048 # Number of Instructions Simulated +system.cpu.committedOps 1723073860 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563048 # Number of Instructions Simulated +system.cpu.cpi 0.655949 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.655949 # CPI: Total CPI of All Threads +system.cpu.ipc 1.524509 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.524509 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9950552971 # number of integer regfile reads +system.cpu.int_regfile_writes 1936868290 # number of integer regfile writes +system.cpu.fp_regfile_reads 164 # number of floating regfile reads +system.cpu.fp_regfile_writes 170 # number of floating regfile writes +system.cpu.misc_regfile_reads 737621516 # number of misc regfile reads +system.cpu.misc_regfile_writes 134 # number of misc regfile writes +system.cpu.icache.replacements 23 # number of replacements +system.cpu.icache.tagsinuse 625.920238 # Cycle average of tags in use +system.cpu.icache.total_refs 286929961 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 368331.143774 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 625.107966 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305228 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305228 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 286732187 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286732187 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286732187 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286732187 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286732187 # number of overall hits -system.cpu.icache.overall_hits::total 286732187 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses -system.cpu.icache.overall_misses::total 1154 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 59543000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 59543000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 59543000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 59543000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 59543000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 59543000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286733341 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286733341 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286733341 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286733341 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286733341 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286733341 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 625.920238 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.305625 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.305625 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 286929961 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 286929961 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 286929961 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 286929961 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 286929961 # number of overall hits +system.cpu.icache.overall_hits::total 286929961 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1175 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1175 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1175 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1175 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1175 # number of overall misses +system.cpu.icache.overall_misses::total 1175 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61332500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61332500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61332500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61332500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61332500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61332500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 286931136 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 286931136 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 286931136 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 286931136 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 286931136 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 286931136 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51597.053726 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51597.053726 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51597.053726 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51597.053726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51597.053726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51597.053726 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52197.872340 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52197.872340 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52197.872340 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52197.872340 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52197.872340 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52197.872340 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -557,246 +556,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 69 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 379 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 379 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 379 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 379 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 379 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41824000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 41824000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41824000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 41824000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41824000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 41824000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 396 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 396 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 779 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 779 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 779 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 779 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 779 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 779 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42649000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42649000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42649000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42649000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42649000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42649000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53966.451613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53966.451613 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54748.395379 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54748.395379 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54748.395379 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54748.395379 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54748.395379 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54748.395379 # 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number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167053904 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 87 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 87 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 655966804 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 655966804 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 655966804 # number of overall hits -system.cpu.dcache.overall_hits::total 655966804 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11479195 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11479195 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5532143 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5532143 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17011338 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17011338 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17011338 # number of overall misses -system.cpu.dcache.overall_misses::total 17011338 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 299504228000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 299504228000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 217114926916 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 217114926916 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 187000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 516619154916 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 516619154916 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 516619154916 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 516619154916 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500392095 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500392095 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 90 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 90 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 672978142 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 672978142 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 672978142 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 672978142 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022940 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022940 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032054 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032054 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025278 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025278 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025278 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025278 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26091.048022 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26091.048022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39246.080030 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39246.080030 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30369.107646 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30369.107646 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19754018 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 992148 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1171998 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.854993 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15.371892 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781955 # number of writebacks -system.cpu.dcache.writebacks::total 3781955 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3770552 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3770552 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638638 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3638638 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7409190 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7409190 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7409190 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7409190 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708643 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708643 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893505 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893505 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9602148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9602148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9602148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9602148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170578712500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 170578712500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71843645589 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71843645589 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242422358089 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 242422358089 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242422358089 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 242422358089 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22128.241313 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22128.241313 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.147282 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.147282 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25246.680023 # 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Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.520910 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.962025 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6288951 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6288979 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3781955 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3781955 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1067075 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1067075 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7356026 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7356054 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 28 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69852.138263 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69847.056281 # average overall miss latency +system.cpu.l2cache.replacements 2213514 # number of replacements +system.cpu.l2cache.tagsinuse 31523.929913 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9246342 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2243293 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.121772 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 20414306502 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14436.839849 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 20.727036 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17066.363028 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440577 # 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average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3781738 # number of writebacks +system.cpu.dcache.writebacks::total 3781738 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3765084 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3765084 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638812 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3638812 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7403896 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7403896 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7403896 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7403896 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707851 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7707851 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893572 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893572 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601423 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601423 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601423 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601423 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170518232500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 170518232500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71841286448 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71841286448 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242359518948 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 242359518948 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242359518948 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 242359518948 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22122.668497 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22122.668497 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37939.558912 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37939.558912 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25242.041617 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25242.041617 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25242.041617 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25242.041617 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 203e11af7..27d1e0868 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/gem5/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index df8c6714b..1d7c1b114 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 20:48:26 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 01:10:37 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 144145b4f..9ba7feff2 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.074245 # Nu sim_ticks 74245032000 # Number of ticks simulated final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131550 # Simulator instruction rate (inst/s) -host_op_rate 144033 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56674428 # Simulator tick rate (ticks/s) -host_mem_usage 280244 # Number of bytes of host memory used -host_seconds 1310.03 # Real time elapsed on the host +host_inst_rate 44193 # Simulator instruction rate (inst/s) +host_op_rate 48386 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19039219 # Simulator tick rate (ticks/s) +host_mem_usage 236076 # Number of bytes of host memory used +host_seconds 3899.58 # Real time elapsed on the host sim_insts 172333441 # Number of instructions simulated sim_ops 188686923 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74245012500 # Total gap between requests +system.physmem.totGap 74245013500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 12366785 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 86366785 # Sum of mem lat for all requests +system.physmem.totQLat 12368785 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 86368785 # Sum of mem lat for all requests system.physmem.totBusLat 15172000 # Total cycles spent in databus access system.physmem.totBankLat 58828000 # Total cycles spent in bank access -system.physmem.avgQLat 3260.42 # Average queueing delay per request +system.physmem.avgQLat 3260.95 # Average queueing delay per request system.physmem.avgBankLat 15509.62 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22770.05 # Average memory access latency +system.physmem.avgMemAccLat 22770.57 # Average memory access latency system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s @@ -184,7 +184,7 @@ system.physmem.readRowHits 3295 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19574218.96 # Average gap between requests +system.physmem.avgGap 19574219.22 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -239,24 +239,24 @@ system.cpu.BPredUnit.BTBHits 43068728 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 39671704 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 39671705 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7321256 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 7321257 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36859860 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1828379 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148388373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36859861 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1828380 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148388374 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68164460 45.94% 45.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68164461 45.94% 45.94% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total) @@ -268,11 +268,11 @@ system.cpu.fetch.rateDist::8 24661769 16.62% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148388373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 148388374 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5988328 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 5988329 # Number of cycles decode is blocked system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing @@ -284,19 +284,19 @@ system.cpu.rename.SquashCycles 20843724 # Nu system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70572280 # Number of cycles rename is running +system.cpu.rename.RunCycles 70572281 # Number of cycles rename is running system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371457492 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 371457493 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631852668 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1582346867 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1565037376 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 631852669 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1582346871 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1565037380 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333759857 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 333759858 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer @@ -311,11 +311,11 @@ system.cpu.iq.iqSquashedInstsIssued 795533 # Nu system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148388373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 148388374 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56153945 37.84% 37.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56153946 37.84% 37.84% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle @@ -327,7 +327,7 @@ system.cpu.iq.issued_per_cycle::8 180612 0.12% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148388373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148388374 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available @@ -400,7 +400,7 @@ system.cpu.iq.FU_type_0::total 249531465 # Ty system.cpu.iq.rate 1.680459 # Inst issue rate system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 647013011 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 647013012 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads @@ -423,7 +423,7 @@ system.cpu.iew.iewSquashCycles 20843724 # Nu system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 786985 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 786986 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions @@ -485,7 +485,7 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 449048801 # The number of ROB reads system.cpu.rob.rob_writes 679713725 # The number of ROB writes system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 101692 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 101691 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172333441 # Number of Instructions Simulated system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated @@ -500,12 +500,12 @@ system.cpu.fp_regfile_writes 2497505 # nu system.cpu.misc_regfile_reads 54528814 # number of misc regfile reads system.cpu.misc_regfile_writes 832204 # number of misc regfile writes system.cpu.icache.replacements 2508 # number of replacements -system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1347.136600 # Cycle average of tags in use system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1347.136586 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1347.136600 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits @@ -514,36 +514,36 @@ system.cpu.icache.demand_hits::cpu.inst 36854521 # nu system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits system.cpu.icache.overall_hits::total 36854521 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5339 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5339 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5339 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5339 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5339 # number of overall misses -system.cpu.icache.overall_misses::total 5339 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 158626499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 158626499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 158626499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 158626499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 158626499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 158626499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36859860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36859860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36859860 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36859860 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36859860 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36859860 # 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miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29710.900730 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29710.900730 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29710.900730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29710.900730 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29718.632772 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29718.632772 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29718.632772 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29718.632772 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked @@ -552,12 +552,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 35.529412 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1102 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1102 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1102 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1102 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1102 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1102 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1103 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1103 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1103 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1103 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1103 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1103 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4237 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4237 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4237 # number of demand (read+write) MSHR misses @@ -583,141 +583,15 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 28969.199670 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use -system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits -system.cpu.dcache.overall_hits::total 46746842 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses -system.cpu.dcache.overall_misses::total 9552 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 18 # number of writebacks -system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 1961.084990 # Cycle average of tags in use system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2727 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.834250 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 4.022996 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1424.044648 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 533.017329 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1424.044661 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 533.017333 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.043458 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy @@ -749,16 +623,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 2051 # system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses system.cpu.l2cache.overall_misses::total 3807 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 96653500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35087500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 131741000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35089000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 131742500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46197000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 46197000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 96653500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 81284500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 177938000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 81286000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 177939500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 96653500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 81284500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 177938000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 81286000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 177939500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4235 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 771 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5006 # number of ReadReq accesses(hits+misses) @@ -788,16 +662,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484298 system.cpu.l2cache.overall_miss_rate::cpu.data 0.947141 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.625226 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47125.060946 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51523.494860 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.449488 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51525.697504 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.998536 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42973.953488 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42973.953488 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46739.690045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46740.084056 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46739.690045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46740.084056 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -828,19 +702,19 @@ system.cpu.l2cache.demand_mshr_misses::total 3793 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2048 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3793 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70387399 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26266459 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96653858 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70388399 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26267459 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96655858 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32716158 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32716158 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70387399 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58982617 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 129370016 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70387399 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58982617 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 129370016 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70388399 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58983617 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 129372016 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70388399 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58983617 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 129372016 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869001 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.542948 # mshr miss rate for ReadReq accesses @@ -854,19 +728,145 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.622927 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.622927 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34368.847168 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39203.670149 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35560.654157 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34369.335449 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39205.162687 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35561.389993 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30433.635349 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30433.635349 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1406.445410 # Cycle average of tags in use +system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 1406.445410 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits +system.cpu.dcache.overall_hits::total 46746842 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses +system.cpu.dcache.overall_misses::total 9552 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 82599500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 82599500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 375319996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 375319996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 375319996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 375319996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45062.465903 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45062.465903 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39292.294389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39292.294389 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 18 # number of writebacks +system.cpu.dcache.writebacks::total 18 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36782500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36782500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84192998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 84192998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84192998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 84192998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47707.522698 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47707.522698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 7edece479..0c6ed2a4b 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -433,21 +430,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -464,6 +456,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -483,21 +478,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -524,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/gem5/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 248fa6c54..e62279342 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2012 00:35:18 -gem5 started Dec 30 2012 00:48:42 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jan 4 2013 21:20:54 +gem5 started Jan 4 2013 23:04:52 +gem5 executing on u200540 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 5da80c53d..92132dbec 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.082648 # Nu sim_ticks 82648140000 # Number of ticks simulated final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58118 # Simulator instruction rate (inst/s) -host_op_rate 97410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36369167 # Simulator tick rate (ticks/s) -host_mem_usage 286740 # Number of bytes of host memory used -host_seconds 2272.48 # Real time elapsed on the host +host_inst_rate 31465 # Simulator instruction rate (inst/s) +host_op_rate 52738 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19690094 # Simulator tick rate (ticks/s) +host_mem_usage 268216 # Number of bytes of host memory used +host_seconds 4197.45 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 82648108000 # Total gap between requests +system.physmem.totGap 82648109000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 16873322 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 122447322 # Sum of mem lat for all requests +system.physmem.totQLat 16873822 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests system.physmem.totBusLat 21392000 # Total cycles spent in databus access system.physmem.totBankLat 84182000 # Total cycles spent in bank access -system.physmem.avgQLat 3155.07 # Average queueing delay per request +system.physmem.avgQLat 3155.16 # Average queueing delay per request system.physmem.avgBankLat 15740.84 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22895.91 # Average memory access latency +system.physmem.avgMemAccLat 22896.00 # Average memory access latency system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s @@ -184,7 +184,7 @@ system.physmem.readRowHits 4742 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15454021.69 # Average gap between requests +system.physmem.avgGap 15454021.88 # Average gap between requests system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 165296281 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -197,18 +197,18 @@ system.cpu.BPredUnit.BTBHits 13098591 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 25830999 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24446052 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 431778 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total) @@ -454,12 +454,12 @@ system.cpu.fp_regfile_writes 2230055 # nu system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes system.cpu.icache.replacements 4732 # number of replacements -system.cpu.icache.tagsinuse 1624.168421 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1624.168421 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits @@ -468,36 +468,36 @@ system.cpu.icache.demand_hits::cpu.inst 24437101 # nu system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits system.cpu.icache.overall_hits::total 24437101 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8951 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8951 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8951 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8951 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8951 # number of overall misses -system.cpu.icache.overall_misses::total 8951 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259393998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259393998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259393998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259393998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259393998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259393998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24446052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24446052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24446052 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24446052 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24446052 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24446052 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses +system.cpu.icache.overall_misses::total 8952 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28979.331695 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28979.331695 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28979.331695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28979.331695 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28984.137399 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28984.137399 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28984.137399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28984.137399 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 676 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -506,154 +506,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 32.190476 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2096 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2096 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2096 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2096 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2096 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2096 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2097 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2097 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2097 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2097 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2097 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2097 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 6855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 6855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 6855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198301998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 198301998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198301998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 198301998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198301998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 198301998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000280 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000280 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000280 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.081400 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.081400 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.227279 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.227279 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 55 # number of replacements -system.cpu.dcache.tagsinuse 1411.367255 # Cycle average of tags in use -system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1411.367255 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67560798 # 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number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.912769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.912769 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45363.111819 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45363.111819 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # 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mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53895.683453 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53895.683453 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2509.913634 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2509.913640 # Cycle average of tags in use system.cpu.l2cache.total_refs 3332 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3792 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.878692 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 0.902701 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2234.774408 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 274.236525 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2234.774413 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 274.236526 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000028 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.068200 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.008369 # Average percentage of cache occupancy @@ -684,17 +576,17 @@ system.cpu.l2cache.demand_misses::total 5348 # nu system.cpu.l2cache.overall_misses::cpu.inst 3402 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1946 # number of overall misses system.cpu.l2cache.overall_misses::total 5348 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158303000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 179980500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158304000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 179981000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68234000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 68234000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 158303000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 89911500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 248214500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 158303000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 89911500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 248214500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 158304000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 89911000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 248215000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 158304000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 89911000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 248215000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6701 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 416 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7117 # number of ReadReq accesses(hits+misses) @@ -723,17 +615,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.615845 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.507685 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.981341 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.615845 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.333921 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56159.326425 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.331573 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.627866 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56158.031088 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.463569 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43739.743590 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43739.743590 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46412.584144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46412.584144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46412.677636 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46412.677636 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,18 +647,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5348 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3402 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1946 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5348 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394483 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844598 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394983 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844098 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132239081 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1540154 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1540154 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48432493 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48432493 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394483 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65277091 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394983 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65276591 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 180671574 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394483 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65277091 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394983 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65276591 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 180671574 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927885 # mshr miss rate for ReadReq accesses @@ -781,19 +673,127 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.615845 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.615845 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.601117 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43638.854922 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.748089 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43637.559585 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34910.000264 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31046.469872 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31046.469872 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.748089 # 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Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits +system.cpu.dcache.overall_hits::total 67560798 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses +system.cpu.dcache.overall_misses::total 2513 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37144000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113997000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113997000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113997000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113997000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 14 # number of writebacks +system.cpu.dcache.writebacks::total 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |